* [U-Boot] [PATCH 00/13] ARM: uniphier: a collection of clean-ups and new clock driver
@ 2016-02-02 12:11 Masahiro Yamada
2016-02-02 12:11 ` [U-Boot] [PATCH 01/13] ARM: uniphier: change stack pointer address for SPL Masahiro Yamada
` (13 more replies)
0 siblings, 14 replies; 16+ messages in thread
From: Masahiro Yamada @ 2016-02-02 12:11 UTC (permalink / raw)
To: u-boot
Masahiro Yamada (13):
ARM: uniphier: change stack pointer address for SPL
ARM: uniphier: create early page table at run-time
ARM: uniphier: add missing static qualifier
ARM: uniphier: support USB boot mode for ProXstream2 / PH1-LD6b SoC
clk: uniphier: add Media I/O clock driver for UniPhier SoCs
ARM: dts: uniphier: add reference clock nodes
ARM: dts: uniphier: add device nodes for system control blocks
ARM: dts: uniphier: add device nodes for Peripheral control block
ARM: dts: uniphier: add device nodes for MIO control block
ARM: dts: uniphier: switch to use clock drivers
usb: remove UniPhier EHCI driver
ARM: uniphier: enable generic EHCI driver
ARM: uniphier: drop unneeded EHCI pin mux settings
arch/arm/Kconfig | 1 +
arch/arm/dts/uniphier-common32.dtsi | 27 ++++
arch/arm/dts/uniphier-ph1-ld4.dtsi | 23 +++
arch/arm/dts/uniphier-ph1-pro4.dtsi | 22 +++
arch/arm/dts/uniphier-ph1-pro5.dtsi | 20 +++
arch/arm/dts/uniphier-ph1-sld3.dtsi | 26 +++
arch/arm/dts/uniphier-ph1-sld8.dtsi | 23 +++
arch/arm/dts/uniphier-proxstream2.dtsi | 20 +++
arch/arm/mach-uniphier/Makefile | 1 -
arch/arm/mach-uniphier/board_late_init.c | 8 +-
arch/arm/mach-uniphier/boot-mode/boot-device.h | 2 +
.../boot-mode/boot-mode-proxstream2.c | 5 +-
arch/arm/mach-uniphier/boot-mode/boot-mode.c | 11 +-
arch/arm/mach-uniphier/clk/clk-ph1-ld4.c | 4 +-
arch/arm/mach-uniphier/clk/clk-ph1-pro4.c | 4 +-
arch/arm/mach-uniphier/init_page_table.S | 32 ----
arch/arm/mach-uniphier/lowlevel_init.S | 103 +++++++++++-
arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c | 9 --
arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c | 7 -
arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c | 2 +-
arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c | 9 --
configs/uniphier_ld4_sld8_defconfig | 2 +
configs/uniphier_sld3_defconfig | 2 +
drivers/clk/Kconfig | 2 +
drivers/clk/Makefile | 1 +
drivers/clk/uniphier/Kconfig | 13 ++
drivers/clk/uniphier/Makefile | 3 +
drivers/clk/uniphier/clk-uniphier-core.c | 159 ++++++++++++++++++
drivers/clk/uniphier/clk-uniphier-mio.c | 178 +++++++++++++++++++++
drivers/clk/uniphier/clk-uniphier.h | 57 +++++++
drivers/usb/host/Kconfig | 7 -
drivers/usb/host/Makefile | 1 -
drivers/usb/host/ehci-uniphier.c | 75 ---------
include/configs/uniphier.h | 2 +-
34 files changed, 703 insertions(+), 158 deletions(-)
delete mode 100644 arch/arm/mach-uniphier/init_page_table.S
create mode 100644 drivers/clk/uniphier/Kconfig
create mode 100644 drivers/clk/uniphier/Makefile
create mode 100644 drivers/clk/uniphier/clk-uniphier-core.c
create mode 100644 drivers/clk/uniphier/clk-uniphier-mio.c
create mode 100644 drivers/clk/uniphier/clk-uniphier.h
delete mode 100644 drivers/usb/host/ehci-uniphier.c
--
1.9.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH 01/13] ARM: uniphier: change stack pointer address for SPL
2016-02-02 12:11 [U-Boot] [PATCH 00/13] ARM: uniphier: a collection of clean-ups and new clock driver Masahiro Yamada
@ 2016-02-02 12:11 ` Masahiro Yamada
2016-02-02 12:11 ` [U-Boot] [PATCH 02/13] ARM: uniphier: create early page table at run-time Masahiro Yamada
` (12 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Masahiro Yamada @ 2016-02-02 12:11 UTC (permalink / raw)
To: u-boot
No special reason for the current stack address 0x0ff08000.
Change it to 0x00100000 to simplify the init_page_table.
There are two types of SoCs in terms of the load address of SPL.
[1] PH1-sLD3, PH1-LD4, PH1-sLD8
SPL is loaded at 0x00040000-0x0004ffff
[2] PH1-Pro4, PH1-Pro5, ProXstream2, PH1-LD6b
SPL is loaded at 0x00100000-0x0010ffff
The new stack area (0x000f8000-0x00100000) should be safe for all the
cases.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
arch/arm/mach-uniphier/init_page_table.S | 5 +----
include/configs/uniphier.h | 2 +-
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-uniphier/init_page_table.S b/arch/arm/mach-uniphier/init_page_table.S
index 2d3ad15..4ed2656 100644
--- a/arch/arm/mach-uniphier/init_page_table.S
+++ b/arch/arm/mach-uniphier/init_page_table.S
@@ -13,15 +13,12 @@
#define DEVICE 0x00002002 /* Non-shareable Device */
#define NORMAL 0x0000000e /* Normal Memory Write-Back, No Write-Allocate */
-#define TEXT_SECTION ((CONFIG_SPL_TEXT_BASE) >> (SECTION_SHIFT))
-#define STACK_SECTION ((CONFIG_SPL_STACK) >> (SECTION_SHIFT))
-
.section ".rodata"
.align 14
ENTRY(init_page_table)
section = 0
.rept NR_SECTIONS
- .if section == 0 || section == 1 || section == STACK_SECTION
+ .if section == 0 || section == 1
attr = NORMAL
.else
attr = DEVICE
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index 8856044..93e1919 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -252,7 +252,7 @@
#define CONFIG_SPL_TEXT_BASE 0x00100000
#endif
-#define CONFIG_SPL_STACK (0x0ff08000)
+#define CONFIG_SPL_STACK (0x00100000)
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE)
#define CONFIG_PANIC_HANG
--
1.9.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH 02/13] ARM: uniphier: create early page table at run-time
2016-02-02 12:11 [U-Boot] [PATCH 00/13] ARM: uniphier: a collection of clean-ups and new clock driver Masahiro Yamada
2016-02-02 12:11 ` [U-Boot] [PATCH 01/13] ARM: uniphier: change stack pointer address for SPL Masahiro Yamada
@ 2016-02-02 12:11 ` Masahiro Yamada
2016-02-02 12:11 ` [U-Boot] [PATCH 03/13] ARM: uniphier: add missing static qualifier Masahiro Yamada
` (11 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Masahiro Yamada @ 2016-02-02 12:11 UTC (permalink / raw)
To: u-boot
UniPhier SoCs are not equipped with dedicated on-chip SRAM. Instead,
locked outer cache is used as RAM area during the early boot stage
where DRAM is not ready yet. This effectively means MMU must be
always enabled while we are in SPL.
Currently, the SPL image for UniPhier SoCs contains the page table
statically defined at compile time. It has been a burden because the
16KB page table occupies a quarter memory footprint of the 64KB SPL
image.
Finally, there is no more room to implement new features in SPL.
Setting aside the NOR boot mode, this issue can be solved by creating
the page table onto RAM at run time.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
arch/arm/mach-uniphier/Makefile | 1 -
arch/arm/mach-uniphier/init_page_table.S | 29 ---------
arch/arm/mach-uniphier/lowlevel_init.S | 103 ++++++++++++++++++++++++++++---
3 files changed, 95 insertions(+), 38 deletions(-)
delete mode 100644 arch/arm/mach-uniphier/init_page_table.S
diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile
index ea3ae54..491e78e 100644
--- a/arch/arm/mach-uniphier/Makefile
+++ b/arch/arm/mach-uniphier/Makefile
@@ -5,7 +5,6 @@
ifdef CONFIG_SPL_BUILD
obj-y += lowlevel_init.o
-obj-y += init_page_table.o
obj-y += init/ bcu/ memconf/ pll/ early-clk/ early-pinctrl/ dram/
obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc/
diff --git a/arch/arm/mach-uniphier/init_page_table.S b/arch/arm/mach-uniphier/init_page_table.S
deleted file mode 100644
index 4ed2656..0000000
--- a/arch/arm/mach-uniphier/init_page_table.S
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <linux/linkage.h>
-
-/* page table */
-#define NR_SECTIONS 4096
-#define SECTION_SHIFT 20
-#define DEVICE 0x00002002 /* Non-shareable Device */
-#define NORMAL 0x0000000e /* Normal Memory Write-Back, No Write-Allocate */
-
- .section ".rodata"
- .align 14
-ENTRY(init_page_table)
- section = 0
- .rept NR_SECTIONS
- .if section == 0 || section == 1
- attr = NORMAL
- .else
- attr = DEVICE
- .endif
- .word (section << SECTION_SHIFT) | attr
- section = section + 1
- .endr
-END(init_page_table)
diff --git a/arch/arm/mach-uniphier/lowlevel_init.S b/arch/arm/mach-uniphier/lowlevel_init.S
index 2913370..c23e0d1 100644
--- a/arch/arm/mach-uniphier/lowlevel_init.S
+++ b/arch/arm/mach-uniphier/lowlevel_init.S
@@ -29,12 +29,16 @@ ENTRY(lowlevel_init)
bl debug_ll_init
#endif
+ bl setup_init_ram @ RAM area for stack and page talbe
+
/*
* Now we are using the page table embedded in the Boot ROM.
* It is not handy since it is not a straight mapped table for sLD3.
- * What we need to do next is to switch over to the page table in SPL.
+ * Also, the access to the external bus is prohibited. What we need
+ * to do next is to create a page table and switch over to it.
*/
- ldr r3, =init_page_table @ page table must be 16KB aligned
+ bl create_page_table
+ bl v7_flush_dcache_all
/* Disable MMU and Dcache before switching Page Table */
mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
@@ -43,8 +47,6 @@ ENTRY(lowlevel_init)
bl enable_mmu
- bl setup_init_ram @ RAM area for temporary stack pointer
-
mov lr, r8 @ restore link
mov pc, lr @ back to my caller
ENDPROC(lowlevel_init)
@@ -55,7 +57,7 @@ ENTRY(enable_mmu)
orr r0, r0, #0x20 @ disable TTBR1
mcr p15, 0, r0, c2, c0, 2
- orr r0, r3, #0x8 @ Outer Cacheability for table walks: WBWA
+ orr r0, r12, #0x8 @ Outer Cacheability for table walks: WBWA
mcr p15, 0, r0, c2, c0, 0 @ TTBR0
mov r0, #0
@@ -82,8 +84,9 @@ ENDPROC(enable_mmu)
* For PH1-Pro4 or older SoCs, the size of WAY is 32KB.
* It is large enough for tmp RAM.
*/
-#define BOOT_RAM_SIZE (SZ_32K)
-#define BOOT_WAY_BITS (0x00000100) /* way 8 */
+#define BOOT_RAM_SIZE (SZ_32K)
+#define BOOT_RAM_BASE ((CONFIG_SPL_STACK) - (BOOT_RAM_SIZE))
+#define BOOT_WAY_BITS (0x00000100) /* way 8 */
ENTRY(setup_init_ram)
/*
@@ -96,7 +99,7 @@ ENTRY(setup_init_ram)
ldr r0, = 0x00408006 @ touch to zero with address range
ldr r1, = SSCOQM
str r0, [r1]
- ldr r0, = (CONFIG_SPL_STACK - BOOT_RAM_SIZE) @ base address
+ ldr r0, = BOOT_RAM_BASE
ldr r1, = SSCOQAD
str r0, [r1]
ldr r0, = BOOT_RAM_SIZE
@@ -119,3 +122,87 @@ ENTRY(setup_init_ram)
mov pc, lr
ENDPROC(setup_init_ram)
+
+/* page table */
+#define DEVICE 0x00002002 /* Non-shareable Device */
+#define NORMAL 0x0000000e /* Normal Memory Write-Back, No Write-Allocate */
+
+ENTRY(create_page_table)
+ ldr r0, = DEVICE
+ ldr r1, = BOOT_RAM_BASE
+ mov r12, r1 @ r12 is preserved during D-cache flush
+0: str r0, [r1], #4 @ specify all the sections as Device
+ adds r0, r0, #0x00100000
+ bcc 0b
+
+ ldr r0, = NORMAL
+ str r0, [r12] @ mark the first section as Normal
+ add r0, r0, #0x00100000
+ str r0, [r12, #4] @ mark the second section as Normal
+ mov pc, lr
+ENDPROC(create_page_table)
+
+/* We don't use Thumb instructions for now */
+#define ARM(x...) x
+#define THUMB(x...)
+
+/*
+ * v7_flush_dcache_all()
+ *
+ * Flush the whole D-cache.
+ *
+ * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
+ *
+ * - mm - mm_struct describing address space
+ *
+ * Note: copied from arch/arm/mm/cache-v7.S of Linux 4.4
+ */
+ENTRY(v7_flush_dcache_all)
+ dmb @ ensure ordering with previous memory accesses
+ mrc p15, 1, r0, c0, c0, 1 @ read clidr
+ mov r3, r0, lsr #23 @ move LoC into position
+ ands r3, r3, #7 << 1 @ extract LoC*2 from clidr
+ beq finished @ if loc is 0, then no need to clean
+start_flush_levels:
+ mov r10, #0 @ start clean at cache level 0
+flush_levels:
+ add r2, r10, r10, lsr #1 @ work out 3x current cache level
+ mov r1, r0, lsr r2 @ extract cache type bits from clidr
+ and r1, r1, #7 @ mask of the bits for current cache only
+ cmp r1, #2 @ see what cache we have@this level
+ blt skip @ skip if no cache, or just i-cache
+ mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
+ isb @ isb to sych the new cssr&csidr
+ mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
+ and r2, r1, #7 @ extract the length of the cache lines
+ add r2, r2, #4 @ add 4 (line length offset)
+ movw r4, #0x3ff
+ ands r4, r4, r1, lsr #3 @ find maximum number on the way size
+ clz r5, r4 @ find bit position of way size increment
+ movw r7, #0x7fff
+ ands r7, r7, r1, lsr #13 @ extract max number of the index size
+loop1:
+ mov r9, r7 @ create working copy of max index
+loop2:
+ ARM( orr r11, r10, r4, lsl r5 ) @ factor way and cache number into r11
+ THUMB( lsl r6, r4, r5 )
+ THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
+ ARM( orr r11, r11, r9, lsl r2 ) @ factor index number into r11
+ THUMB( lsl r6, r9, r2 )
+ THUMB( orr r11, r11, r6 ) @ factor index number into r11
+ mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
+ subs r9, r9, #1 @ decrement the index
+ bge loop2
+ subs r4, r4, #1 @ decrement the way
+ bge loop1
+skip:
+ add r10, r10, #2 @ increment cache number
+ cmp r3, r10
+ bgt flush_levels
+finished:
+ mov r10, #0 @ swith back to cache level 0
+ mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
+ dsb st
+ isb
+ mov pc, lr
+ENDPROC(v7_flush_dcache_all)
--
1.9.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH 03/13] ARM: uniphier: add missing static qualifier
2016-02-02 12:11 [U-Boot] [PATCH 00/13] ARM: uniphier: a collection of clean-ups and new clock driver Masahiro Yamada
2016-02-02 12:11 ` [U-Boot] [PATCH 01/13] ARM: uniphier: change stack pointer address for SPL Masahiro Yamada
2016-02-02 12:11 ` [U-Boot] [PATCH 02/13] ARM: uniphier: create early page table at run-time Masahiro Yamada
@ 2016-02-02 12:11 ` Masahiro Yamada
2016-02-02 12:11 ` [U-Boot] [PATCH 04/13] ARM: uniphier: support USB boot mode for ProXstream2 / PH1-LD6b SoC Masahiro Yamada
` (10 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Masahiro Yamada @ 2016-02-02 12:11 UTC (permalink / raw)
To: u-boot
This function is for local use in the file.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c
index de12953..3769ec5 100644
--- a/arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c
@@ -46,7 +46,7 @@ static struct boot_device_info boot_device_table[] = {
{BOOT_DEVICE_NONE, "Reserved"},
};
-int get_boot_mode_sel(void)
+static int get_boot_mode_sel(void)
{
return (readl(SG_PINMON0) >> 1) & 0x1f;
}
--
1.9.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH 04/13] ARM: uniphier: support USB boot mode for ProXstream2 / PH1-LD6b SoC
2016-02-02 12:11 [U-Boot] [PATCH 00/13] ARM: uniphier: a collection of clean-ups and new clock driver Masahiro Yamada
` (2 preceding siblings ...)
2016-02-02 12:11 ` [U-Boot] [PATCH 03/13] ARM: uniphier: add missing static qualifier Masahiro Yamada
@ 2016-02-02 12:11 ` Masahiro Yamada
2016-02-02 12:11 ` [U-Boot] [PATCH 05/13] clk: uniphier: add Media I/O clock driver for UniPhier SoCs Masahiro Yamada
` (9 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Masahiro Yamada @ 2016-02-02 12:11 UTC (permalink / raw)
To: u-boot
The USB boot code is too fat and complicated to be included in SPL
(at least for now). So, it was implemented as a separate project
(USB-loader).
The expected boot sequence is as follows:
Boot ROM -> USB-loader -> SPL -> U-Boot proper
The USB-loader loads the SPL and U-Boot proper from a USB memory
onto the locked L2 cache. Then, SPL needs to copy the U-Boot proper
to DRAM, so this mode looks like a NOR boot from the view of SPL.
However, we want to distinguish between (genuine) NOR boot and USB
boot in some places.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
arch/arm/mach-uniphier/board_late_init.c | 8 +++++++-
arch/arm/mach-uniphier/boot-mode/boot-device.h | 2 ++
arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c | 3 +++
arch/arm/mach-uniphier/boot-mode/boot-mode.c | 11 ++++++++++-
4 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-uniphier/board_late_init.c b/arch/arm/mach-uniphier/board_late_init.c
index c2a3261..eba48a2 100644
--- a/arch/arm/mach-uniphier/board_late_init.c
+++ b/arch/arm/mach-uniphier/board_late_init.c
@@ -11,6 +11,8 @@
#include <linux/io.h>
#include <../drivers/mtd/nand/denali.h>
+#include "boot-mode/boot-device.h"
+
static void nand_denali_wp_disable(void)
{
#ifdef CONFIG_NAND_DENALI
@@ -62,7 +64,7 @@ int board_late_init(void)
{
puts("MODE: ");
- switch (spl_boot_device()) {
+ switch (spl_boot_device_raw()) {
case BOOT_DEVICE_MMC1:
printf("eMMC Boot\n");
setenv("bootmode", "emmcboot");
@@ -76,6 +78,10 @@ int board_late_init(void)
printf("NOR Boot\n");
setenv("bootmode", "norboot");
break;
+ case BOOT_DEVICE_USB:
+ printf("USB Boot\n");
+ setenv("bootmode", "usbboot");
+ break;
default:
printf("Unsupported Boot Mode\n");
return -1;
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-device.h b/arch/arm/mach-uniphier/boot-mode/boot-device.h
index 2ab5a53..1c59aaa 100644
--- a/arch/arm/mach-uniphier/boot-mode/boot-device.h
+++ b/arch/arm/mach-uniphier/boot-mode/boot-device.h
@@ -22,4 +22,6 @@ void ph1_ld4_boot_mode_show(void);
void ph1_pro5_boot_mode_show(void);
void proxstream2_boot_mode_show(void);
+u32 spl_boot_device_raw(void);
+
#endif /* _ASM_BOOT_DEVICE_H_ */
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c
index 3769ec5..1b0c183 100644
--- a/arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c
@@ -55,6 +55,9 @@ u32 proxstream2_boot_device(void)
{
int boot_mode;
+ if (readl(SG_PINMON0) & BIT(6))
+ return BOOT_DEVICE_USB;
+
boot_mode = get_boot_mode_sel();
return boot_device_table[boot_mode].type;
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode.c b/arch/arm/mach-uniphier/boot-mode/boot-mode.c
index 0c5749b..935e551 100644
--- a/arch/arm/mach-uniphier/boot-mode/boot-mode.c
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode.c
@@ -11,7 +11,7 @@
#include "../soc-info.h"
#include "boot-device.h"
-u32 spl_boot_device(void)
+u32 spl_boot_device_raw(void)
{
if (boot_is_swapped())
return BOOT_DEVICE_NOR;
@@ -43,3 +43,12 @@ u32 spl_boot_device(void)
return BOOT_DEVICE_NONE;
}
}
+
+u32 spl_boot_device(void)
+{
+ u32 ret;
+
+ ret = spl_boot_device_raw();
+
+ return ret == BOOT_DEVICE_USB ? BOOT_DEVICE_NOR : ret;
+}
--
1.9.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH 05/13] clk: uniphier: add Media I/O clock driver for UniPhier SoCs
2016-02-02 12:11 [U-Boot] [PATCH 00/13] ARM: uniphier: a collection of clean-ups and new clock driver Masahiro Yamada
` (3 preceding siblings ...)
2016-02-02 12:11 ` [U-Boot] [PATCH 04/13] ARM: uniphier: support USB boot mode for ProXstream2 / PH1-LD6b SoC Masahiro Yamada
@ 2016-02-02 12:11 ` Masahiro Yamada
2016-02-02 12:11 ` [U-Boot] [PATCH 06/13] ARM: dts: uniphier: add reference clock nodes Masahiro Yamada
` (8 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Masahiro Yamada @ 2016-02-02 12:11 UTC (permalink / raw)
To: u-boot
This is the initial commit for the UniPhier clock drivers.
Currently, only the Media I/O clock is supported.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
arch/arm/Kconfig | 1 +
drivers/clk/Kconfig | 2 +
drivers/clk/Makefile | 1 +
drivers/clk/uniphier/Kconfig | 13 +++
drivers/clk/uniphier/Makefile | 3 +
drivers/clk/uniphier/clk-uniphier-core.c | 159 +++++++++++++++++++++++++++
drivers/clk/uniphier/clk-uniphier-mio.c | 178 +++++++++++++++++++++++++++++++
drivers/clk/uniphier/clk-uniphier.h | 57 ++++++++++
8 files changed, 414 insertions(+)
create mode 100644 drivers/clk/uniphier/Kconfig
create mode 100644 drivers/clk/uniphier/Makefile
create mode 100644 drivers/clk/uniphier/clk-uniphier-core.c
create mode 100644 drivers/clk/uniphier/clk-uniphier-mio.c
create mode 100644 drivers/clk/uniphier/clk-uniphier.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index d2dbb1a..d8b63e9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -689,6 +689,7 @@ config TARGET_COLIBRI_PXA270
config ARCH_UNIPHIER
bool "Socionext UniPhier SoCs"
+ select CLK_UNIPHIER
select CPU_V7
select SUPPORT_SPL
select SPL
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 9fcde39..a98b74b 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -20,4 +20,6 @@ config SPL_CLK
setting up clocks within SPL, and allows the same drivers to be
used as U-Boot proper.
+source "drivers/clk/uniphier/Kconfig"
+
endmenu
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index c9144e3..c51db15 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
obj-$(CONFIG_SANDBOX) += clk_sandbox.o
obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
+obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
diff --git a/drivers/clk/uniphier/Kconfig b/drivers/clk/uniphier/Kconfig
new file mode 100644
index 0000000..0e90c01
--- /dev/null
+++ b/drivers/clk/uniphier/Kconfig
@@ -0,0 +1,13 @@
+config CLK_UNIPHIER
+ bool
+ select CLK
+ select SPL_CLK
+
+menu "Clock drivers for UniPhier SoCs"
+ depends on CLK_UNIPHIER
+
+config CLK_UNIPHIER_MIO
+ bool "Clock driver for UniPhier Media I/O block"
+ default y
+
+endmenu
diff --git a/drivers/clk/uniphier/Makefile b/drivers/clk/uniphier/Makefile
new file mode 100644
index 0000000..a3168f9
--- /dev/null
+++ b/drivers/clk/uniphier/Makefile
@@ -0,0 +1,3 @@
+obj-y += clk-uniphier-core.o
+
+obj-$(CONFIG_CLK_UNIPHIER_MIO) += clk-uniphier-mio.o
diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c
new file mode 100644
index 0000000..e79e0ff
--- /dev/null
+++ b/drivers/clk/uniphier/clk-uniphier-core.c
@@ -0,0 +1,159 @@
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mapmem.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <clk.h>
+#include <dm/device.h>
+
+#include "clk-uniphier.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int uniphier_clk_enable(struct udevice *dev, int index)
+{
+ struct uniphier_clk_priv *priv = dev_get_priv(dev);
+ struct uniphier_clk_gate_data *gate = priv->socdata->gate;
+ unsigned int nr_gate = priv->socdata->nr_gate;
+ void __iomem *reg;
+ u32 mask, data, tmp;
+ int i;
+
+ for (i = 0; i < nr_gate; i++) {
+ if (gate[i].index != index)
+ continue;
+
+ reg = priv->base + gate[i].reg;
+ mask = gate[i].mask;
+ data = gate[i].data & mask;
+
+ tmp = readl(reg);
+ tmp &= ~mask;
+ tmp |= data & mask;
+ debug("%s: %p: %08x\n", __func__, reg, tmp);
+ writel(tmp, reg);
+ }
+
+ return 0;
+}
+
+static ulong uniphier_clk_get_rate(struct udevice *dev, int index)
+{
+ struct uniphier_clk_priv *priv = dev_get_priv(dev);
+ struct uniphier_clk_rate_data *rdata = priv->socdata->rate;
+ unsigned int nr_rdata = priv->socdata->nr_rate;
+ void __iomem *reg;
+ u32 mask, data;
+ ulong matched_rate = 0;
+ int i;
+
+ for (i = 0; i < nr_rdata; i++) {
+ if (rdata[i].index != index)
+ continue;
+
+ if (rdata[i].reg == UNIPHIER_CLK_RATE_IS_FIXED)
+ return rdata[i].rate;
+
+ reg = priv->base + rdata[i].reg;
+ mask = rdata[i].mask;
+ data = rdata[i].data & mask;
+ if ((readl(reg) & mask) == data) {
+ if (matched_rate && rdata[i].rate != matched_rate) {
+ printf("failed to get clk rate for insane register values\n");
+ return -EINVAL;
+ }
+ matched_rate = rdata[i].rate;
+ }
+ }
+
+ debug("%s: rate = %lu\n", __func__, matched_rate);
+
+ return matched_rate;
+}
+
+static ulong uniphier_clk_set_rate(struct udevice *dev, int index, ulong rate)
+{
+ struct uniphier_clk_priv *priv = dev_get_priv(dev);
+ struct uniphier_clk_rate_data *rdata = priv->socdata->rate;
+ unsigned int nr_rdata = priv->socdata->nr_rate;
+ void __iomem *reg;
+ u32 mask, data, tmp;
+ ulong best_rate = 0;
+ int i;
+
+ /* first, decide the best match rate */
+ for (i = 0; i < nr_rdata; i++) {
+ if (rdata[i].index != index)
+ continue;
+
+ if (rdata[i].reg == UNIPHIER_CLK_RATE_IS_FIXED)
+ return 0;
+
+ if (rdata[i].rate > best_rate && rdata[i].rate <= rate)
+ best_rate = rdata[i].rate;
+ }
+
+ if (!best_rate)
+ return -ENODEV;
+
+ debug("%s: requested rate = %lu, set rate = %lu\n", __func__,
+ rate, best_rate);
+
+ /* second, really set registers */
+ for (i = 0; i < nr_rdata; i++) {
+ if (rdata[i].index != index || rdata[i].rate != best_rate)
+ continue;
+
+ reg = priv->base + rdata[i].reg;
+ mask = rdata[i].mask;
+ data = rdata[i].data & mask;
+
+ tmp = readl(reg);
+ tmp &= ~mask;
+ tmp |= data;
+ debug("%s: %p: %08x\n", __func__, reg, tmp);
+ writel(tmp, reg);
+ }
+
+ return best_rate;
+}
+
+const struct clk_ops uniphier_clk_ops = {
+ .enable = uniphier_clk_enable,
+ .get_periph_rate = uniphier_clk_get_rate,
+ .set_periph_rate = uniphier_clk_set_rate,
+};
+
+int uniphier_clk_probe(struct udevice *dev)
+{
+ struct uniphier_clk_priv *priv = dev_get_priv(dev);
+ fdt_addr_t addr;
+ fdt_size_t size;
+
+ addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg",
+ &size);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->base = map_sysmem(addr, size);
+ if (!priv->base)
+ return -ENOMEM;
+
+ priv->socdata = (void *)dev_get_driver_data(dev);
+
+ return 0;
+}
+
+int uniphier_clk_remove(struct udevice *dev)
+{
+ struct uniphier_clk_priv *priv = dev_get_priv(dev);
+
+ unmap_sysmem(priv->base);
+
+ return 0;
+}
diff --git a/drivers/clk/uniphier/clk-uniphier-mio.c b/drivers/clk/uniphier/clk-uniphier-mio.c
new file mode 100644
index 0000000..d91ae34
--- /dev/null
+++ b/drivers/clk/uniphier/clk-uniphier-mio.c
@@ -0,0 +1,178 @@
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <clk.h>
+#include <dm/device.h>
+
+#include "clk-uniphier.h"
+
+#define UNIPHIER_MIO_CLK_GATE_SD(ch, idx) \
+ { \
+ .index = (idx), \
+ .reg = 0x20 + 0x200 * (ch), \
+ .mask = 0x00000100, \
+ .data = 0x00000100, \
+ }, \
+ { \
+ .index = (idx), \
+ .reg = 0x110 + 0x200 * (ch), \
+ .mask = 0x00000001, \
+ .data = 0x00000001, \
+ }
+
+#define UNIPHIER_MIO_CLK_RATE_SD(ch, idx) \
+ { \
+ .index = (idx), \
+ .reg = 0x30 + 0x200 * (ch), \
+ .mask = 0x00031300, \
+ .data = 0x00000000, \
+ .rate = 44444444, \
+ }, \
+ { \
+ .index = (idx), \
+ .reg = 0x30 + 0x200 * (ch), \
+ .mask = 0x00031300, \
+ .data = 0x00010000, \
+ .rate = 33333333, \
+ }, \
+ { \
+ .index = (idx), \
+ .reg = 0x30 + 0x200 * (ch), \
+ .mask = 0x00031300, \
+ .data = 0x00020000, \
+ .rate = 50000000, \
+ }, \
+ { \
+ .index = (idx), \
+ .reg = 0x30 + 0x200 * (ch), \
+ .mask = 0x00031300, \
+ .data = 0x00020000, \
+ .rate = 66666666, \
+ }, \
+ { \
+ .index = (idx), \
+ .reg = 0x30 + 0x200 * (ch), \
+ .mask = 0x00031300, \
+ .data = 0x00001000, \
+ .rate = 100000000, \
+ }, \
+ { \
+ .index = (idx), \
+ .reg = 0x30 + 0x200 * (ch), \
+ .mask = 0x00031300, \
+ .data = 0x00001100, \
+ .rate = 40000000, \
+ }, \
+ { \
+ .index = (idx), \
+ .reg = 0x30 + 0x200 * (ch), \
+ .mask = 0x00031300, \
+ .data = 0x00001200, \
+ .rate = 25000000, \
+ }, \
+ { \
+ .index = (idx), \
+ .reg = 0x30 + 0x200 * (ch), \
+ .mask = 0x00031300, \
+ .data = 0x00001300, \
+ .rate = 22222222, \
+ }
+
+#define UNIPHIER_MIO_CLK_GATE_USB(ch, idx) \
+ { \
+ .index = (idx), \
+ .reg = 0x20 + 0x200 * (ch), \
+ .mask = 0x30000000, \
+ .data = 0x30000000, \
+ }, \
+ { \
+ .index = (idx), \
+ .reg = 0x110 + 0x200 * (ch), \
+ .mask = 0x01000000, \
+ .data = 0x01000000, \
+ }, \
+ { \
+ .index = (idx), \
+ .reg = 0x114 + 0x200 * (ch), \
+ .mask = 0x00000001, \
+ .data = 0x00000001, \
+ }
+
+#define UNIPHIER_MIO_CLK_GATE_DMAC(idx) \
+ { \
+ .index = (idx), \
+ .reg = 0x20, \
+ .mask = 0x02000000, \
+ .data = 0x02000000, \
+ }, \
+ { \
+ .index = (idx), \
+ .reg = 0x110, \
+ .mask = 0x00020000, \
+ .data = 0x00020000, \
+ }
+
+static struct uniphier_clk_gate_data uniphier_mio_clk_gate[] = {
+ UNIPHIER_MIO_CLK_GATE_SD(0, 0),
+ UNIPHIER_MIO_CLK_GATE_SD(1, 1),
+ UNIPHIER_MIO_CLK_GATE_SD(2, 2), /* for PH1-Pro4 only */
+ UNIPHIER_MIO_CLK_GATE_USB(0, 3),
+ UNIPHIER_MIO_CLK_GATE_USB(1, 4),
+ UNIPHIER_MIO_CLK_GATE_USB(2, 5),
+ UNIPHIER_MIO_CLK_GATE_DMAC(6),
+ UNIPHIER_MIO_CLK_GATE_USB(3, 7), /* for PH1-sLD3 only */
+};
+
+static struct uniphier_clk_rate_data uniphier_mio_clk_rate[] = {
+ UNIPHIER_MIO_CLK_RATE_SD(0, 0),
+ UNIPHIER_MIO_CLK_RATE_SD(1, 1),
+ UNIPHIER_MIO_CLK_RATE_SD(2, 2), /* for PH1-Pro4 only */
+};
+
+static struct uniphier_clk_soc_data uniphier_mio_clk_data = {
+ .gate = uniphier_mio_clk_gate,
+ .nr_gate = ARRAY_SIZE(uniphier_mio_clk_gate),
+ .rate = uniphier_mio_clk_rate,
+ .nr_rate = ARRAY_SIZE(uniphier_mio_clk_rate),
+};
+
+static const struct udevice_id uniphier_mio_clk_match[] = {
+ {
+ .compatible = "socionext,ph1-sld3-mioctrl",
+ .data = (ulong)&uniphier_mio_clk_data,
+ },
+ {
+ .compatible = "socionext,ph1-ld4-mioctrl",
+ .data = (ulong)&uniphier_mio_clk_data,
+ },
+ {
+ .compatible = "socionext,ph1-pro4-mioctrl",
+ .data = (ulong)&uniphier_mio_clk_data,
+ },
+ {
+ .compatible = "socionext,ph1-sld8-mioctrl",
+ .data = (ulong)&uniphier_mio_clk_data,
+ },
+ {
+ .compatible = "socionext,ph1-pro5-mioctrl",
+ .data = (ulong)&uniphier_mio_clk_data,
+ },
+ {
+ .compatible = "socionext,proxstream2-mioctrl",
+ .data = (ulong)&uniphier_mio_clk_data,
+ },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(uniphier_mio_clk) = {
+ .name = "uniphier-mio-clk",
+ .id = UCLASS_CLK,
+ .of_match = uniphier_mio_clk_match,
+ .probe = uniphier_clk_probe,
+ .remove = uniphier_clk_remove,
+ .priv_auto_alloc_size = sizeof(struct uniphier_clk_priv),
+ .ops = &uniphier_clk_ops,
+};
diff --git a/drivers/clk/uniphier/clk-uniphier.h b/drivers/clk/uniphier/clk-uniphier.h
new file mode 100644
index 0000000..560b3f8
--- /dev/null
+++ b/drivers/clk/uniphier/clk-uniphier.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CLK_UNIPHIER_H__
+#define __CLK_UNIPHIER_H__
+
+#include <linux/kernel.h>
+
+struct uniphier_clk_gate_data {
+ int index;
+ unsigned int reg;
+ u32 mask;
+ u32 data;
+};
+
+struct uniphier_clk_rate_data {
+ int index;
+ unsigned int reg;
+#define UNIPHIER_CLK_RATE_IS_FIXED UINT_MAX
+ u32 mask;
+ u32 data;
+ unsigned long rate;
+};
+
+struct uniphier_clk_soc_data {
+ struct uniphier_clk_gate_data *gate;
+ unsigned int nr_gate;
+ struct uniphier_clk_rate_data *rate;
+ unsigned int nr_rate;
+};
+
+#define UNIPHIER_CLK_FIXED_RATE(i, f) \
+ { \
+ .index = i, \
+ .reg = UNIPHIER_CLK_RATE_IS_FIXED, \
+ .rate = f, \
+ }
+
+/**
+ * struct uniphier_clk_priv - private data for UniPhier clock driver
+ *
+ * @base: base address of the clock provider
+ * @socdata: SoC specific data
+ */
+struct uniphier_clk_priv {
+ void __iomem *base;
+ struct uniphier_clk_soc_data *socdata;
+};
+
+extern const struct clk_ops uniphier_clk_ops;
+int uniphier_clk_probe(struct udevice *dev);
+int uniphier_clk_remove(struct udevice *dev);
+
+#endif /* __CLK_UNIPHIER_H__ */
--
1.9.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH 06/13] ARM: dts: uniphier: add reference clock nodes
2016-02-02 12:11 [U-Boot] [PATCH 00/13] ARM: uniphier: a collection of clean-ups and new clock driver Masahiro Yamada
` (4 preceding siblings ...)
2016-02-02 12:11 ` [U-Boot] [PATCH 05/13] clk: uniphier: add Media I/O clock driver for UniPhier SoCs Masahiro Yamada
@ 2016-02-02 12:11 ` Masahiro Yamada
2016-02-02 12:11 ` [U-Boot] [PATCH 07/13] ARM: dts: uniphier: add device nodes for system control blocks Masahiro Yamada
` (7 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Masahiro Yamada @ 2016-02-02 12:11 UTC (permalink / raw)
To: u-boot
Add master clock nodes generated by crystal oscillators.
PH1-sLD3, PH1-LD4: 24.576 MHz
PH1-Pro4, ProXstream2: 25.000 MHz
PH1-Pro5: 20.000 MHz
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
arch/arm/dts/uniphier-common32.dtsi | 7 +++++++
arch/arm/dts/uniphier-ph1-ld4.dtsi | 4 ++++
arch/arm/dts/uniphier-ph1-pro4.dtsi | 4 ++++
arch/arm/dts/uniphier-ph1-pro5.dtsi | 4 ++++
arch/arm/dts/uniphier-ph1-sld3.dtsi | 6 ++++++
arch/arm/dts/uniphier-ph1-sld8.dtsi | 4 ++++
arch/arm/dts/uniphier-proxstream2.dtsi | 4 ++++
7 files changed, 33 insertions(+)
diff --git a/arch/arm/dts/uniphier-common32.dtsi b/arch/arm/dts/uniphier-common32.dtsi
index 5d4b2cf..de04de1 100644
--- a/arch/arm/dts/uniphier-common32.dtsi
+++ b/arch/arm/dts/uniphier-common32.dtsi
@@ -9,6 +9,13 @@
/include/ "skeleton.dtsi"
/ {
+ clocks {
+ refclk: ref {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+ };
+
soc: soc {
compatible = "simple-bus";
#address-cells = <1>;
diff --git a/arch/arm/dts/uniphier-ph1-ld4.dtsi b/arch/arm/dts/uniphier-ph1-ld4.dtsi
index 856c207..6f15978 100644
--- a/arch/arm/dts/uniphier-ph1-ld4.dtsi
+++ b/arch/arm/dts/uniphier-ph1-ld4.dtsi
@@ -136,6 +136,10 @@
};
};
+&refclk {
+ clock-frequency = <24576000>;
+};
+
&serial0 {
clock-frequency = <36864000>;
};
diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi
index 244ccf6..a236dbc 100644
--- a/arch/arm/dts/uniphier-ph1-pro4.dtsi
+++ b/arch/arm/dts/uniphier-ph1-pro4.dtsi
@@ -177,6 +177,10 @@
};
};
+&refclk {
+ clock-frequency = <25000000>;
+};
+
&serial0 {
clock-frequency = <73728000>;
};
diff --git a/arch/arm/dts/uniphier-ph1-pro5.dtsi b/arch/arm/dts/uniphier-ph1-pro5.dtsi
index 0049106..120767c 100644
--- a/arch/arm/dts/uniphier-ph1-pro5.dtsi
+++ b/arch/arm/dts/uniphier-ph1-pro5.dtsi
@@ -171,6 +171,10 @@
};
};
+&refclk {
+ clock-frequency = <20000000>;
+};
+
&serial0 {
clock-frequency = <73728000>;
};
diff --git a/arch/arm/dts/uniphier-ph1-sld3.dtsi b/arch/arm/dts/uniphier-ph1-sld3.dtsi
index f481521..9ff9584 100644
--- a/arch/arm/dts/uniphier-ph1-sld3.dtsi
+++ b/arch/arm/dts/uniphier-ph1-sld3.dtsi
@@ -30,6 +30,12 @@
};
clocks {
+ refclk: ref {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24576000>;
+ };
+
arm_timer_clk: arm_timer_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
diff --git a/arch/arm/dts/uniphier-ph1-sld8.dtsi b/arch/arm/dts/uniphier-ph1-sld8.dtsi
index cb28bc4..e765a4b 100644
--- a/arch/arm/dts/uniphier-ph1-sld8.dtsi
+++ b/arch/arm/dts/uniphier-ph1-sld8.dtsi
@@ -136,6 +136,10 @@
};
};
+&refclk {
+ clock-frequency = <25000000>;
+};
+
&serial0 {
clock-frequency = <80000000>;
};
diff --git a/arch/arm/dts/uniphier-proxstream2.dtsi b/arch/arm/dts/uniphier-proxstream2.dtsi
index 3ba6a4a..c7423ff 100644
--- a/arch/arm/dts/uniphier-proxstream2.dtsi
+++ b/arch/arm/dts/uniphier-proxstream2.dtsi
@@ -182,6 +182,10 @@
};
};
+&refclk {
+ clock-frequency = <25000000>;
+};
+
&serial0 {
clock-frequency = <88900000>;
};
--
1.9.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH 07/13] ARM: dts: uniphier: add device nodes for system control blocks
2016-02-02 12:11 [U-Boot] [PATCH 00/13] ARM: uniphier: a collection of clean-ups and new clock driver Masahiro Yamada
` (5 preceding siblings ...)
2016-02-02 12:11 ` [U-Boot] [PATCH 06/13] ARM: dts: uniphier: add reference clock nodes Masahiro Yamada
@ 2016-02-02 12:11 ` Masahiro Yamada
2016-02-02 12:11 ` [U-Boot] [PATCH 08/13] ARM: dts: uniphier: add device nodes for Peripheral control block Masahiro Yamada
` (6 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Masahiro Yamada @ 2016-02-02 12:11 UTC (permalink / raw)
To: u-boot
This is a system control block mainly used for clock and reset control.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
arch/arm/dts/uniphier-common32.dtsi | 8 ++++++++
arch/arm/dts/uniphier-ph1-ld4.dtsi | 4 ++++
arch/arm/dts/uniphier-ph1-pro4.dtsi | 4 ++++
arch/arm/dts/uniphier-ph1-pro5.dtsi | 4 ++++
arch/arm/dts/uniphier-ph1-sld3.dtsi | 8 ++++++++
arch/arm/dts/uniphier-ph1-sld8.dtsi | 4 ++++
arch/arm/dts/uniphier-proxstream2.dtsi | 4 ++++
7 files changed, 36 insertions(+)
diff --git a/arch/arm/dts/uniphier-common32.dtsi b/arch/arm/dts/uniphier-common32.dtsi
index de04de1..d3e5a74 100644
--- a/arch/arm/dts/uniphier-common32.dtsi
+++ b/arch/arm/dts/uniphier-common32.dtsi
@@ -101,6 +101,14 @@
reg = <0x5f801000 0xe00>;
};
+ sysctrl: sysctrl at 61840000 {
+ /* specify compatible in each SoC DTSI */
+ reg = <0x61840000 0x4000>;
+ #clock-cells = <1>;
+ clock-names = "ref";
+ clocks = <&refclk>;
+ };
+
nand: nand at 68000000 {
compatible = "denali,denali-nand-dt";
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
diff --git a/arch/arm/dts/uniphier-ph1-ld4.dtsi b/arch/arm/dts/uniphier-ph1-ld4.dtsi
index 6f15978..6bd4b91 100644
--- a/arch/arm/dts/uniphier-ph1-ld4.dtsi
+++ b/arch/arm/dts/uniphier-ph1-ld4.dtsi
@@ -160,3 +160,7 @@
&pinctrl {
compatible = "socionext,ph1-ld4-pinctrl", "syscon";
};
+
+&sysctrl {
+ compatible = "socionext,ph1-ld4-sysctrl";
+};
diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi
index a236dbc..984f99c 100644
--- a/arch/arm/dts/uniphier-ph1-pro4.dtsi
+++ b/arch/arm/dts/uniphier-ph1-pro4.dtsi
@@ -200,3 +200,7 @@
&pinctrl {
compatible = "socionext,ph1-pro4-pinctrl", "syscon";
};
+
+&sysctrl {
+ compatible = "socionext,ph1-pro4-sysctrl";
+};
diff --git a/arch/arm/dts/uniphier-ph1-pro5.dtsi b/arch/arm/dts/uniphier-ph1-pro5.dtsi
index 120767c..a836176 100644
--- a/arch/arm/dts/uniphier-ph1-pro5.dtsi
+++ b/arch/arm/dts/uniphier-ph1-pro5.dtsi
@@ -194,3 +194,7 @@
&pinctrl {
compatible = "socionext,ph1-pro5-pinctrl", "syscon";
};
+
+&sysctrl {
+ compatible = "socionext,ph1-pro5-sysctrl";
+};
diff --git a/arch/arm/dts/uniphier-ph1-sld3.dtsi b/arch/arm/dts/uniphier-ph1-sld3.dtsi
index 9ff9584..c7a8902 100644
--- a/arch/arm/dts/uniphier-ph1-sld3.dtsi
+++ b/arch/arm/dts/uniphier-ph1-sld3.dtsi
@@ -206,6 +206,14 @@
interrupts = <0 83 4>;
};
+ sysctrl: sysctrl at f1840000 {
+ compatible = "socionext,ph1-sld3-sysctrl";
+ reg = <0xf1840000 0x4000>;
+ #clock-cells = <1>;
+ clock-names = "ref";
+ clocks = <&refclk>;
+ };
+
nand: nand at f8000000 {
compatible = "denali,denali-nand-dt";
reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
diff --git a/arch/arm/dts/uniphier-ph1-sld8.dtsi b/arch/arm/dts/uniphier-ph1-sld8.dtsi
index e765a4b..9d97fb0 100644
--- a/arch/arm/dts/uniphier-ph1-sld8.dtsi
+++ b/arch/arm/dts/uniphier-ph1-sld8.dtsi
@@ -160,3 +160,7 @@
&pinctrl {
compatible = "socionext,ph1-sld8-pinctrl", "syscon";
};
+
+&sysctrl {
+ compatible = "socionext,ph1-sld8-sysctrl";
+};
diff --git a/arch/arm/dts/uniphier-proxstream2.dtsi b/arch/arm/dts/uniphier-proxstream2.dtsi
index c7423ff..f6f4bbe 100644
--- a/arch/arm/dts/uniphier-proxstream2.dtsi
+++ b/arch/arm/dts/uniphier-proxstream2.dtsi
@@ -205,3 +205,7 @@
&pinctrl {
compatible = "socionext,proxstream2-pinctrl", "syscon";
};
+
+&sysctrl {
+ compatible = "socionext,proxstream2-sysctrl";
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH 08/13] ARM: dts: uniphier: add device nodes for Peripheral control block
2016-02-02 12:11 [U-Boot] [PATCH 00/13] ARM: uniphier: a collection of clean-ups and new clock driver Masahiro Yamada
` (6 preceding siblings ...)
2016-02-02 12:11 ` [U-Boot] [PATCH 07/13] ARM: dts: uniphier: add device nodes for system control blocks Masahiro Yamada
@ 2016-02-02 12:11 ` Masahiro Yamada
2016-02-02 12:11 ` [U-Boot] [PATCH 09/13] ARM: dts: uniphier: add device nodes for MIO " Masahiro Yamada
` (5 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Masahiro Yamada @ 2016-02-02 12:11 UTC (permalink / raw)
To: u-boot
This block provides clock and reset control for peripherals such as
UART, I2C, IC card, etc.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
arch/arm/dts/uniphier-common32.dtsi | 6 ++++++
arch/arm/dts/uniphier-ph1-ld4.dtsi | 6 ++++++
arch/arm/dts/uniphier-ph1-pro4.dtsi | 6 ++++++
arch/arm/dts/uniphier-ph1-pro5.dtsi | 6 ++++++
arch/arm/dts/uniphier-ph1-sld8.dtsi | 6 ++++++
arch/arm/dts/uniphier-proxstream2.dtsi | 6 ++++++
6 files changed, 36 insertions(+)
diff --git a/arch/arm/dts/uniphier-common32.dtsi b/arch/arm/dts/uniphier-common32.dtsi
index d3e5a74..43e5bea 100644
--- a/arch/arm/dts/uniphier-common32.dtsi
+++ b/arch/arm/dts/uniphier-common32.dtsi
@@ -74,6 +74,12 @@
reg = <0x58c00000 0x400>, <0x59800000 0x2000>;
};
+ peri: perictrl at 59820000 {
+ /* specify compatible in each SoC DTSI */
+ reg = <0x59820000 0x200>;
+ #clock-cells = <1>;
+ };
+
timer at 60000200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x60000200 0x20>;
diff --git a/arch/arm/dts/uniphier-ph1-ld4.dtsi b/arch/arm/dts/uniphier-ph1-ld4.dtsi
index 6bd4b91..5843097 100644
--- a/arch/arm/dts/uniphier-ph1-ld4.dtsi
+++ b/arch/arm/dts/uniphier-ph1-ld4.dtsi
@@ -157,6 +157,12 @@
clock-frequency = <36864000>;
};
+&peri {
+ compatible = "socionext,ph1-ld4-perictrl";
+ clock-names = "uart", "i2c";
+ clocks = <&sysctrl 3>, <&sysctrl 4>;
+};
+
&pinctrl {
compatible = "socionext,ph1-ld4-pinctrl", "syscon";
};
diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi
index 984f99c..0c2f02f 100644
--- a/arch/arm/dts/uniphier-ph1-pro4.dtsi
+++ b/arch/arm/dts/uniphier-ph1-pro4.dtsi
@@ -197,6 +197,12 @@
clock-frequency = <73728000>;
};
+&peri {
+ compatible = "socionext,ph1-pro4-perictrl";
+ clock-names = "uart", "fi2c";
+ clocks = <&sysctrl 3>, <&sysctrl 4>;
+};
+
&pinctrl {
compatible = "socionext,ph1-pro4-pinctrl", "syscon";
};
diff --git a/arch/arm/dts/uniphier-ph1-pro5.dtsi b/arch/arm/dts/uniphier-ph1-pro5.dtsi
index a836176..305114c 100644
--- a/arch/arm/dts/uniphier-ph1-pro5.dtsi
+++ b/arch/arm/dts/uniphier-ph1-pro5.dtsi
@@ -191,6 +191,12 @@
clock-frequency = <73728000>;
};
+&peri {
+ compatible = "socionext,ph1-pro5-perictrl";
+ clock-names = "uart", "fi2c";
+ clocks = <&sysctrl 3>, <&sysctrl 4>;
+};
+
&pinctrl {
compatible = "socionext,ph1-pro5-pinctrl", "syscon";
};
diff --git a/arch/arm/dts/uniphier-ph1-sld8.dtsi b/arch/arm/dts/uniphier-ph1-sld8.dtsi
index 9d97fb0..7a26b4a 100644
--- a/arch/arm/dts/uniphier-ph1-sld8.dtsi
+++ b/arch/arm/dts/uniphier-ph1-sld8.dtsi
@@ -157,6 +157,12 @@
clock-frequency = <80000000>;
};
+&peri {
+ compatible = "socionext,ph1-sld8-perictrl";
+ clock-names = "uart", "i2c";
+ clocks = <&sysctrl 3>, <&sysctrl 4>;
+};
+
&pinctrl {
compatible = "socionext,ph1-sld8-pinctrl", "syscon";
};
diff --git a/arch/arm/dts/uniphier-proxstream2.dtsi b/arch/arm/dts/uniphier-proxstream2.dtsi
index f6f4bbe..f2faf25 100644
--- a/arch/arm/dts/uniphier-proxstream2.dtsi
+++ b/arch/arm/dts/uniphier-proxstream2.dtsi
@@ -202,6 +202,12 @@
clock-frequency = <88900000>;
};
+&peri {
+ compatible = "socionext,proxstream2-perictrl";
+ clock-names = "uart", "fi2c";
+ clocks = <&sysctrl 3>, <&sysctrl 4>;
+};
+
&pinctrl {
compatible = "socionext,proxstream2-pinctrl", "syscon";
};
--
1.9.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH 09/13] ARM: dts: uniphier: add device nodes for MIO control block
2016-02-02 12:11 [U-Boot] [PATCH 00/13] ARM: uniphier: a collection of clean-ups and new clock driver Masahiro Yamada
` (7 preceding siblings ...)
2016-02-02 12:11 ` [U-Boot] [PATCH 08/13] ARM: dts: uniphier: add device nodes for Peripheral control block Masahiro Yamada
@ 2016-02-02 12:11 ` Masahiro Yamada
2016-02-02 12:11 ` [U-Boot] [PATCH 10/13] ARM: dts: uniphier: switch to use clock drivers Masahiro Yamada
` (4 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Masahiro Yamada @ 2016-02-02 12:11 UTC (permalink / raw)
To: u-boot
This block provides clock and reset control for MIO (Media I/O)
hardware blocks such as USB2.0, SD card, eMMC, etc.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
arch/arm/dts/uniphier-common32.dtsi | 6 ++++++
arch/arm/dts/uniphier-ph1-ld4.dtsi | 6 ++++++
arch/arm/dts/uniphier-ph1-pro4.dtsi | 6 ++++++
arch/arm/dts/uniphier-ph1-pro5.dtsi | 6 ++++++
arch/arm/dts/uniphier-ph1-sld3.dtsi | 8 ++++++++
arch/arm/dts/uniphier-ph1-sld8.dtsi | 6 ++++++
arch/arm/dts/uniphier-proxstream2.dtsi | 6 ++++++
7 files changed, 44 insertions(+)
diff --git a/arch/arm/dts/uniphier-common32.dtsi b/arch/arm/dts/uniphier-common32.dtsi
index 43e5bea..59511bd 100644
--- a/arch/arm/dts/uniphier-common32.dtsi
+++ b/arch/arm/dts/uniphier-common32.dtsi
@@ -74,6 +74,12 @@
reg = <0x58c00000 0x400>, <0x59800000 0x2000>;
};
+ mio: mioctrl at 59810000 {
+ /* specify compatible in each SoC DTSI */
+ reg = <0x59810000 0x800>;
+ #clock-cells = <1>;
+ };
+
peri: perictrl at 59820000 {
/* specify compatible in each SoC DTSI */
reg = <0x59820000 0x200>;
diff --git a/arch/arm/dts/uniphier-ph1-ld4.dtsi b/arch/arm/dts/uniphier-ph1-ld4.dtsi
index 5843097..628a397 100644
--- a/arch/arm/dts/uniphier-ph1-ld4.dtsi
+++ b/arch/arm/dts/uniphier-ph1-ld4.dtsi
@@ -157,6 +157,12 @@
clock-frequency = <36864000>;
};
+&mio {
+ compatible = "socionext,ph1-ld4-mioctrl";
+ clock-names = "stdmac", "ehci";
+ clocks = <&sysctrl 10>, <&sysctrl 18>;
+};
+
&peri {
compatible = "socionext,ph1-ld4-perictrl";
clock-names = "uart", "i2c";
diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi
index 0c2f02f..bfffe94 100644
--- a/arch/arm/dts/uniphier-ph1-pro4.dtsi
+++ b/arch/arm/dts/uniphier-ph1-pro4.dtsi
@@ -197,6 +197,12 @@
clock-frequency = <73728000>;
};
+&mio {
+ compatible = "socionext,ph1-pro4-mioctrl";
+ clock-names = "stdmac", "ehci";
+ clocks = <&sysctrl 10>, <&sysctrl 18>;
+};
+
&peri {
compatible = "socionext,ph1-pro4-perictrl";
clock-names = "uart", "fi2c";
diff --git a/arch/arm/dts/uniphier-ph1-pro5.dtsi b/arch/arm/dts/uniphier-ph1-pro5.dtsi
index 305114c..087b25a 100644
--- a/arch/arm/dts/uniphier-ph1-pro5.dtsi
+++ b/arch/arm/dts/uniphier-ph1-pro5.dtsi
@@ -191,6 +191,12 @@
clock-frequency = <73728000>;
};
+&mio {
+ compatible = "socionext,ph1-pro5-mioctrl";
+ clock-names = "stdmac";
+ clocks = <&sysctrl 10>;
+};
+
&peri {
compatible = "socionext,ph1-pro5-perictrl";
clock-names = "uart", "fi2c";
diff --git a/arch/arm/dts/uniphier-ph1-sld3.dtsi b/arch/arm/dts/uniphier-ph1-sld3.dtsi
index c7a8902..91c9ba5 100644
--- a/arch/arm/dts/uniphier-ph1-sld3.dtsi
+++ b/arch/arm/dts/uniphier-ph1-sld3.dtsi
@@ -178,6 +178,14 @@
reg = <0x59800000 0x2000>;
};
+ mio: mioctrl at 59810000 {
+ compatible = "socionext,ph1-sld3-mioctrl";
+ reg = <0x59810000 0x800>;
+ #clock-cells = <1>;
+ clock-names = "stdmac", "ehci";
+ clocks = <&sysctrl 10>, <&sysctrl 18>;
+ };
+
usb0: usb at 5a800100 {
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
diff --git a/arch/arm/dts/uniphier-ph1-sld8.dtsi b/arch/arm/dts/uniphier-ph1-sld8.dtsi
index 7a26b4a..b9ef401 100644
--- a/arch/arm/dts/uniphier-ph1-sld8.dtsi
+++ b/arch/arm/dts/uniphier-ph1-sld8.dtsi
@@ -157,6 +157,12 @@
clock-frequency = <80000000>;
};
+&mio {
+ compatible = "socionext,ph1-sld8-mioctrl";
+ clock-names = "stdmac", "ehci";
+ clocks = <&sysctrl 10>, <&sysctrl 18>;
+};
+
&peri {
compatible = "socionext,ph1-sld8-perictrl";
clock-names = "uart", "i2c";
diff --git a/arch/arm/dts/uniphier-proxstream2.dtsi b/arch/arm/dts/uniphier-proxstream2.dtsi
index f2faf25..a70b135 100644
--- a/arch/arm/dts/uniphier-proxstream2.dtsi
+++ b/arch/arm/dts/uniphier-proxstream2.dtsi
@@ -202,6 +202,12 @@
clock-frequency = <88900000>;
};
+&mio {
+ compatible = "socionext,ph1-pro5-mioctrl";
+ clock-names = "stdmac";
+ clocks = <&sysctrl 10>;
+};
+
&peri {
compatible = "socionext,proxstream2-perictrl";
clock-names = "uart", "fi2c";
--
1.9.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH 10/13] ARM: dts: uniphier: switch to use clock drivers
2016-02-02 12:11 [U-Boot] [PATCH 00/13] ARM: uniphier: a collection of clean-ups and new clock driver Masahiro Yamada
` (8 preceding siblings ...)
2016-02-02 12:11 ` [U-Boot] [PATCH 09/13] ARM: dts: uniphier: add device nodes for MIO " Masahiro Yamada
@ 2016-02-02 12:11 ` Masahiro Yamada
2016-02-02 12:11 ` [U-Boot] [PATCH 11/13] usb: remove UniPhier EHCI driver Masahiro Yamada
` (3 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Masahiro Yamada @ 2016-02-02 12:11 UTC (permalink / raw)
To: u-boot
Specify clocks properties to the EHCI nodes.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
arch/arm/dts/uniphier-ph1-ld4.dtsi | 3 +++
arch/arm/dts/uniphier-ph1-pro4.dtsi | 2 ++
arch/arm/dts/uniphier-ph1-sld3.dtsi | 4 ++++
arch/arm/dts/uniphier-ph1-sld8.dtsi | 3 +++
4 files changed, 12 insertions(+)
diff --git a/arch/arm/dts/uniphier-ph1-ld4.dtsi b/arch/arm/dts/uniphier-ph1-ld4.dtsi
index 628a397..7c8759f 100644
--- a/arch/arm/dts/uniphier-ph1-ld4.dtsi
+++ b/arch/arm/dts/uniphier-ph1-ld4.dtsi
@@ -115,6 +115,7 @@
interrupts = <0 80 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
+ clocks = <&mio 3>, <&mio 6>;
};
usb1: usb at 5a810100 {
@@ -124,6 +125,7 @@
interrupts = <0 81 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
+ clocks = <&mio 4>, <&mio 6>;
};
usb2: usb at 5a820100 {
@@ -133,6 +135,7 @@
interrupts = <0 82 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2>;
+ clocks = <&mio 5>, <&mio 6>;
};
};
diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi
index bfffe94..cb5b8f1 100644
--- a/arch/arm/dts/uniphier-ph1-pro4.dtsi
+++ b/arch/arm/dts/uniphier-ph1-pro4.dtsi
@@ -147,6 +147,7 @@
interrupts = <0 80 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2>;
+ clocks = <&mio 3>, <&mio 6>;
};
usb3: usb at 5a810100 {
@@ -156,6 +157,7 @@
interrupts = <0 81 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb3>;
+ clocks = <&mio 4>, <&mio 6>;
};
usb0: usb at 65a00000 {
diff --git a/arch/arm/dts/uniphier-ph1-sld3.dtsi b/arch/arm/dts/uniphier-ph1-sld3.dtsi
index 91c9ba5..85dde66 100644
--- a/arch/arm/dts/uniphier-ph1-sld3.dtsi
+++ b/arch/arm/dts/uniphier-ph1-sld3.dtsi
@@ -191,6 +191,7 @@
status = "disabled";
reg = <0x5a800100 0x100>;
interrupts = <0 80 4>;
+ clocks = <&mio 3>, <&mio 6>;
};
usb1: usb at 5a810100 {
@@ -198,6 +199,7 @@
status = "disabled";
reg = <0x5a810100 0x100>;
interrupts = <0 81 4>;
+ clocks = <&mio 4>, <&mio 6>;
};
usb2: usb at 5a820100 {
@@ -205,6 +207,7 @@
status = "disabled";
reg = <0x5a820100 0x100>;
interrupts = <0 82 4>;
+ clocks = <&mio 5>, <&mio 6>;
};
usb3: usb at 5a830100 {
@@ -212,6 +215,7 @@
status = "disabled";
reg = <0x5a830100 0x100>;
interrupts = <0 83 4>;
+ clocks = <&mio 7>, <&mio 6>;
};
sysctrl: sysctrl at f1840000 {
diff --git a/arch/arm/dts/uniphier-ph1-sld8.dtsi b/arch/arm/dts/uniphier-ph1-sld8.dtsi
index b9ef401..f93db83 100644
--- a/arch/arm/dts/uniphier-ph1-sld8.dtsi
+++ b/arch/arm/dts/uniphier-ph1-sld8.dtsi
@@ -115,6 +115,7 @@
interrupts = <0 80 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
+ clocks = <&mio 3>, <&mio 6>;
};
usb1: usb at 5a810100 {
@@ -124,6 +125,7 @@
interrupts = <0 81 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
+ clocks = <&mio 4>, <&mio 6>;
};
usb2: usb at 5a820100 {
@@ -133,6 +135,7 @@
interrupts = <0 82 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2>;
+ clocks = <&mio 5>, <&mio 6>;
};
};
--
1.9.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH 11/13] usb: remove UniPhier EHCI driver
2016-02-02 12:11 [U-Boot] [PATCH 00/13] ARM: uniphier: a collection of clean-ups and new clock driver Masahiro Yamada
` (9 preceding siblings ...)
2016-02-02 12:11 ` [U-Boot] [PATCH 10/13] ARM: dts: uniphier: switch to use clock drivers Masahiro Yamada
@ 2016-02-02 12:11 ` Masahiro Yamada
2016-02-02 12:12 ` Marek Vasut
2016-02-02 12:11 ` [U-Boot] [PATCH 12/13] ARM: uniphier: enable generic " Masahiro Yamada
` (2 subsequent siblings)
13 siblings, 1 reply; 16+ messages in thread
From: Masahiro Yamada @ 2016-02-02 12:11 UTC (permalink / raw)
To: u-boot
Currently, what this driver does is just to set the base address and
reset/clock handling. The latter is cared by the clock driver now.
There is nothing special for this EHCI controller.
I want to use the generic-ehci driver rather than bothering to convert
this driver to Driver Model.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
drivers/usb/host/Kconfig | 7 ----
drivers/usb/host/Makefile | 1 -
drivers/usb/host/ehci-uniphier.c | 75 ----------------------------------------
3 files changed, 83 deletions(-)
delete mode 100644 drivers/usb/host/ehci-uniphier.c
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 39f7185..9332374 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -74,13 +74,6 @@ config USB_EHCI_MX6
---help---
Enables support for the on-chip EHCI controller on i.MX6 SoCs.
-config USB_EHCI_UNIPHIER
- bool "Support for UniPhier on-chip EHCI USB controller"
- depends on ARCH_UNIPHIER && OF_CONTROL
- default y
- ---help---
- Enables support for the on-chip EHCI controller on UniPhier SoCs.
-
config USB_EHCI_GENERIC
bool "Support for generic EHCI USB controller"
depends on OF_CONTROL
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 6183b80..9a87d2b 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -47,7 +47,6 @@ obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o
obj-$(CONFIG_USB_EHCI_SUNXI) += ehci-sunxi.o
obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
-obj-$(CONFIG_USB_EHCI_UNIPHIER) += ehci-uniphier.o
obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
obj-$(CONFIG_USB_EHCI_VF) += ehci-vf.o
obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o
diff --git a/drivers/usb/host/ehci-uniphier.c b/drivers/usb/host/ehci-uniphier.c
deleted file mode 100644
index c3f827c..0000000
--- a/drivers/usb/host/ehci-uniphier.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <usb.h>
-#include <mach/mio-regs.h>
-#include <fdtdec.h>
-#include "ehci.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define FDT gd->fdt_blob
-#define COMPAT "socionext,uniphier-ehci"
-
-static int get_uniphier_ehci_base(int index, struct ehci_hccr **base)
-{
- int offset;
-
- for (offset = fdt_node_offset_by_compatible(FDT, 0, COMPAT);
- offset >= 0;
- offset = fdt_node_offset_by_compatible(FDT, offset, COMPAT)) {
- if (index == 0) {
- *base = (struct ehci_hccr *)
- fdtdec_get_addr(FDT, offset, "reg");
- return 0;
- }
- index--;
- }
-
- return -ENODEV; /* not found */
-}
-
-static void uniphier_ehci_reset(int index, int on)
-{
- u32 tmp;
-
- tmp = readl(MIO_USB_RSTCTRL(index));
- if (on)
- tmp &= ~MIO_USB_RSTCTRL_XRST;
- else
- tmp |= MIO_USB_RSTCTRL_XRST;
- writel(tmp, MIO_USB_RSTCTRL(index));
-}
-
-int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr,
- struct ehci_hcor **hcor)
-{
- int ret;
- struct ehci_hccr *cr;
- struct ehci_hcor *or;
-
- uniphier_ehci_reset(index, 0);
-
- ret = get_uniphier_ehci_base(index, &cr);
- if (ret < 0)
- return ret;
- or = (void *)cr + HC_LENGTH(ehci_readl(&cr->cr_capbase));
-
- *hccr = cr;
- *hcor = or;
-
- return 0;
-}
-
-int ehci_hcd_stop(int index)
-{
- uniphier_ehci_reset(index, 1);
-
- return 0;
-}
--
1.9.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH 12/13] ARM: uniphier: enable generic EHCI driver
2016-02-02 12:11 [U-Boot] [PATCH 00/13] ARM: uniphier: a collection of clean-ups and new clock driver Masahiro Yamada
` (10 preceding siblings ...)
2016-02-02 12:11 ` [U-Boot] [PATCH 11/13] usb: remove UniPhier EHCI driver Masahiro Yamada
@ 2016-02-02 12:11 ` Masahiro Yamada
2016-02-02 12:11 ` [U-Boot] [PATCH 13/13] ARM: uniphier: drop unneeded EHCI pin mux settings Masahiro Yamada
2016-02-14 8:29 ` [U-Boot] [PATCH 00/13] ARM: uniphier: a collection of clean-ups and new clock driver Masahiro Yamada
13 siblings, 0 replies; 16+ messages in thread
From: Masahiro Yamada @ 2016-02-02 12:11 UTC (permalink / raw)
To: u-boot
This generic driver will do for the time being.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
arch/arm/mach-uniphier/clk/clk-ph1-ld4.c | 4 ++--
arch/arm/mach-uniphier/clk/clk-ph1-pro4.c | 4 ++--
arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c | 2 +-
arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c | 2 +-
arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c | 2 +-
arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c | 2 +-
configs/uniphier_ld4_sld8_defconfig | 2 ++
configs/uniphier_sld3_defconfig | 2 ++
8 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-uniphier/clk/clk-ph1-ld4.c b/arch/arm/mach-uniphier/clk/clk-ph1-ld4.c
index 4de9bfb..7a34bee 100644
--- a/arch/arm/mach-uniphier/clk/clk-ph1-ld4.c
+++ b/arch/arm/mach-uniphier/clk/clk-ph1-ld4.c
@@ -18,7 +18,7 @@ void ph1_ld4_clk_init(void)
#ifdef CONFIG_UNIPHIER_ETH
tmp |= SC_RSTCTRL_NRST_ETHER;
#endif
-#ifdef CONFIG_USB_EHCI_UNIPHIER
+#ifdef CONFIG_USB_EHCI
tmp |= SC_RSTCTRL_NRST_STDMAC;
#endif
#ifdef CONFIG_NAND_DENALI
@@ -32,7 +32,7 @@ void ph1_ld4_clk_init(void)
#ifdef CONFIG_UNIPHIER_ETH
tmp |= SC_CLKCTRL_CEN_ETHER;
#endif
-#ifdef CONFIG_USB_EHCI_UNIPHIER
+#ifdef CONFIG_USB_EHCI
tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC;
#endif
#ifdef CONFIG_NAND_DENALI
diff --git a/arch/arm/mach-uniphier/clk/clk-ph1-pro4.c b/arch/arm/mach-uniphier/clk/clk-ph1-pro4.c
index 3df017e..c784c31 100644
--- a/arch/arm/mach-uniphier/clk/clk-ph1-pro4.c
+++ b/arch/arm/mach-uniphier/clk/clk-ph1-pro4.c
@@ -22,7 +22,7 @@ void ph1_pro4_clk_init(void)
#ifdef CONFIG_UNIPHIER_ETH
tmp |= SC_RSTCTRL_NRST_ETHER;
#endif
-#ifdef CONFIG_USB_EHCI_UNIPHIER
+#ifdef CONFIG_USB_EHCI
tmp |= SC_RSTCTRL_NRST_STDMAC;
#endif
#ifdef CONFIG_NAND_DENALI
@@ -47,7 +47,7 @@ void ph1_pro4_clk_init(void)
#ifdef CONFIG_UNIPHIER_ETH
tmp |= SC_CLKCTRL_CEN_ETHER;
#endif
-#ifdef CONFIG_USB_EHCI_UNIPHIER
+#ifdef CONFIG_USB_EHCI
tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC;
#endif
#ifdef CONFIG_NAND_DENALI
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c
index 8168a63..3c06b30 100644
--- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c
+++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c
@@ -35,7 +35,7 @@ void ph1_ld4_pin_init(void)
sg_set_pinsel(31, 0, 8, 4); /* MMCDAT7 -> NFD7_GB */
#endif
-#ifdef CONFIG_USB_EHCI_UNIPHIER
+#ifdef CONFIG_USB_EHCI
sg_set_pinsel(53, 0, 8, 4); /* USB0VBUS -> USB0VBUS */
sg_set_pinsel(54, 0, 8, 4); /* USB0OD -> USB0OD */
sg_set_pinsel(55, 0, 8, 4); /* USB1VBUS -> USB1VBUS */
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c
index 23b5f93..d5541a9 100644
--- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c
+++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c
@@ -40,7 +40,7 @@ void ph1_pro4_pin_init(void)
sg_set_pinsel(183, 0, 4, 8); /* USB1OD -> USB1OD */
#endif
-#ifdef CONFIG_USB_EHCI_UNIPHIER
+#ifdef CONFIG_USB_EHCI
sg_set_pinsel(184, 0, 4, 8); /* USB2VBUS -> USB2VBUS */
sg_set_pinsel(185, 0, 4, 8); /* USB2OD -> USB2OD */
sg_set_pinsel(187, 0, 4, 8); /* USB3VBUS -> USB3VBUS */
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c
index 6fc0dee..367d9f3 100644
--- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c
+++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c
@@ -9,7 +9,7 @@
void ph1_sld3_pin_init(void)
{
-#ifdef CONFIG_USB_EHCI_UNIPHIER
+#ifdef CONFIG_USB_EHCI
sg_set_pinsel(13, 0, 4, 4); /* USB0OC */
sg_set_pinsel(14, 1, 4, 4); /* USB0VBUS */
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c
index a4e3e7a..6763584 100644
--- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c
+++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c
@@ -33,7 +33,7 @@ void ph1_sld8_pin_init(void)
sg_set_pinsel(31, 0, 8, 4); /* NFD7_GB -> NFD7_GB */
#endif
-#ifdef CONFIG_USB_EHCI_UNIPHIER
+#ifdef CONFIG_USB_EHCI
sg_set_pinsel(41, 0, 8, 4); /* USB0VBUS -> USB0VBUS */
sg_set_pinsel(42, 0, 8, 4); /* USB0OD -> USB0OD */
sg_set_pinsel(43, 0, 8, 4); /* USB1VBUS -> USB1VBUS */
diff --git a/configs/uniphier_ld4_sld8_defconfig b/configs/uniphier_ld4_sld8_defconfig
index ee3cbad..535f96f 100644
--- a/configs/uniphier_ld4_sld8_defconfig
+++ b/configs/uniphier_ld4_sld8_defconfig
@@ -27,5 +27,7 @@ CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_UNIPHIER_SERIAL=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_STORAGE=y
diff --git a/configs/uniphier_sld3_defconfig b/configs/uniphier_sld3_defconfig
index 4b871d0..e369c45 100644
--- a/configs/uniphier_sld3_defconfig
+++ b/configs/uniphier_sld3_defconfig
@@ -22,5 +22,7 @@ CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
CONFIG_SPL_NAND_DENALI=y
CONFIG_UNIPHIER_SERIAL=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_STORAGE=y
--
1.9.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH 13/13] ARM: uniphier: drop unneeded EHCI pin mux settings
2016-02-02 12:11 [U-Boot] [PATCH 00/13] ARM: uniphier: a collection of clean-ups and new clock driver Masahiro Yamada
` (11 preceding siblings ...)
2016-02-02 12:11 ` [U-Boot] [PATCH 12/13] ARM: uniphier: enable generic " Masahiro Yamada
@ 2016-02-02 12:11 ` Masahiro Yamada
2016-02-14 8:29 ` [U-Boot] [PATCH 00/13] ARM: uniphier: a collection of clean-ups and new clock driver Masahiro Yamada
13 siblings, 0 replies; 16+ messages in thread
From: Masahiro Yamada @ 2016-02-02 12:11 UTC (permalink / raw)
To: u-boot
These pin mux settings are cared by the pinctrl driver.
Remove the ad-hoc code.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c | 9 ---------
arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c | 7 -------
arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c | 9 ---------
3 files changed, 25 deletions(-)
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c
index 3c06b30..2fe2c7f 100644
--- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c
+++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c
@@ -35,15 +35,6 @@ void ph1_ld4_pin_init(void)
sg_set_pinsel(31, 0, 8, 4); /* MMCDAT7 -> NFD7_GB */
#endif
-#ifdef CONFIG_USB_EHCI
- sg_set_pinsel(53, 0, 8, 4); /* USB0VBUS -> USB0VBUS */
- sg_set_pinsel(54, 0, 8, 4); /* USB0OD -> USB0OD */
- sg_set_pinsel(55, 0, 8, 4); /* USB1VBUS -> USB1VBUS */
- sg_set_pinsel(56, 0, 8, 4); /* USB1OD -> USB1OD */
- /* sg_set_pinsel(67, 23, 8, 4); */ /* PCOE -> USB2VBUS */
- /* sg_set_pinsel(68, 23, 8, 4); */ /* PCWAIT -> USB2OD */
-#endif
-
tmp = readl(SG_IECTRL);
tmp |= 0x41;
writel(tmp, SG_IECTRL);
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c
index d5541a9..b08ca1e 100644
--- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c
+++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c
@@ -40,12 +40,5 @@ void ph1_pro4_pin_init(void)
sg_set_pinsel(183, 0, 4, 8); /* USB1OD -> USB1OD */
#endif
-#ifdef CONFIG_USB_EHCI
- sg_set_pinsel(184, 0, 4, 8); /* USB2VBUS -> USB2VBUS */
- sg_set_pinsel(185, 0, 4, 8); /* USB2OD -> USB2OD */
- sg_set_pinsel(187, 0, 4, 8); /* USB3VBUS -> USB3VBUS */
- sg_set_pinsel(188, 0, 4, 8); /* USB3OD -> USB3OD */
-#endif
-
writel(1, SG_LOADPINCTRL);
}
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c
index 6763584..f3fae1d 100644
--- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c
+++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c
@@ -32,13 +32,4 @@ void ph1_sld8_pin_init(void)
sg_set_pinsel(30, 0, 8, 4); /* NFD6_GB -> NFD6_GB */
sg_set_pinsel(31, 0, 8, 4); /* NFD7_GB -> NFD7_GB */
#endif
-
-#ifdef CONFIG_USB_EHCI
- sg_set_pinsel(41, 0, 8, 4); /* USB0VBUS -> USB0VBUS */
- sg_set_pinsel(42, 0, 8, 4); /* USB0OD -> USB0OD */
- sg_set_pinsel(43, 0, 8, 4); /* USB1VBUS -> USB1VBUS */
- sg_set_pinsel(44, 0, 8, 4); /* USB1OD -> USB1OD */
- /* sg_set_pinsel(114, 1, 8, 4); */ /* TXD1 -> USB2VBUS (shared with UART) */
- /* sg_set_pinsel(115, 1, 8, 4); */ /* RXD1 -> USB2OD */
-#endif
}
--
1.9.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH 11/13] usb: remove UniPhier EHCI driver
2016-02-02 12:11 ` [U-Boot] [PATCH 11/13] usb: remove UniPhier EHCI driver Masahiro Yamada
@ 2016-02-02 12:12 ` Marek Vasut
0 siblings, 0 replies; 16+ messages in thread
From: Marek Vasut @ 2016-02-02 12:12 UTC (permalink / raw)
To: u-boot
On Tuesday, February 02, 2016 at 01:11:38 PM, Masahiro Yamada wrote:
> Currently, what this driver does is just to set the base address and
> reset/clock handling. The latter is cared by the clock driver now.
> There is nothing special for this EHCI controller.
>
> I want to use the generic-ehci driver rather than bothering to convert
> this driver to Driver Model.
>
> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Excellent, thanks!
Acked-by: Marek Vasut <marex@denx.de>
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [PATCH 00/13] ARM: uniphier: a collection of clean-ups and new clock driver
2016-02-02 12:11 [U-Boot] [PATCH 00/13] ARM: uniphier: a collection of clean-ups and new clock driver Masahiro Yamada
` (12 preceding siblings ...)
2016-02-02 12:11 ` [U-Boot] [PATCH 13/13] ARM: uniphier: drop unneeded EHCI pin mux settings Masahiro Yamada
@ 2016-02-14 8:29 ` Masahiro Yamada
13 siblings, 0 replies; 16+ messages in thread
From: Masahiro Yamada @ 2016-02-14 8:29 UTC (permalink / raw)
To: u-boot
2016-02-02 21:11 GMT+09:00 Masahiro Yamada <yamada.masahiro@socionext.com>:
>
>
>
> Masahiro Yamada (13):
> ARM: uniphier: change stack pointer address for SPL
> ARM: uniphier: create early page table at run-time
> ARM: uniphier: add missing static qualifier
> ARM: uniphier: support USB boot mode for ProXstream2 / PH1-LD6b SoC
> clk: uniphier: add Media I/O clock driver for UniPhier SoCs
> ARM: dts: uniphier: add reference clock nodes
> ARM: dts: uniphier: add device nodes for system control blocks
> ARM: dts: uniphier: add device nodes for Peripheral control block
> ARM: dts: uniphier: add device nodes for MIO control block
> ARM: dts: uniphier: switch to use clock drivers
> usb: remove UniPhier EHCI driver
> ARM: uniphier: enable generic EHCI driver
> ARM: uniphier: drop unneeded EHCI pin mux settings
Series, applied to u-boot-uniphier/master.
--
Best Regards
Masahiro Yamada
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2016-02-14 8:29 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2016-02-02 12:11 [U-Boot] [PATCH 00/13] ARM: uniphier: a collection of clean-ups and new clock driver Masahiro Yamada
2016-02-02 12:11 ` [U-Boot] [PATCH 01/13] ARM: uniphier: change stack pointer address for SPL Masahiro Yamada
2016-02-02 12:11 ` [U-Boot] [PATCH 02/13] ARM: uniphier: create early page table at run-time Masahiro Yamada
2016-02-02 12:11 ` [U-Boot] [PATCH 03/13] ARM: uniphier: add missing static qualifier Masahiro Yamada
2016-02-02 12:11 ` [U-Boot] [PATCH 04/13] ARM: uniphier: support USB boot mode for ProXstream2 / PH1-LD6b SoC Masahiro Yamada
2016-02-02 12:11 ` [U-Boot] [PATCH 05/13] clk: uniphier: add Media I/O clock driver for UniPhier SoCs Masahiro Yamada
2016-02-02 12:11 ` [U-Boot] [PATCH 06/13] ARM: dts: uniphier: add reference clock nodes Masahiro Yamada
2016-02-02 12:11 ` [U-Boot] [PATCH 07/13] ARM: dts: uniphier: add device nodes for system control blocks Masahiro Yamada
2016-02-02 12:11 ` [U-Boot] [PATCH 08/13] ARM: dts: uniphier: add device nodes for Peripheral control block Masahiro Yamada
2016-02-02 12:11 ` [U-Boot] [PATCH 09/13] ARM: dts: uniphier: add device nodes for MIO " Masahiro Yamada
2016-02-02 12:11 ` [U-Boot] [PATCH 10/13] ARM: dts: uniphier: switch to use clock drivers Masahiro Yamada
2016-02-02 12:11 ` [U-Boot] [PATCH 11/13] usb: remove UniPhier EHCI driver Masahiro Yamada
2016-02-02 12:12 ` Marek Vasut
2016-02-02 12:11 ` [U-Boot] [PATCH 12/13] ARM: uniphier: enable generic " Masahiro Yamada
2016-02-02 12:11 ` [U-Boot] [PATCH 13/13] ARM: uniphier: drop unneeded EHCI pin mux settings Masahiro Yamada
2016-02-14 8:29 ` [U-Boot] [PATCH 00/13] ARM: uniphier: a collection of clean-ups and new clock driver Masahiro Yamada
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