[U-Boot] [PATCH 40/60] ARM: tegra: remove gp_padctrl.h

Stephen Warren
2016-04-19T20:59:20Z

From: Stephen Warren <swarren@nvidia.com>

The only place this is still used is Tegra20's warmboot.c. Keep the T20
copy around for that use, but remove the other unused duplicates.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
arch/arm/include/asm/arch-tegra/gp_padctrl.h | 24 --------
arch/arm/include/asm/arch-tegra/tegra.h | 1 -
arch/arm/include/asm/arch-tegra114/gp_padctrl.h | 67 ---------------------
arch/arm/include/asm/arch-tegra124/gp_padctrl.h | 68 ----------------------
arch/arm/include/asm/arch-tegra210/gp_padctrl.h | 68 ----------------------
arch/arm/include/asm/arch-tegra30/gp_padctrl.h | 49 ----------------
.../tegra20}/gp_padctrl.h | 13 +++--
arch/arm/mach-tegra/tegra20/warmboot.c | 2 +-
board/toradex/colibri_t30/colibri_t30.c | 1 -
9 files changed, 9 insertions(+), 284 deletions(-)
delete mode 100644 arch/arm/include/asm/arch-tegra/gp_padctrl.h
delete mode 100644 arch/arm/include/asm/arch-tegra114/gp_padctrl.h
delete mode 100644 arch/arm/include/asm/arch-tegra124/gp_padctrl.h
delete mode 100644 arch/arm/include/asm/arch-tegra210/gp_padctrl.h
delete mode 100644 arch/arm/include/asm/arch-tegra30/gp_padctrl.h
rename arch/arm/{include/asm/arch-tegra20 => mach-tegra/tegra20}/gp_padctrl.h (88%)

diff --git a/arch/arm/include/asm/arch-tegra/gp_padctrl.h b/arch/arm/include/asm/arch-tegra/gp_padctrl.h
deleted file mode 100644
index 854966a30f9e..000000000000
--- a/arch/arm/include/asm/arch-tegra/gp_padctrl.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * (C) Copyright 2010-2016
- * NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _TEGRA_GP_PADCTRL_H_
-#define _TEGRA_GP_PADCTRL_H_
-
-/* bit fields definitions for APB_MISC_GP_HIDREV register */
-#define HIDREV_CHIPID_SHIFT 8
-#define HIDREV_CHIPID_MASK (0xff << HIDREV_CHIPID_SHIFT)
-#define HIDREV_MAJORPREV_SHIFT 4
-#define HIDREV_MAJORPREV_MASK (0xf << HIDREV_MAJORPREV_SHIFT)
-
-/* CHIPID field returned from APB_MISC_GP_HIDREV register */
-#define CHIPID_TEGRA20 0x20
-#define CHIPID_TEGRA30 0x30
-#define CHIPID_TEGRA114 0x35
-#define CHIPID_TEGRA124 0x40
-#define CHIPID_TEGRA210 0x21
-
-#endif /* _TEGRA_GP_PADCTRL_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h
index 4051a7d26630..0de6aedf6b2a 100644
--- a/arch/arm/include/asm/arch-tegra/tegra.h
+++ b/arch/arm/include/asm/arch-tegra/tegra.h
@@ -18,7 +18,6 @@
#define NV_PA_GPIO_BASE 0x6000D000
#define NV_PA_EVP_BASE 0x6000F000
#define NV_PA_APB_MISC_BASE 0x70000000
-#define NV_PA_APB_MISC_GP_BASE (NV_PA_APB_MISC_BASE + 0x0800)
#define NV_PA_APB_UARTA_BASE (NV_PA_APB_MISC_BASE + 0x6000)
#define NV_PA_APB_UARTB_BASE (NV_PA_APB_MISC_BASE + 0x6040)
#define NV_PA_APB_UARTC_BASE (NV_PA_APB_MISC_BASE + 0x6200)
diff --git a/arch/arm/include/asm/arch-tegra114/gp_padctrl.h b/arch/arm/include/asm/arch-tegra114/gp_padctrl.h
deleted file mode 100644
index 24416f4a5c52..000000000000
--- a/arch/arm/include/asm/arch-tegra114/gp_padctrl.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#ifndef _TEGRA114_GP_PADCTRL_H_
-#define _TEGRA114_GP_PADCTRL_H_
-
-#include <asm/arch-tegra/gp_padctrl.h>
-
-/* APB_MISC_GP and padctrl registers */
-struct apb_misc_gp_ctlr {
- u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */
- u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */
- u32 reserved0[22]; /* 0x08 - 0x5C: */
- u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */
- u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
- u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
- u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */
- u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
- u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
- u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
- u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */
- u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */
- u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */
- u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */
- u32 reserved1; /* 0x8C: */
- u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */
- u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */
- u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */
- u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */
- u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */
- u32 reserved2[3]; /* 0xA4 - 0xAC: */
- u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */
- u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */
- u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */
- u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */
- u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */
- u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */
- u32 reserved3[9]; /* 0xC8-0xE8: */
- u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */
- u32 reserved4[3]; /* 0xF0-0xF8: */
- u32 ddccfg; /* 0xFC: APB_MISC_GP_DDCCFGPADCTRL */
- u32 gmacfg; /* 0x100: APB_MISC_GP_GMACFGPADCTRL */
- u32 reserved5[3]; /* 0x104-0x10C: */
- u32 gmecfg; /* 0x110: APB_MISC_GP_GMECFGPADCTRL */
- u32 gmfcfg; /* 0x114: APB_MISC_GP_GMFCFGPADCTRL */
- u32 gmgcfg; /* 0x118: APB_MISC_GP_GMGCFGPADCTRL */
- u32 gmhcfg; /* 0x11C: APB_MISC_GP_GMHCFGPADCTRL */
- u32 owrcfg; /* 0x120: APB_MISC_GP_OWRCFGPADCTRL */
- u32 uadcfg; /* 0x124: APB_MISC_GP_UADCFGPADCTRL */
- u32 reserved6; /* 0x128: */
- u32 dev3cfg; /* 0x12C: APB_MISC_GP_DEV3CFGPADCTRL */
- u32 reserved7[2]; /* 0x130 - 0x134: */
- u32 ceccfg; /* 0x138: APB_MISC_GP_CECCFGPADCTRL */
- u32 reserved8[22]; /* 0x13C - 0x190: */
- u32 atcfg6; /* 0x194: APB_MISC_GP_ATCFG6PADCTRL */
- u32 dap5cfg; /* 0x198: APB_MISC_GP_DAP5CFGPADCTRL */
- u32 vbuscfg; /* 0x19C: APB_MISC_GP_USBVBUSENCFGPADCTRL */
- u32 aocfg3; /* 0x1A0: APB_MISC_GP_AOCFG3PADCTRL */
- u32 hvccfg0; /* 0x1A4: APB_MISC_GP_HVCCFG0PADCTRL */
- u32 sdio4cfg; /* 0x1A8: APB_MISC_GP_SDIO4CFGPADCTRL */
- u32 aocfg0; /* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */
-};
-
-#endif /* _TEGRA114_GP_PADCTRL_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/gp_padctrl.h b/arch/arm/include/asm/arch-tegra124/gp_padctrl.h
deleted file mode 100644
index 406edd0d7ea6..000000000000
--- a/arch/arm/include/asm/arch-tegra124/gp_padctrl.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * (C) Copyright 2010-2016
- * NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _TEGRA124_GP_PADCTRL_H_
-#define _TEGRA124_GP_PADCTRL_H_
-
-#include <asm/arch-tegra/gp_padctrl.h>
-
-/* APB_MISC_GP and padctrl registers */
-struct apb_misc_gp_ctlr {
- u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */
- u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */
- u32 reserved0[22]; /* 0x08 - 0x5C: */
- u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */
- u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
- u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
- u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */
- u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
- u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
- u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
- u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */
- u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */
- u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */
- u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */
- u32 reserved1; /* 0x8C: */
- u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */
- u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */
- u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */
- u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */
- u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */
- u32 reserved2[3]; /* 0xA4 - 0xAC: */
- u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */
- u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */
- u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */
- u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */
- u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */
- u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */
- u32 reserved3[9]; /* 0xC8-0xE8: */
- u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */
- u32 reserved4[3]; /* 0xF0-0xF8: */
- u32 ddccfg; /* 0xFC: APB_MISC_GP_DDCCFGPADCTRL */
- u32 gmacfg; /* 0x100: APB_MISC_GP_GMACFGPADCTRL */
- u32 reserved5[3]; /* 0x104-0x10C: */
- u32 gmecfg; /* 0x110: APB_MISC_GP_GMECFGPADCTRL */
- u32 gmfcfg; /* 0x114: APB_MISC_GP_GMFCFGPADCTRL */
- u32 gmgcfg; /* 0x118: APB_MISC_GP_GMGCFGPADCTRL */
- u32 gmhcfg; /* 0x11C: APB_MISC_GP_GMHCFGPADCTRL */
- u32 owrcfg; /* 0x120: APB_MISC_GP_OWRCFGPADCTRL */
- u32 uadcfg; /* 0x124: APB_MISC_GP_UADCFGPADCTRL */
- u32 reserved6; /* 0x128: */
- u32 dev3cfg; /* 0x12C: APB_MISC_GP_DEV3CFGPADCTRL */
- u32 reserved7[2]; /* 0x130 - 0x134: */
- u32 ceccfg; /* 0x138: APB_MISC_GP_CECCFGPADCTRL */
- u32 reserved8[22]; /* 0x13C - 0x190: */
- u32 atcfg6; /* 0x194: APB_MISC_GP_ATCFG6PADCTRL */
- u32 dap5cfg; /* 0x198: APB_MISC_GP_DAP5CFGPADCTRL */
- u32 vbuscfg; /* 0x19C: APB_MISC_GP_USBVBUSENCFGPADCTRL */
- u32 aocfg3; /* 0x1A0: APB_MISC_GP_AOCFG3PADCTRL */
- u32 hvccfg0; /* 0x1A4: APB_MISC_GP_HVCCFG0PADCTRL */
- u32 sdio4cfg; /* 0x1A8: APB_MISC_GP_SDIO4CFGPADCTRL */
- u32 aocfg0; /* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */
-};
-
-#endif /* _TEGRA124_GP_PADCTRL_H_ */
diff --git a/arch/arm/include/asm/arch-tegra210/gp_padctrl.h b/arch/arm/include/asm/arch-tegra210/gp_padctrl.h
deleted file mode 100644
index ead620534c7d..000000000000
--- a/arch/arm/include/asm/arch-tegra210/gp_padctrl.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * (C) Copyright 2010-2016
- * NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _TEGRA210_GP_PADCTRL_H_
-#define _TEGRA210_GP_PADCTRL_H_
-
-#include <asm/arch-tegra/gp_padctrl.h>
-
-/* APB_MISC_GP and padctrl registers */
-struct apb_misc_gp_ctlr {
- u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */
- u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */
- u32 reserved0[22]; /* 0x08 - 0x5C: */
- u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */
- u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
- u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
- u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */
- u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
- u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
- u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
- u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */
- u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */
- u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */
- u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */
- u32 reserved1; /* 0x8C: */
- u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */
- u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */
- u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */
- u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */
- u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */
- u32 reserved2[3]; /* 0xA4 - 0xAC: */
- u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */
- u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */
- u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */
- u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */
- u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */
- u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */
- u32 reserved3[9]; /* 0xC8-0xE8: */
- u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */
- u32 reserved4[3]; /* 0xF0-0xF8: */
- u32 ddccfg; /* 0xFC: APB_MISC_GP_DDCCFGPADCTRL */
- u32 gmacfg; /* 0x100: APB_MISC_GP_GMACFGPADCTRL */
- u32 reserved5[3]; /* 0x104-0x10C: */
- u32 gmecfg; /* 0x110: APB_MISC_GP_GMECFGPADCTRL */
- u32 gmfcfg; /* 0x114: APB_MISC_GP_GMFCFGPADCTRL */
- u32 gmgcfg; /* 0x118: APB_MISC_GP_GMGCFGPADCTRL */
- u32 gmhcfg; /* 0x11C: APB_MISC_GP_GMHCFGPADCTRL */
- u32 owrcfg; /* 0x120: APB_MISC_GP_OWRCFGPADCTRL */
- u32 uadcfg; /* 0x124: APB_MISC_GP_UADCFGPADCTRL */
- u32 reserved6; /* 0x128: */
- u32 dev3cfg; /* 0x12C: APB_MISC_GP_DEV3CFGPADCTRL */
- u32 reserved7[2]; /* 0x130 - 0x134: */
- u32 ceccfg; /* 0x138: APB_MISC_GP_CECCFGPADCTRL */
- u32 reserved8[22]; /* 0x13C - 0x190: */
- u32 atcfg6; /* 0x194: APB_MISC_GP_ATCFG6PADCTRL */
- u32 dap5cfg; /* 0x198: APB_MISC_GP_DAP5CFGPADCTRL */
- u32 vbuscfg; /* 0x19C: APB_MISC_GP_USBVBUSENCFGPADCTRL */
- u32 aocfg3; /* 0x1A0: APB_MISC_GP_AOCFG3PADCTRL */
- u32 hvccfg0; /* 0x1A4: APB_MISC_GP_HVCCFG0PADCTRL */
- u32 sdio4cfg; /* 0x1A8: APB_MISC_GP_SDIO4CFGPADCTRL */
- u32 aocfg0; /* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */
-};
-
-#endif /* _TEGRA210_GP_PADCTRL_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/gp_padctrl.h b/arch/arm/include/asm/arch-tegra30/gp_padctrl.h
deleted file mode 100644
index 5453555d3ea3..000000000000
--- a/arch/arm/include/asm/arch-tegra30/gp_padctrl.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#ifndef _TEGRA30_GP_PADCTRL_H_
-#define _TEGRA30_GP_PADCTRL_H_
-
-#include <asm/arch-tegra/gp_padctrl.h>
-
-/* APB_MISC_GP and padctrl registers */
-struct apb_misc_gp_ctlr {
- u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */
- u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */
- u32 reserved0[22]; /* 0x08 - 0x5C: */
- u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */
- u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
- u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
- u32 aocfg2; /* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */
- u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
- u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
- u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
- u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */
- u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */
- u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */
- u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */
- u32 csuscfg; /* 0x8C: APB_MISC_GP_CSUSCFGPADCTRL */
- u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */
- u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */
- u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */
- u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */
- u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */
- u32 lcdcfg1; /* 0xA4: APB_MISC_GP_LCDCFG1PADCTRL */
- u32 lcdcfg2; /* 0xA8: APB_MISC_GP_LCDCFG2PADCTRL */
- u32 sdio2cfg; /* 0xAC: APB_MISC_GP_SDIO2CFGPADCTRL */
- u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */
- u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */
- u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */
- u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */
- u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */
- u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */
- u32 vicfg1; /* 0xC8: APB_MISC_GP_VICFG1PADCTRL */
- u32 vivttgen; /* 0xCC: APB_MISC_GP_VIVTTGENPADCTRL */
- u32 reserved1[7]; /* 0xD0-0xE8: */
- u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */
-};
-
-#endif /* _TEGRA30_GP_PADCTRL_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/gp_padctrl.h b/arch/arm/mach-tegra/tegra20/gp_padctrl.h
similarity index 88%
rename from arch/arm/include/asm/arch-tegra20/gp_padctrl.h
rename to arch/arm/mach-tegra/tegra20/gp_padctrl.h
index 6631871ce574..99fc2044f05c 100644
--- a/arch/arm/include/asm/arch-tegra20/gp_padctrl.h
+++ b/arch/arm/mach-tegra/tegra20/gp_padctrl.h
@@ -1,14 +1,14 @@
/*
- * (C) Copyright 2010,2011
+ * (C) Copyright 2010-2016
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/

-#ifndef _TEGRA20_GP_PADCTRL_H_
-#define _TEGRA20_GP_PADCTRL_H_
+#ifndef _TEGRA20_GP_PADCTRL_H
+#define _TEGRA20_GP_PADCTRL_H

-#include <asm/arch-tegra/gp_padctrl.h>
+#define NV_PA_APB_MISC_GP_BASE (NV_PA_APB_MISC_BASE + 0x0800)

/* APB_MISC_GP and padctrl registers */
struct apb_misc_gp_ctlr {
@@ -47,4 +47,7 @@ struct apb_misc_gp_ctlr {
u32 memcomp; /* 0xD4: APB_MISC_GP_MEMCOMPPADCTRL */
};

-#endif /* _TEGRA20_GP_PADCTRL_H_ */
+#define HIDREV_MAJORPREV_SHIFT 4
+#define HIDREV_MAJORPREV_MASK (0xf << HIDREV_MAJORPREV_SHIFT)
+
+#endif
diff --git a/arch/arm/mach-tegra/tegra20/warmboot.c b/arch/arm/mach-tegra/tegra20/warmboot.c
index 1159f05a5dc3..dd3da116faef 100644
--- a/arch/arm/mach-tegra/tegra20/warmboot.c
+++ b/arch/arm/mach-tegra/tegra20/warmboot.c
@@ -9,7 +9,6 @@
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/arch/clock.h>
-#include <asm/arch/gp_padctrl.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/clk_rst.h>
@@ -19,6 +18,7 @@
#include "../pmc.h"
#include "crypto.h"
#include "emc_priv.h"
+#include "gp_padctrl.h"
#include "sdram_param.h"
#include "warmboot.h"

diff --git a/board/toradex/colibri_t30/colibri_t30.c b/board/toradex/colibri_t30/colibri_t30.c
index 4312f79f2d00..e0e7deef579a 100644
--- a/board/toradex/colibri_t30/colibri_t30.c
+++ b/board/toradex/colibri_t30/colibri_t30.c
@@ -11,7 +11,6 @@
#include <dt-bindings/gpio/tegra-gpio.h>
#include <asm/gpio.h>
#include <asm/io.h>
-#include <asm/arch/gp_padctrl.h>
#include <asm/arch/pinmux.h>
#include <asm/arch-tegra/tegra.h>
#include "pinmux-config-colibri_t30.h"
--
2.8.1