From mboxrd@z Thu Jan 1 00:00:00 1970 From: Vignesh R Date: Fri, 20 May 2016 16:11:22 +0530 Subject: [U-Boot] [PATCH] ARM: dts: dra7x: Support QSPI MODE-0 operation at 64MHz Message-ID: <20160520104122.3539-1-vigneshr@ti.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de According to Data Manual(SPRS915P) of AM57x, TI QSPI controller on DRA74(rev 1.1+)/DRA72 EVM can support up to 64MHz in MODE-0, whereas MODE-3 is limited to 48MHz. Hence, switch to MODE-0 for better throughput. Signed-off-by: Vignesh R --- arch/arm/dts/dra7-evm.dts | 6 ++---- arch/arm/dts/dra72-evm.dts | 6 ++---- 2 files changed, 4 insertions(+), 8 deletions(-) diff --git a/arch/arm/dts/dra7-evm.dts b/arch/arm/dts/dra7-evm.dts index 08ef04e177b0..429b9edc1b2b 100644 --- a/arch/arm/dts/dra7-evm.dts +++ b/arch/arm/dts/dra7-evm.dts @@ -491,15 +491,13 @@ pinctrl-names = "default"; pinctrl-0 = <&qspi1_pins>; - spi-max-frequency = <48000000>; + spi-max-frequency = <64000000>; m25p80 at 0 { compatible = "s25fl256s1","spi-flash"; - spi-max-frequency = <48000000>; + spi-max-frequency = <64000000>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; - spi-cpol; - spi-cpha; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/dts/dra72-evm.dts b/arch/arm/dts/dra72-evm.dts index 205103e2b0e1..ced2f1166d8c 100644 --- a/arch/arm/dts/dra72-evm.dts +++ b/arch/arm/dts/dra72-evm.dts @@ -603,15 +603,13 @@ pinctrl-names = "default"; pinctrl-0 = <&qspi1_pins>; - spi-max-frequency = <48000000>; + spi-max-frequency = <64000000>; m25p80 at 0 { compatible = "s25fl256s1","spi-flash"; - spi-max-frequency = <48000000>; + spi-max-frequency = <64000000>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; - spi-cpol; - spi-cpha; #address-cells = <1>; #size-cells = <1>; -- 2.8.3