From mboxrd@z Thu Jan  1 00:00:00 1970
From: Tom Rini <trini@konsulko.com>
Date: Fri, 22 Jul 2016 09:42:20 -0400
Subject: [U-Boot] [PATCH 1/2] ARM: am33xx: Fix DDR init delay placement
In-Reply-To: <1469100512-5467-2-git-send-email-Russ.Dill@ti.com>
References: <1469100512-5467-1-git-send-email-Russ.Dill@ti.com>
 <1469100512-5467-2-git-send-email-Russ.Dill@ti.com>
Message-ID: <20160722134220.GI14698@bill-the-cat>
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On Thu, Jul 21, 2016 at 04:28:31AM -0700, Russ Dill wrote:

> The delay needs to be before the write to ref_ctrl register
> which initiates refreshes. An improper initialization sequence
> generates an L3 noc error.
> 
> Signed-off-by: Russ Dill <Russ.Dill@ti.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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