From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tom Rini Date: Mon, 25 Jul 2016 09:38:00 -0400 Subject: [U-Boot] [PATCH 0/4] dra7xx: QSPI: Increase SPI bus speed. In-Reply-To: <20160725101547.18503-1-vigneshr@ti.com> References: <20160725101547.18503-1-vigneshr@ti.com> Message-ID: <20160725133800.GC14698@bill-the-cat> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Mon, Jul 25, 2016 at 03:45:43PM +0530, Vignesh R wrote: > By configuring DPLL_PER_HS13 divider value to provide 76.8MHz clock as > QSPI fclk on dra7xx, it is possible to operate SPI slave clock at > 768.MHz which is the maximum supported frequency as per AM572x DM > SPRS953A. This helps to increase flash read speed by ~2MB/s. > > Tested on DRA74 Rev G & H, DRA72 Rev B & C EVMs. And for the record, there is no HW that exists "in the wild" that would not support these options, yes? Thanks! -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: