From mboxrd@z Thu Jan  1 00:00:00 1970
From: Tom Rini <trini@konsulko.com>
Date: Mon, 25 Jul 2016 09:38:07 -0400
Subject: [U-Boot] [PATCH 1/4] ARM: dra7xx: Change DPLL_PER_HS13 divider
	value
In-Reply-To: <20160725101547.18503-2-vigneshr@ti.com>
References: <20160725101547.18503-1-vigneshr@ti.com>
 <20160725101547.18503-2-vigneshr@ti.com>
Message-ID: <20160725133807.GD14698@bill-the-cat>
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To: u-boot@lists.denx.de

On Mon, Jul 25, 2016 at 03:45:44PM +0530, Vignesh R wrote:

> From: Lokesh Vutla <lokeshvutla@ti.com>
> 
> According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, hence
> update QSPI input clock divider value (DPLL_PER_HS13) to provide 76.8MHz
> clock, so that driver can use the same.
> 
> Signed-off-by: Vignesh R <vigneshr@ti.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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