[U-Boot] [PATCH 2/3] net: davinci_emac: Round up top buffer boundaries for dcache ops

[Karl Beldan <kbeldan@baylibre.com>]

On Sun, Aug 14, 2016 at 11:47:25AM -0400, Tom Rini wrote:
> On Sun, Aug 14, 2016 at 03:03:16PM +0000, Karl Beldan wrote:
> 
> > check_cache_range() warns that the top boundaries are not properly
> > aligned while flushing and invalidating the buffers and make these
> > operations to fail.
> > ATM the RX bottom boundaries are aligned by design with EMAC_RXBUF_SIZE,
> > properly aligned with ARCH_DMA_MINALIGN, however the top ones are not.
> > 
> > This gets rid of the warnings:
> > CACHE: Misaligned operation at range
> > 
> > Signed-off-by: Karl Beldan <karl.beldan+oss@gmail.com>
> > ---
> >  drivers/net/davinci_emac.c | 6 ++++--
> >  1 file changed, 4 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c
> > index 947bfab..55461b0 100644
> > --- a/drivers/net/davinci_emac.c
> > +++ b/drivers/net/davinci_emac.c
> > @@ -632,7 +632,8 @@ static int davinci_eth_send_packet (struct eth_device *dev,
> >  				      EMAC_CPPI_EOP_BIT);
> >  
> >  	flush_dcache_range((unsigned long)packet,
> > -			(unsigned long)packet + length);
> > +			   round_up((unsigned long)packet + length,
> > +				    ARCH_DMA_MINALIGN));
> 
> It's preferred to use:
>                         (unsigned long)packet + ALIGN(length, PKTALIGN)); 
> here instead of ARCH_DMA_MINALIGN.
> 

Hmm, I think your suggestion is buggy.
The cache primitives act on [laddr, haddr[, i.e. haddr is excluded, IOW
you are missing the tail of the packet (that's why I rounded up).

Conceptually I still prefer ARCH_DMA_MINALIGN, also all other code in
the base does so.

Rgds, 
Karl