From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefan Agner Date: Sun, 14 Aug 2016 21:33:01 -0700 Subject: [U-Boot] [PATCH v5 2/2] arm: cache: always flush cache line size for page table In-Reply-To: <20160815043301.29276-1-stefan@agner.ch> References: <20160815043301.29276-1-stefan@agner.ch> Message-ID: <20160815043301.29276-2-stefan@agner.ch> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From: Stefan Agner The page table is maintained by the CPU, hence it is safe to always align cache flush to a whole cache line size. This allows to use mmu_page_table_flush for a single page table, e.g. when configure only small regions through mmu_set_region_dcache_behaviour. Signed-off-by: Stefan Agner Tested-by: Fabio Estevam Reviewed-by: Simon Glass Reviewed-by: Heiko Schocher --- Changes in v5: - Convert to a type the size of a CPU pointer (unsigned long) - Rebase on LPAE enablement patch Changes in v4: - Fixed spelling misstake for real Changes in v3: - Fixed spelling misstake Changes in v2: - Move cache line alignment from mmu_page_table_flush to mmu_set_region_dcache_behaviour arch/arm/lib/cache-cp15.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 3aabda1..70e94f0 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -66,6 +66,7 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, #else u32 *page_table = (u32 *)gd->arch.tlb_addr; #endif + unsigned long startpt, stoppt; unsigned long upto, end; end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT; @@ -74,7 +75,18 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, option); for (upto = start; upto < end; upto++) set_section_dcache(upto, option); - mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]); + + /* + * Make sure range is cache line aligned + * Only CPU maintains page tables, hence it is safe to always + * flush complete cache lines... + */ + + startpt = (unsigned long)&page_table[start]; + startpt &= ~(CONFIG_SYS_CACHELINE_SIZE - 1); + stoppt = (unsigned long)&page_table[end]; + stoppt = ALIGN(stoppt, CONFIG_SYS_CACHELINE_SIZE); + mmu_page_table_flush(startpt, stoppt); } __weak void dram_bank_mmu_setup(int bank) -- 2.9.0