[U-Boot] [PATCH v1 1/2] arm: mvebu: Add support for NAND interface on A-38x

[U-Boot] [PATCH v1 1/2] arm: mvebu: Add support for NAND interface on A-38x

[Chris Packham]

From: Chris Packham <chris.packham@alliedtelesis.co.nz>

The NAND interface on the Armada-38x series is similar to that on the
Armada-XP. The key difference is that the NAND ECC clock ratio is
provided via the DFX Server registers instead of the Core Clock.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <eibach@gdsys.de>
---
I haven't got access to any Armada-375 docs so I wasn't sure if
I should include it in the condition. For now it'll fall back to using
the same clock control register as the Armada-XP.

 arch/arm/mach-mvebu/cpu.c              | 9 ++++++++-
 arch/arm/mach-mvebu/include/mach/soc.h | 2 ++
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index fd66f59..5eb2a39 100644
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -452,8 +452,15 @@ int arch_cpu_init(void)
 
 u32 mvebu_get_nand_clock(void)
 {
+	u32 reg;
+
+	if (mvebu_soc_family() == MVEBU_SOC_A38X)
+		reg = MVEBU_DFX_DIV_CLK_CTRL(1);
+	else
+		reg = MVEBU_CORE_DIV_CLK_CTRL(1);
+
 	return CONFIG_SYS_MVEBU_PLL_CLOCK /
-		((readl(MVEBU_CORE_DIV_CLK_CTRL(1)) &
+		((readl(reg) &
 		  NAND_ECC_DIVCKL_RATIO_MASK) >> NAND_ECC_DIVCKL_RATIO_OFFS);
 }
 
diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h
index 13c9f29..6342cdc 100644
--- a/arch/arm/mach-mvebu/include/mach/soc.h
+++ b/arch/arm/mach-mvebu/include/mach/soc.h
@@ -73,6 +73,7 @@
 #define MVEBU_NAND_BASE		(MVEBU_REGISTER(0xd0000))
 #define MVEBU_SDIO_BASE		(MVEBU_REGISTER(0xd8000))
 #define MVEBU_LCD_BASE		(MVEBU_REGISTER(0xe0000))
+#define MVEBU_DFX_BASE		(MVEBU_REGISTER(0xe4000))
 
 #define SOC_COHERENCY_FABRIC_CTRL_REG	(MVEBU_REGISTER(0x20200))
 #define MBUS_ERR_PROP_EN	(1 << 8)
@@ -92,6 +93,7 @@
 #define SPI_PUP_EN		BIT(5)
 
 #define MVEBU_CORE_DIV_CLK_CTRL(i)	(MVEBU_CLOCK_BASE + ((i) * 0x8))
+#define MVEBU_DFX_DIV_CLK_CTRL(i)	(MVEBU_DFX_BASE + 0x250 + ((i) * 0x4))
 #define NAND_ECC_DIVCKL_RATIO_OFFS	8
 #define NAND_ECC_DIVCKL_RATIO_MASK	(0x3F << NAND_ECC_DIVCKL_RATIO_OFFS)
 
-- 
2.9.2.518.ged577c6.dirty

[U-Boot] [PATCH v1 2/2] arm: mvebu: Define NAND interface pins for A-38x

[Chris Packham]

From: Chris Packham <chris.packham@alliedtelesis.co.nz>

Add pin control settings for the NAND flash interface. This interface
is multiplexed with the device bus interface to the function is "dev"
not "nand" as one might expect.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <eibach@gdsys.de>
---
I don't think this is strictly necessary. A quick scan of boards that
use this family of processor all seem to set their MPP configurations
manually.

Another issue is that technically on the Armada-385 there are 4 possible
CE pins. The board I'm looking at happens to use CE#0 (mpp25) but mpp26,
mpp27 and mpp6 are all potentially available. I guess if any boards
actually use them they can add them to their pin specification. At the
very least such boards would need to update the num-cs property anyway.

 arch/arm/dts/armada-38x.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/dts/armada-38x.dtsi b/arch/arm/dts/armada-38x.dtsi
index dc8a1a6..9ecba8a 100644
--- a/arch/arm/dts/armada-38x.dtsi
+++ b/arch/arm/dts/armada-38x.dtsi
@@ -258,6 +258,14 @@
 					marvell,function = "i2c0";
 				};
 
+				nand_pins: nand-pins {
+					marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33",
+						       "mpp38", "mpp28", "mpp40", "mpp42",
+						       "mpp35", "mpp36", "mpp25", "mpp30",
+						       "mpp32";
+					marvell,function = "dev";
+				};
+
 				mdio_pins: mdio-pins {
 					marvell,pins = "mpp4", "mpp5";
 					marvell,function = "ge";
-- 
2.9.2.518.ged577c6.dirty

[U-Boot] [PATCH v1 2/2] arm: mvebu: Define NAND interface pins for A-38x

[Stefan Roese]

Hi Chris,

On 22.08.2016 02:38, Chris Packham wrote:
> From: Chris Packham <chris.packham@alliedtelesis.co.nz>
>
> Add pin control settings for the NAND flash interface. This interface
> is multiplexed with the device bus interface to the function is "dev"
> not "nand" as one might expect.
>
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> Cc: Luka Perkov <luka.perkov@sartura.hr>
> Cc: Dirk Eibach <eibach@gdsys.de>
> ---
> I don't think this is strictly necessary. A quick scan of boards that
> use this family of processor all seem to set their MPP configurations
> manually.

Correct. Unfortunately we don't have a pin-ctrl driver for AXP / A38x
in U-Boot yet. Such a driver would be very welcome though. ;)

> Another issue is that technically on the Armada-385 there are 4 possible
> CE pins. The board I'm looking at happens to use CE#0 (mpp25) but mpp26,
> mpp27 and mpp6 are all potentially available. I guess if any boards
> actually use them they can add them to their pin specification. At the
> very least such boards would need to update the num-cs property anyway.

How is this handled in the kernel? I would very much like to see
these changes in the dts in sync with the kernel as much as
possible. Does the kernel also use "dev" instead of "nand" here?

Thanks,
Stefan

[U-Boot] [PATCH v1 2/2] arm: mvebu: Define NAND interface pins for A-38x

[Chris Packham]

On Tue, Aug 23, 2016 at 6:57 PM, Stefan Roese <sr@denx.de> wrote:
> Hi Chris,
>
> On 22.08.2016 02:38, Chris Packham wrote:
>>
>> From: Chris Packham <chris.packham@alliedtelesis.co.nz>
>>
>> Add pin control settings for the NAND flash interface. This interface
>> is multiplexed with the device bus interface to the function is "dev"
>> not "nand" as one might expect.
>>
>> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
>> Cc: Luka Perkov <luka.perkov@sartura.hr>
>> Cc: Dirk Eibach <eibach@gdsys.de>
>> ---
>> I don't think this is strictly necessary. A quick scan of boards that
>> use this family of processor all seem to set their MPP configurations
>> manually.
>
>
> Correct. Unfortunately we don't have a pin-ctrl driver for AXP / A38x
> in U-Boot yet. Such a driver would be very welcome though. ;)
>
>> Another issue is that technically on the Armada-385 there are 4 possible
>> CE pins. The board I'm looking at happens to use CE#0 (mpp25) but mpp26,
>> mpp27 and mpp6 are all potentially available. I guess if any boards
>> actually use them they can add them to their pin specification. At the
>> very least such boards would need to update the num-cs property anyway.
>
>
> How is this handled in the kernel?

I haven't seen anything in the kernel yet that uses these chip selects.

> I would very much like to see
> these changes in the dts in sync with the kernel as much as
> possible. Does the kernel also use "dev" instead of "nand" here?

Yes I based this on
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/arm/boot/dts/armada-39x.dtsi
I haven't got round to porting the kernel to my board so I imagine a
similar change will be required to armada-38x.dtsi in the kernel.

>
> Thanks,
> Stefan

[U-Boot] [PATCH v1 2/2] arm: mvebu: Define NAND interface pins for A-38x

[Chris Packham]

Hi Stefan,

On Tue, Aug 23, 2016 at 10:54 PM, Chris Packham <judge.packham@gmail.com> wrote:
> On Tue, Aug 23, 2016 at 6:57 PM, Stefan Roese <sr@denx.de> wrote:
>> Hi Chris,
>>
>> On 22.08.2016 02:38, Chris Packham wrote:
>>>
>>> From: Chris Packham <chris.packham@alliedtelesis.co.nz>
>>>
>>> Add pin control settings for the NAND flash interface. This interface
>>> is multiplexed with the device bus interface to the function is "dev"
>>> not "nand" as one might expect.
>>>
>>> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
>>> Cc: Luka Perkov <luka.perkov@sartura.hr>
>>> Cc: Dirk Eibach <eibach@gdsys.de>
>>> ---
>>> I don't think this is strictly necessary. A quick scan of boards that
>>> use this family of processor all seem to set their MPP configurations
>>> manually.
>>
>>
>> Correct. Unfortunately we don't have a pin-ctrl driver for AXP / A38x
>> in U-Boot yet. Such a driver would be very welcome though. ;)
>>
>>> Another issue is that technically on the Armada-385 there are 4 possible
>>> CE pins. The board I'm looking at happens to use CE#0 (mpp25) but mpp26,
>>> mpp27 and mpp6 are all potentially available. I guess if any boards
>>> actually use them they can add them to their pin specification. At the
>>> very least such boards would need to update the num-cs property anyway.
>>
>>
>> How is this handled in the kernel?
>
> I haven't seen anything in the kernel yet that uses these chip selects.
>
>> I would very much like to see
>> these changes in the dts in sync with the kernel as much as
>> possible. Does the kernel also use "dev" instead of "nand" here?
>
> Yes I based this on
> https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/arm/boot/dts/armada-39x.dtsi
> I haven't got round to porting the kernel to my board so I imagine a
> similar change will be required to armada-38x.dtsi in the kernel.
>

I've sent a kernel patch for the armada-38x[1] so perhaps we should
just drop this one and sync up if/when the kernel patch is accepted.

[1] - http://lists.infradead.org/pipermail/linux-arm-kernel/2016-August/451027.html

[U-Boot] [PATCH v1 2/2] arm: mvebu: Define NAND interface pins for A-38x

[Stefan Roese]

Hi Chris,

On 24.08.2016 02:24, Chris Packham wrote:
> On Tue, Aug 23, 2016 at 10:54 PM, Chris Packham <judge.packham@gmail.com> wrote:
>> On Tue, Aug 23, 2016 at 6:57 PM, Stefan Roese <sr@denx.de> wrote:
>>> Hi Chris,
>>>
>>> On 22.08.2016 02:38, Chris Packham wrote:
>>>>
>>>> From: Chris Packham <chris.packham@alliedtelesis.co.nz>
>>>>
>>>> Add pin control settings for the NAND flash interface. This interface
>>>> is multiplexed with the device bus interface to the function is "dev"
>>>> not "nand" as one might expect.
>>>>
>>>> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
>>>> Cc: Luka Perkov <luka.perkov@sartura.hr>
>>>> Cc: Dirk Eibach <eibach@gdsys.de>
>>>> ---
>>>> I don't think this is strictly necessary. A quick scan of boards that
>>>> use this family of processor all seem to set their MPP configurations
>>>> manually.
>>>
>>>
>>> Correct. Unfortunately we don't have a pin-ctrl driver for AXP / A38x
>>> in U-Boot yet. Such a driver would be very welcome though. ;)
>>>
>>>> Another issue is that technically on the Armada-385 there are 4 possible
>>>> CE pins. The board I'm looking at happens to use CE#0 (mpp25) but mpp26,
>>>> mpp27 and mpp6 are all potentially available. I guess if any boards
>>>> actually use them they can add them to their pin specification. At the
>>>> very least such boards would need to update the num-cs property anyway.
>>>
>>>
>>> How is this handled in the kernel?
>>
>> I haven't seen anything in the kernel yet that uses these chip selects.
>>
>>> I would very much like to see
>>> these changes in the dts in sync with the kernel as much as
>>> possible. Does the kernel also use "dev" instead of "nand" here?
>>
>> Yes I based this on
>> https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/arm/boot/dts/armada-39x.dtsi
>> I haven't got round to porting the kernel to my board so I imagine a
>> similar change will be required to armada-38x.dtsi in the kernel.
>>
>
> I've sent a kernel patch for the armada-38x[1] so perhaps we should
> just drop this one and sync up if/when the kernel patch is accepted.
>
> [1] - http://lists.infradead.org/pipermail/linux-arm-kernel/2016-August/451027.html

Yes, this is better. I'll drop the patch for now and will make sure
that we sync with the kernel at some later time. Perhaps we even
have a pinctrl driver for A38x at that time... ;)

Thanks,
Stefan

[U-Boot] [PATCH v1 1/2] arm: mvebu: Add support for NAND interface on A-38x

[Stefan Roese]

On 22.08.2016 02:38, Chris Packham wrote:
> From: Chris Packham <chris.packham@alliedtelesis.co.nz>
>
> The NAND interface on the Armada-38x series is similar to that on the
> Armada-XP. The key difference is that the NAND ECC clock ratio is
> provided via the DFX Server registers instead of the Core Clock.
>
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> Cc: Luka Perkov <luka.perkov@sartura.hr>
> Cc: Dirk Eibach <eibach@gdsys.de>

Applied to u-boot-marvell/master.

Thanks,
Stefan