From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Packham Date: Mon, 22 Aug 2016 12:38:40 +1200 Subject: [U-Boot] [PATCH v1 2/2] arm: mvebu: Define NAND interface pins for A-38x In-Reply-To: <20160822003840.16992-1-judge.packham@gmail.com> References: <20160822003840.16992-1-judge.packham@gmail.com> Message-ID: <20160822003840.16992-2-judge.packham@gmail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From: Chris Packham Add pin control settings for the NAND flash interface. This interface is multiplexed with the device bus interface to the function is "dev" not "nand" as one might expect. Signed-off-by: Chris Packham Cc: Luka Perkov Cc: Dirk Eibach --- I don't think this is strictly necessary. A quick scan of boards that use this family of processor all seem to set their MPP configurations manually. Another issue is that technically on the Armada-385 there are 4 possible CE pins. The board I'm looking at happens to use CE#0 (mpp25) but mpp26, mpp27 and mpp6 are all potentially available. I guess if any boards actually use them they can add them to their pin specification. At the very least such boards would need to update the num-cs property anyway. arch/arm/dts/armada-38x.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/dts/armada-38x.dtsi b/arch/arm/dts/armada-38x.dtsi index dc8a1a6..9ecba8a 100644 --- a/arch/arm/dts/armada-38x.dtsi +++ b/arch/arm/dts/armada-38x.dtsi @@ -258,6 +258,14 @@ marvell,function = "i2c0"; }; + nand_pins: nand-pins { + marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33", + "mpp38", "mpp28", "mpp40", "mpp42", + "mpp35", "mpp36", "mpp25", "mpp30", + "mpp32"; + marvell,function = "dev"; + }; + mdio_pins: mdio-pins { marvell,pins = "mpp4", "mpp5"; marvell,function = "ge"; -- 2.9.2.518.ged577c6.dirty