From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tom Rini Date: Mon, 29 Aug 2016 08:00:44 -0400 Subject: [U-Boot] [U-Boot, v5, 2/2] arm: cache: always flush cache line size for page table In-Reply-To: <20160815043301.29276-2-stefan@agner.ch> References: <20160815043301.29276-2-stefan@agner.ch> Message-ID: <20160829120044.GD8799@bill-the-cat> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Sun, Aug 14, 2016 at 09:33:01PM -0700, Stefan Agner wrote: > From: Stefan Agner > > The page table is maintained by the CPU, hence it is safe to always > align cache flush to a whole cache line size. This allows to use > mmu_page_table_flush for a single page table, e.g. when configure > only small regions through mmu_set_region_dcache_behaviour. > > Signed-off-by: Stefan Agner > Tested-by: Fabio Estevam > Reviewed-by: Simon Glass > Reviewed-by: Heiko Schocher Applied to u-boot/master, thanks! -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: