From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tom Rini Date: Fri, 2 Sep 2016 10:54:20 -0400 Subject: [U-Boot] [PATCH 1/2] spi: ti_qspi: use 128 bit transfer mode when writing to flash In-Reply-To: <20160901075440.29943-2-vigneshr@ti.com> References: <20160901075440.29943-1-vigneshr@ti.com> <20160901075440.29943-2-vigneshr@ti.com> Message-ID: <20160902145420.GS4990@bill-the-cat> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Thu, Sep 01, 2016 at 01:24:39PM +0530, Vignesh R wrote: > TI QSPI has four 32 bit data registers which can be used to transfer 16 > bytes of data at once. The register group QSPI_SPI_DATA_REG_3, > QSPI_SPI_DATA_REG_2, QSPI_SPI_DATA_REG_1 and QSPI_SPI_DATA_REG is > treated as a single 128-bit word for shifting data in and out. The bit > at QSPI_SPI_DATA_REG_3[31] position is the first bit to be shifted out > in case of 128 bit transfer mode. Therefore the first byte to be written > to flash should be at QSPI_SPI_DATA_REG_3[31-25] position. > Instead of writing 1 byte at a time when interacting with SPI NOR flash, > make use of all the four registers so that 16 bytes can be transferred > in one go. > > With this patch, the flash write speed increases from ~250KBs/ to > ~650KB/s on DRA74 EVM. > > Signed-off-by: Vignesh R Reviewed-by: Tom Rini -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: