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From: Mark Rutland <mark.rutland@arm.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v3 01/10] arm: add atomic functions with return support
Date: Wed, 26 Oct 2016 16:14:31 +0100	[thread overview]
Message-ID: <20161026151354.GA22713@leverpostej> (raw)
In-Reply-To: <20161026121033.6339-2-antoine.tenart@free-electrons.com>

Hi,

On Wed, Oct 26, 2016 at 02:10:24PM +0200, Antoine Tenart wrote:
> Implement three atomic functions to allow making an atomic operation
> that returns the value. Adds: atomic_add_return(), atomic_sub_return(),
> atomic_inc_return() and atomic_dec_return().
> 
> Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>

In the cover letter, you mentioned that these are needed for SMP
systems (for managing common suspend entry/exit management).

The below operations are *not* atomic in SMP systems, and can only work
in UP. The same is true of all the existing code in the same file.

> +static inline int atomic_add_return(int i, volatile atomic_t *v)
> +{
> +	unsigned long flags = 0;
> +	int ret;
> +
> +	local_irq_save(flags);
> +	ret = (v->counter += i);
> +	local_irq_restore(flags);
> +
> +	return ret;
> +}

local_irq_{save,restore}() won't serialize two CPUs. Consider two CPUs
executing this in parallel (assuming the compiler chooses a register rX
as a temporary):

	CPU0				CPU1

	local_irq_save()		local_irq_save()
	rX = v->counter			rX = v->counter
	rX += i				rX += i
	v->counter = rX
					v->counter = rX
	local_irq_restore()		local_irq_restore()

At the end of this, CPU0's increment of v->counter is lost.

If you need atomics on SMP, you'll need to use the
{load,store}-exclusive instructions, which come with a number of
additional requirements (e.g. the memory being operated on must be
mapped as write-back cacheable, the entire retry loop needs to be
writtten in asm, etc).

Thanks,
Mark.

  reply	other threads:[~2016-10-26 15:14 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-10-26 12:10 [U-Boot] [PATCH v3 00/10] sunxi: sun5/7i: add the psci suspend function Antoine Tenart
2016-10-26 12:10 ` [U-Boot] [PATCH v3 01/10] arm: add atomic functions with return support Antoine Tenart
2016-10-26 15:14   ` Mark Rutland [this message]
2016-10-27 13:28     ` Antoine Tenart
2016-10-26 12:10 ` [U-Boot] [PATCH v3 02/10] ARM: add the ARM_GIC configuration option Antoine Tenart
2016-10-26 12:10 ` [U-Boot] [PATCH v3 03/10] sunxi: select ARM_GIC for sun[6789]i Antoine Tenart
2016-10-26 12:10 ` [U-Boot] [PATCH v3 04/10] ARM: select ARM_GIC for SoCs having a psci implementation Antoine Tenart
2016-10-26 12:10 ` [U-Boot] [PATCH v3 05/10] exynos: select ARM_GIC for TARGET_ARNDALE Antoine Tenart
2016-10-26 12:10 ` [U-Boot] [PATCH v3 06/10] tegra: select ARM_GIC for Tegra TK1s Antoine Tenart
2016-10-26 14:55   ` Stephen Warren
2016-10-26 14:59     ` Antoine Tenart
2016-10-26 15:01       ` Stephen Warren
2016-10-27 13:13         ` Antoine Tenart
2016-10-26 12:10 ` [U-Boot] [PATCH v3 07/10] ARM: PSCI: protect GIC specific code with ARM_GIC Antoine Tenart
2016-10-26 12:10 ` [U-Boot] [PATCH v3 08/10] sun5/7i: add an implementation of the psci suspend function Antoine Tenart
2016-10-26 12:38   ` Maxime Ripard
2016-10-27 13:10     ` Antoine Tenart
2016-10-27 13:20       ` Maxime Ripard
2016-10-27 13:32         ` Antoine Tenart
2016-10-27 13:21       ` Chen-Yu Tsai
2016-10-27 13:41         ` Antoine Tenart
2016-10-27 13:56           ` Chen-Yu Tsai
2016-10-26 12:10 ` [U-Boot] [PATCH v3 09/10] sun5i: add defines used by the PSCI code Antoine Tenart
2016-10-26 12:34   ` Maxime Ripard
2016-10-27 13:04     ` Antoine Tenart
2016-10-26 12:10 ` [U-Boot] [PATCH v3 10/10] sun5i: boot in non-secure mode by default Antoine Tenart

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