* [U-Boot] [PATCH RESEND v2 1/2] ARM: dts: dra7xx: Update spi-max-frequency for qspi slave node @ 2016-10-31 4:10 Vignesh R 2016-10-31 4:10 ` [U-Boot] [PATCH RESEND v2 2/2] spi: ti_qspi: Fix baudrate divider calculation Vignesh R 2016-10-31 11:54 ` [U-Boot] [PATCH RESEND v2 1/2] ARM: dts: dra7xx: Update spi-max-frequency for qspi slave node Tom Rini 0 siblings, 2 replies; 7+ messages in thread From: Vignesh R @ 2016-10-31 4:10 UTC (permalink / raw) To: u-boot Update the spi-max-frequency property of m25p80 flash slave to match that of TI QSPI controller node, so that QSPI operations happen at maximum supported frequency of 76.8MHz. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com> --- v2: No changes arch/arm/dts/dra7-evm.dts | 2 +- arch/arm/dts/dra72-evm-common.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/dra7-evm.dts b/arch/arm/dts/dra7-evm.dts index fe755c05841d..be36d456206d 100644 --- a/arch/arm/dts/dra7-evm.dts +++ b/arch/arm/dts/dra7-evm.dts @@ -505,7 +505,7 @@ spi-max-frequency = <76800000>; m25p80 at 0 { compatible = "s25fl256s1","spi-flash"; - spi-max-frequency = <64000000>; + spi-max-frequency = <76800000>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; diff --git a/arch/arm/dts/dra72-evm-common.dtsi b/arch/arm/dts/dra72-evm-common.dtsi index b0993e5bf7e0..1e1ca725577f 100644 --- a/arch/arm/dts/dra72-evm-common.dtsi +++ b/arch/arm/dts/dra72-evm-common.dtsi @@ -441,7 +441,7 @@ spi-max-frequency = <76800000>; m25p80 at 0 { compatible = "s25fl256s1", "spi-flash"; - spi-max-frequency = <64000000>; + spi-max-frequency = <76800000>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; -- 2.10.2 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH RESEND v2 2/2] spi: ti_qspi: Fix baudrate divider calculation 2016-10-31 4:10 [U-Boot] [PATCH RESEND v2 1/2] ARM: dts: dra7xx: Update spi-max-frequency for qspi slave node Vignesh R @ 2016-10-31 4:10 ` Vignesh R 2016-10-31 9:24 ` Jagan Teki 2016-10-31 11:54 ` [U-Boot] [PATCH RESEND v2 1/2] ARM: dts: dra7xx: Update spi-max-frequency for qspi slave node Tom Rini 1 sibling, 1 reply; 7+ messages in thread From: Vignesh R @ 2016-10-31 4:10 UTC (permalink / raw) To: u-boot Fix the divider calculation logic to choose a value so that the resulting baudrate is either equal to or closest possible baudrate less than the requested value. While at that, cleanup ti_spi_set_speed(). Signed-off-by: Vignesh R <vigneshr@ti.com> --- v2: cleanup ti_spi_set_speed() a bit. drivers/spi/ti_qspi.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index 52520dff6325..b5de70bf40e3 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -16,6 +16,7 @@ #include <asm/omap_gpio.h> #include <asm/omap_common.h> #include <asm/ti-common/ti-edma3.h> +#include <linux/kernel.h> DECLARE_GLOBAL_DATA_PTR; @@ -118,21 +119,19 @@ static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz) if (!hz) clk_div = 0; else - clk_div = (priv->fclk / hz) - 1; - - debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div); + clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1; /* disable SCLK */ writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN, &priv->base->clk_ctrl); - /* assign clk_div values */ - if (clk_div < 0) - clk_div = 0; - else if (clk_div > QSPI_CLK_DIV_MAX) + /* truncate clk_div value to QSPI_CLK_DIV_MAX */ + if (clk_div > QSPI_CLK_DIV_MAX) clk_div = QSPI_CLK_DIV_MAX; - /* enable SCLK */ + debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div); + + /* enable SCLK and program the clk divider */ writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl); } -- 2.10.2 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH RESEND v2 2/2] spi: ti_qspi: Fix baudrate divider calculation 2016-10-31 4:10 ` [U-Boot] [PATCH RESEND v2 2/2] spi: ti_qspi: Fix baudrate divider calculation Vignesh R @ 2016-10-31 9:24 ` Jagan Teki 2016-11-04 11:01 ` Jagan Teki 0 siblings, 1 reply; 7+ messages in thread From: Jagan Teki @ 2016-10-31 9:24 UTC (permalink / raw) To: u-boot On Mon, Oct 31, 2016 at 9:40 AM, Vignesh R <vigneshr@ti.com> wrote: > Fix the divider calculation logic to choose a value so that the > resulting baudrate is either equal to or closest possible baudrate less > than the requested value. While at that, cleanup ti_spi_set_speed(). > > Signed-off-by: Vignesh R <vigneshr@ti.com> > --- > > v2: cleanup ti_spi_set_speed() a bit. > > drivers/spi/ti_qspi.c | 15 +++++++-------- > 1 file changed, 7 insertions(+), 8 deletions(-) > > diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c > index 52520dff6325..b5de70bf40e3 100644 > --- a/drivers/spi/ti_qspi.c > +++ b/drivers/spi/ti_qspi.c > @@ -16,6 +16,7 @@ > #include <asm/omap_gpio.h> > #include <asm/omap_common.h> > #include <asm/ti-common/ti-edma3.h> > +#include <linux/kernel.h> > > DECLARE_GLOBAL_DATA_PTR; > > @@ -118,21 +119,19 @@ static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz) > if (!hz) > clk_div = 0; > else > - clk_div = (priv->fclk / hz) - 1; > - > - debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div); > + clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1; > > /* disable SCLK */ > writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN, > &priv->base->clk_ctrl); Move this before enable SCLK. > > - /* assign clk_div values */ > - if (clk_div < 0) > - clk_div = 0; > - else if (clk_div > QSPI_CLK_DIV_MAX) > + /* truncate clk_div value to QSPI_CLK_DIV_MAX */ > + if (clk_div > QSPI_CLK_DIV_MAX) > clk_div = QSPI_CLK_DIV_MAX; > > - /* enable SCLK */ > + debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div); > + > + /* enable SCLK and program the clk divider */ > writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl); > } thanks! -- Jagan Teki Free Software Engineer | www.openedev.com U-Boot, Linux | Upstream Maintainer Hyderabad, India. ^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH RESEND v2 2/2] spi: ti_qspi: Fix baudrate divider calculation 2016-10-31 9:24 ` Jagan Teki @ 2016-11-04 11:01 ` Jagan Teki 2016-11-05 10:36 ` R, Vignesh 0 siblings, 1 reply; 7+ messages in thread From: Jagan Teki @ 2016-11-04 11:01 UTC (permalink / raw) To: u-boot On Mon, Oct 31, 2016 at 2:54 PM, Jagan Teki <jagan@openedev.com> wrote: > On Mon, Oct 31, 2016 at 9:40 AM, Vignesh R <vigneshr@ti.com> wrote: >> Fix the divider calculation logic to choose a value so that the >> resulting baudrate is either equal to or closest possible baudrate less >> than the requested value. While at that, cleanup ti_spi_set_speed(). >> >> Signed-off-by: Vignesh R <vigneshr@ti.com> >> --- >> >> v2: cleanup ti_spi_set_speed() a bit. >> >> drivers/spi/ti_qspi.c | 15 +++++++-------- >> 1 file changed, 7 insertions(+), 8 deletions(-) >> >> diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c >> index 52520dff6325..b5de70bf40e3 100644 >> --- a/drivers/spi/ti_qspi.c >> +++ b/drivers/spi/ti_qspi.c >> @@ -16,6 +16,7 @@ >> #include <asm/omap_gpio.h> >> #include <asm/omap_common.h> >> #include <asm/ti-common/ti-edma3.h> >> +#include <linux/kernel.h> >> >> DECLARE_GLOBAL_DATA_PTR; >> >> @@ -118,21 +119,19 @@ static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz) >> if (!hz) >> clk_div = 0; >> else >> - clk_div = (priv->fclk / hz) - 1; >> - >> - debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div); >> + clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1; >> >> /* disable SCLK */ >> writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN, >> &priv->base->clk_ctrl); > > Move this before enable SCLK. Do send the updated v3 or discusses further, I need to send the release PR? thanks! -- Jagan Teki Free Software Engineer | www.openedev.com U-Boot, Linux | Upstream Maintainer Hyderabad, India. ^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH RESEND v2 2/2] spi: ti_qspi: Fix baudrate divider calculation 2016-11-04 11:01 ` Jagan Teki @ 2016-11-05 10:36 ` R, Vignesh 0 siblings, 0 replies; 7+ messages in thread From: R, Vignesh @ 2016-11-05 10:36 UTC (permalink / raw) To: u-boot [...] On 11/4/2016 4:31 PM, Jagan Teki wrote: >>> >> diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c >>> >> index 52520dff6325..b5de70bf40e3 100644 >>> >> --- a/drivers/spi/ti_qspi.c >>> >> +++ b/drivers/spi/ti_qspi.c >>> >> @@ -16,6 +16,7 @@ >>> >> #include <asm/omap_gpio.h> >>> >> #include <asm/omap_common.h> >>> >> #include <asm/ti-common/ti-edma3.h> >>> >> +#include <linux/kernel.h> >>> >> >>> >> DECLARE_GLOBAL_DATA_PTR; >>> >> >>> >> @@ -118,21 +119,19 @@ static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz) >>> >> if (!hz) >>> >> clk_div = 0; >>> >> else >>> >> - clk_div = (priv->fclk / hz) - 1; >>> >> - >>> >> - debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div); >>> >> + clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1; >>> >> >>> >> /* disable SCLK */ >>> >> writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN, >>> >> &priv->base->clk_ctrl); >> > >> > Move this before enable SCLK. Ok... > Do send the updated v3 or discusses further, I need to send the release PR? Sorry for the delay.. Posted v3 with above change. -- Regards Vignesh ^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH RESEND v2 1/2] ARM: dts: dra7xx: Update spi-max-frequency for qspi slave node 2016-10-31 4:10 [U-Boot] [PATCH RESEND v2 1/2] ARM: dts: dra7xx: Update spi-max-frequency for qspi slave node Vignesh R 2016-10-31 4:10 ` [U-Boot] [PATCH RESEND v2 2/2] spi: ti_qspi: Fix baudrate divider calculation Vignesh R @ 2016-10-31 11:54 ` Tom Rini 2016-10-31 15:40 ` R, Vignesh 1 sibling, 1 reply; 7+ messages in thread From: Tom Rini @ 2016-10-31 11:54 UTC (permalink / raw) To: u-boot On Mon, Oct 31, 2016 at 09:40:34AM +0530, Vignesh R wrote: > Update the spi-max-frequency property of m25p80 flash slave to match > that of TI QSPI controller node, so that QSPI operations happen at > maximum supported frequency of 76.8MHz. > > Signed-off-by: Vignesh R <vigneshr@ti.com> > Reviewed-by: Jagan Teki <jteki@openedev.com> And this is also done in the kernel right? Thanks! -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: <http://lists.denx.de/pipermail/u-boot/attachments/20161031/112aa489/attachment.sig> ^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] [PATCH RESEND v2 1/2] ARM: dts: dra7xx: Update spi-max-frequency for qspi slave node 2016-10-31 11:54 ` [U-Boot] [PATCH RESEND v2 1/2] ARM: dts: dra7xx: Update spi-max-frequency for qspi slave node Tom Rini @ 2016-10-31 15:40 ` R, Vignesh 0 siblings, 0 replies; 7+ messages in thread From: R, Vignesh @ 2016-10-31 15:40 UTC (permalink / raw) To: u-boot On 10/31/2016 5:24 PM, Tom Rini wrote: > On Mon, Oct 31, 2016 at 09:40:34AM +0530, Vignesh R wrote: > >> Update the spi-max-frequency property of m25p80 flash slave to match >> that of TI QSPI controller node, so that QSPI operations happen at >> maximum supported frequency of 76.8MHz. >> >> Signed-off-by: Vignesh R <vigneshr@ti.com> >> Reviewed-by: Jagan Teki <jteki@openedev.com> > > And this is also done in the kernel right? Thanks! > Yes, the kernel patch is merged. -- Regards Vignesh ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2016-11-05 10:36 UTC | newest] Thread overview: 7+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2016-10-31 4:10 [U-Boot] [PATCH RESEND v2 1/2] ARM: dts: dra7xx: Update spi-max-frequency for qspi slave node Vignesh R 2016-10-31 4:10 ` [U-Boot] [PATCH RESEND v2 2/2] spi: ti_qspi: Fix baudrate divider calculation Vignesh R 2016-10-31 9:24 ` Jagan Teki 2016-11-04 11:01 ` Jagan Teki 2016-11-05 10:36 ` R, Vignesh 2016-10-31 11:54 ` [U-Boot] [PATCH RESEND v2 1/2] ARM: dts: dra7xx: Update spi-max-frequency for qspi slave node Tom Rini 2016-10-31 15:40 ` R, Vignesh
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