From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tom Rini Date: Fri, 4 Nov 2016 07:25:50 -0400 Subject: [U-Boot] [PATCH] ARM: k2g: Update PLL Multiplier and divider values In-Reply-To: <20161103100502.1896-1-lokeshvutla@ti.com> References: <20161103100502.1896-1-lokeshvutla@ti.com> Message-ID: <20161104112550.GV23095@bill-the-cat> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Thu, Nov 03, 2016 at 03:35:02PM +0530, Lokesh Vutla wrote: > Only a certain set of PLLM/D values are recommended to configure the DDR > at the required speeds for a given clock input frequency. Updating these > values as specified in Data Sheet[1] Table 5-18 > > [1] http://www.ti.com/lit/ds/symlink/66ak2g02.pdf > > Signed-off-by: Lokesh Vutla Reviewed-by: Tom Rini -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: