From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tom Rini Date: Sun, 13 Nov 2016 15:56:46 -0500 Subject: [U-Boot] [U-Boot, v2, 2/2] arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode In-Reply-To: <1477734550-17989-2-git-send-email-j-keerthy@ti.com> References: <1477734550-17989-2-git-send-email-j-keerthy@ti.com> Message-ID: <20161113205646.GQ27304@bill-the-cat> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Sat, Oct 29, 2016 at 03:19:10PM +0530, Keerthy wrote: > While we setup the mmu initially we mark set_section_dcache with > DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro > is rightly defined with TTB_SECT_XN_MASK set so as to mark all the > 4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with > DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which > keeps all the regions execute okay and this leads to random speculative > fetches in random memory regions which was eventually caught by kernel > omap-l3-noc driver. > > Fix this to mark the regions as XN by default. > > Signed-off-by: Keerthy > Reviewed-by: Alexander Graf > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: