[U-Boot] [RFC PATCH 7/7] fpga/spartan3: add reverse bitstream mode

[Chris Packham <judge.packham@gmail.com>]

The Xilinx tools we use appear to give us a bitstream with the bits
reversed (compared to what the existing code expects) add a new
CONFIG_FPGA_REVERSE_BITSTREAM option which tells the spartan3 driver
to output the serial stream with the leftmost bit first.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
---

 drivers/fpga/Kconfig    | 7 +++++++
 drivers/fpga/spartan3.c | 8 ++++++++
 2 files changed, 15 insertions(+)

diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 1b3b03c8f938..26b7c864d275 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -29,6 +29,13 @@ config FPGA_SPARTAN2
 	help
 	  Enable FPGA driver for Xilinx Spartan-II devices.
 
+config FPGA_REVERSE_BITSTREAM
+	bool "Reverse bitstream when programming"
+	depends on FPGA_SPARTAN3
+	help
+	  Some Xilinx tools generate programs that need to be uploaded LSb
+	  first. Set this option if your fpga binary requires this.
+
 config FPGA_PROG_FEEDBACK
 	bool "FPGA programming feedback"
 	help
diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c
index 34aa097ab6c2..2a57c8ab77b5 100644
--- a/drivers/fpga/spartan3.c
+++ b/drivers/fpga/spartan3.c
@@ -392,12 +392,20 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
 					(*fn->clk) (false, true, cookie);
 					CONFIG_FPGA_DELAY ();
 					/* Write data */
+#ifdef CONFIG_FPGA_REVERSE_BITSTREAM
+					(*fn->wr) ((val & 0x01), true, cookie);
+#else
 					(*fn->wr) ((val & 0x80), true, cookie);
+#endif
 					CONFIG_FPGA_DELAY ();
 					/* Assert the clock */
 					(*fn->clk) (true, true, cookie);
 					CONFIG_FPGA_DELAY ();
+#ifdef CONFIG_FPGA_REVERSE_BITSTREAM
+					val >>= 1;
+#else
 					val <<= 1;
+#endif
 					i --;
 				} while (i > 0);
 
-- 
2.10.2