From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tom Rini Date: Mon, 28 Nov 2016 11:40:14 -0500 Subject: [U-Boot] [RFC PATCH 0/3] spl: Add D-cache support In-Reply-To: <20161128093445.15300-1-lokeshvutla@ti.com> References: <20161128093445.15300-1-lokeshvutla@ti.com> Message-ID: <20161128164014.GF2546@bill-the-cat> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Mon, Nov 28, 2016 at 03:04:42PM +0530, Lokesh Vutla wrote: > This series tries to add D-cache support in spl in order to reduce boot time > either in 2stage boot or Falcon Boot. I assume you've measured and confirmed that there is a speed increase? I ask since I'd tried this ages ago but.. > > Lokesh Vutla (3): > arch: arm: omap: Declare size of ddr very early > spl: reorder the assignment of board info to global data ... I didn't have changes like this, which is perhaps why it ended up not working right. Thanks! -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: