From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tom Rini Date: Thu, 1 Dec 2016 15:30:26 -0500 Subject: [U-Boot] [PATCH] davinci: omapl138_lcdk: increase PLL0 frequency In-Reply-To: <1480590463-31252-1-git-send-email-bgolaszewski@baylibre.com> References: <1480590463-31252-1-git-send-email-bgolaszewski@baylibre.com> Message-ID: <20161201203026.GF2546@bill-the-cat> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Thu, Dec 01, 2016 at 12:07:43PM +0100, Bartosz Golaszewski wrote: > The LCDC controller on the lcdk board has high memory throughput > requirements. Even with the kernel-side tweaks to master peripheral > and peripheral bus burst priorities, the default PLL0 frquency of > 300 MHz is not enough to service the LCD controller and causes > DMA FIFO underflows. > > Increment the PLL0 multiplier to 37, resulting in PLL0 frequency of > 456 MHz - the same value that downstream reference u-boot from Texas > Instruments uses. > > Signed-off-by: Bartosz Golaszewski Reviewed-by: Tom Rini -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: