From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tom Rini Date: Sun, 4 Dec 2016 18:19:17 -0500 Subject: [U-Boot] [U-Boot, v2, 3/3] ARM: DRA7: Fixup DSPEVE, IVA and GPU clock frequencies based on OPP In-Reply-To: <20161123072441.32630-4-lokeshvutla@ti.com> References: <20161123072441.32630-4-lokeshvutla@ti.com> Message-ID: <20161204231917.GD4248@bill-the-cat> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Wed, Nov 23, 2016 at 12:54:41PM +0530, Lokesh Vutla wrote: > From: Suman Anna > > This patch adds support to update the device-tree blob to adjust the > DSP and IVA DPLL clocks pertinent to the selected OPP choice, with > the default being OPP_NOM. The voltage settings are done in u-boot, > but the actual clock configuration itself is done in kernel because > of the following reasons: > 1. SoC definition constraints us to NOT to do dynamic voltage > scaling ever after the initial avs0 setting in bootloader > - so the voltage must be set in bootloader. > 2. The voltage level must be set even if the IP blocks like > GPU/DSP are unused. > 3. The IVA, GPU and DSP DPLLs are not essential for u-boot functionality, > and similar DPLL clock configuration code has been cleaned up in > v2014.10 u-boot release. See commit, 02c41535b6a4 ("ARM: OMAP4/5: > Remove dead code against CONFIG_SYS_CLOCKS_ENABLE_ALL"). > > The non-essential DPLLs are configured within the kernel during > the clock init step when parsing the device tree and creating > the clock devices. This approach meets both the u-boot and kernel > needs. > > Signed-off-by: Suman Anna > Signed-off-by: Subhajit Paul > Signed-off-by: Lokesh Vutla > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: