From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime Ripard Date: Mon, 19 Dec 2016 10:57:39 +0100 Subject: [U-Boot] [PATCH v3 16/26] sunxi: H3: add DRAM controller single bit delay support In-Reply-To: <1482112216-12983-17-git-send-email-andre.przywara@arm.com> References: <1482112216-12983-1-git-send-email-andre.przywara@arm.com> <1482112216-12983-17-git-send-email-andre.przywara@arm.com> Message-ID: <20161219095739.flo5qlfoecthu5db@lukather> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Mon, Dec 19, 2016 at 01:50:06AM +0000, Andre Przywara wrote: > From: Jens Kuske > > So far the DRAM driver for the H3 SoC (and apparently boot0/libdram as > well) only applied coarse delay line settings, with one delay value for > all the data lines in each byte lane and one value for the control lines. > > Instead of setting the delays for whole bytes only allow setting it for > each individual bit. Also add support for address/command lane delays. > > For the purpose of this patch the rules for the existing coarse settings > were just applied to the new scheme, so the actual register writes don't > change for the H3. Other SoCs will utilize this feature later properly. > > With a stock GCC 5.3.0 this increases the dram_sun8i_h3.o code size from > 2296 to 2344 Bytes. > > [Andre: move delay parameters into macros to ease later sharing, use > defines for numbers of delay registers, extend commit message] > > Signed-off-by: Jens Kuske > Signed-off-by: Andre Przywara I said it earlier, but some comments on these new fields would really be welcome to document the structure and what values they're supposed to hold. -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 801 bytes Desc: not available URL: