From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime Ripard Date: Mon, 19 Dec 2016 11:03:42 +0100 Subject: [U-Boot] [PATCH v3 25/26] sunxi: introduce RMR switch to enter payloads in 64-bit mode In-Reply-To: <1482112216-12983-26-git-send-email-andre.przywara@arm.com> References: <1482112216-12983-1-git-send-email-andre.przywara@arm.com> <1482112216-12983-26-git-send-email-andre.przywara@arm.com> Message-ID: <20161219100342.6nxgo47kbgltlazs@lukather> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Mon, Dec 19, 2016 at 01:50:15AM +0000, Andre Przywara wrote: > The ARMv8 capable Allwinner A64 SoC comes out of reset in AArch32 mode. > To run AArch64 code, we have to trigger a warm reset via the RMR register, > which proceeds with code execution at the address stored in the RVBAR > register. > If the bootable payload in the FIT image is using a different > architecture than the SPL has been compiled for, enter it via this said > RMR switch mechanism, by writing the entry point address into the MMIO > mapped, writable version of the RVBAR register. > Then the warm reset is triggered via a system register write. > If the payload architecture is the same as the SPL, we use the normal > branch as usual. > > Signed-off-by: Andre Przywara Acked-by: Maxime Ripard Thanks, Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 801 bytes Desc: not available URL: