[U-Boot] [PATCH 18/24] ddr: fsl: Move macro CONFIG_NUM_DDR_CONTROLLERS to Kconfig

York Sun
2016-12-28T16:43:44Z

Use option NUM_DDR_CONTROLLERS in ddr Kconfig and clean up existing
usage in ls102xa and fsl-layerscape. Remove all powerpc macros in
config header and board header files.

Signed-off-by: York Sun <york.sun@nxp.com>
---

arch/arm/cpu/armv7/ls102xa/Kconfig | 4 ----
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 5 -----
arch/powerpc/include/asm/config_mpc85xx.h | 17 -----------------
drivers/ddr/fsl/Kconfig | 14 ++++++++++++++
include/configs/B4860QDS.h | 1 -
include/configs/BSC9131RDB.h | 1 -
include/configs/MPC8349EMDS.h | 1 -
include/configs/MPC8536DS.h | 1 -
include/configs/MPC8540ADS.h | 1 -
include/configs/MPC8541CDS.h | 1 -
include/configs/MPC8544DS.h | 1 -
include/configs/MPC8548CDS.h | 1 -
include/configs/MPC8555CDS.h | 1 -
include/configs/MPC8560ADS.h | 1 -
include/configs/MPC8568MDS.h | 1 -
include/configs/MPC8569MDS.h | 1 -
include/configs/MPC8572DS.h | 1 -
include/configs/MPC8610HPCD.h | 1 -
include/configs/MPC8641HPCN.h | 1 -
include/configs/P1022DS.h | 1 -
include/configs/T1040QDS.h | 1 -
include/configs/T104xRDB.h | 1 -
include/configs/T4240RDB.h | 1 -
include/configs/UCP1020.h | 1 -
include/configs/controlcenterd.h | 1 -
include/configs/p1_p2_rdb_pc.h | 1 -
include/configs/p1_twr.h | 1 -
include/configs/sbc8548.h | 1 -
include/configs/sbc8641d.h | 2 --
include/configs/socrates.h | 1 -
include/configs/t4qds.h | 1 -
include/configs/xpedite517x.h | 1 -
include/configs/xpedite520x.h | 1 -
include/configs/xpedite537x.h | 1 -
include/configs/xpedite550x.h | 1 -
scripts/config_whitelist.txt | 1 -
36 files changed, 14 insertions(+), 59 deletions(-)

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
index 4b904f3..9ffb90e 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -33,10 +33,6 @@ config MAX_CPUS
cores, count the reserved ports. This will allocate enough memory
in spin table to properly handle all cores.

-config NUM_DDR_CONTROLLERS
- int "Maximum DDR controllers"
- default 1
-
config SECURE_BOOT
bool "Secure Boot"
help
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index af84e40..de0b580 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -115,11 +115,6 @@ config MAX_CPUS
cores, count the reserved ports. This will allocate enough memory
in spin table to properly handle all cores.

-config NUM_DDR_CONTROLLERS
- int "Maximum DDR controllers"
- default 3 if ARCH_LS2080A
- default 1
-
config SECURE_BOOT
bool
help
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 0eaa944..dbc8d7a 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -66,7 +66,6 @@
#elif defined(CONFIG_ARCH_P1010)
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_TSECV2
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
@@ -102,7 +101,6 @@
#elif defined(CONFIG_ARCH_P1023)
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 2
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_QMAN_NUM_PORTALS 3
#define CONFIG_SYS_BMAN_NUM_PORTALS 3
@@ -139,7 +137,6 @@
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 32
@@ -159,7 +156,6 @@
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 32
@@ -182,7 +178,6 @@
#define CONFIG_SYS_NUM_FM2_DTSEC 4
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_NUM_FM2_10GEC 1
-#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
@@ -203,7 +198,6 @@
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
-#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
@@ -227,7 +221,6 @@
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_NUM_FM2_DTSEC 5
#define CONFIG_SYS_NUM_FM2_10GEC 1
-#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
@@ -241,7 +234,6 @@
#elif defined(CONFIG_ARCH_BSC9131)
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_TSECV2
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
@@ -253,7 +245,6 @@
#elif defined(CONFIG_ARCH_BSC9132)
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_TSECV2
-#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
@@ -279,13 +270,11 @@
#define CONFIG_SYS_NUM_FM1_10GEC 2
#define CONFIG_SYS_NUM_FM2_DTSEC 8
#define CONFIG_SYS_NUM_FM2_10GEC 2
-#define CONFIG_NUM_DDR_CONTROLLERS 3
#else
#define CONFIG_SYS_NUM_FM1_DTSEC 6
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_NUM_FM2_DTSEC 8
#define CONFIG_SYS_NUM_FM2_10GEC 1
-#define CONFIG_NUM_DDR_CONTROLLERS 2
#if defined(CONFIG_ARCH_T4160)
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
#endif
@@ -352,7 +341,6 @@
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
#define CONFIG_SYS_NUM_FM1_DTSEC 6
#define CONFIG_SYS_NUM_FM1_10GEC 2
-#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
@@ -365,7 +353,6 @@
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
#define CONFIG_SYS_NUM_FM1_DTSEC 4
#define CONFIG_SYS_NUM_FM1_10GEC 0
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#endif

#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
@@ -379,7 +366,6 @@
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_PME_PLAT_CLK_DIV 2
#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
@@ -417,7 +403,6 @@
#define CONFIG_SYS_NUM_FM1_DTSEC 4
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
@@ -462,7 +447,6 @@
#define CONFIG_SYS_NUM_FM1_10GEC 2
#endif
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_PME_PLAT_CLK_DIV 1
#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
#define CONFIG_SYS_FM1_CLK 0
@@ -486,7 +470,6 @@
#elif defined(CONFIG_ARCH_C29X)
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_TSECV2_1
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3
diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig
index 7b7e4f2..b035502 100644
--- a/drivers/ddr/fsl/Kconfig
+++ b/drivers/ddr/fsl/Kconfig
@@ -23,6 +23,20 @@ config SYS_FSL_DDR_LE
menu "Freescale DDR controllers"
depends on SYS_FSL_DDR

+config NUM_DDR_CONTROLLERS
+ int "Maximum DDR controllers"
+ default 3 if ARCH_LS2080A || \
+ ARCH_T4240
+ default 2 if ARCH_B4860 || \
+ ARCH_BSC9132 || \
+ ARCH_MPC8572 || \
+ ARCH_MPC8641 || \
+ ARCH_P4080 || \
+ ARCH_P5020 || \
+ ARCH_P5040 || \
+ ARCH_T4160
+ default 1
+
config SYS_FSL_DDR_VER
int
default 50 if SYS_FSL_DDR_VER_50
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index 101a398..e5c220e 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -222,7 +222,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE

-/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)

diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h
index 7864936..a6f73f2 100644
--- a/include/configs/BSC9131RDB.h
+++ b/include/configs/BSC9131RDB.h
@@ -84,7 +84,6 @@ extern unsigned long get_sdram_size(void);
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE

-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 1

diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index d289bf4..3d3eeb5 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -66,7 +66,6 @@
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS1 0x52
#define SPD_EEPROM_ADDRESS2 0x51
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 8075085..a64f0de 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -105,7 +105,6 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE

-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 2

diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index c0d74fa..3389a77 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -77,7 +77,6 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE

-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)

diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index f2618a0..00a18b5 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -52,7 +52,6 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE

-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)

diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index 406ac5a..b9c62e1 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -63,7 +63,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_VERY_BIG_RAM

-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 2

diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 84292b4..c241b51 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -73,7 +73,6 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE

-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)

diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index 7058b85..6faa230 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -52,7 +52,6 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE

-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)

diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index 218d77d..e0d010a 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -76,7 +76,6 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE

-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)

diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index 3573ef4..0d3707f 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -60,7 +60,6 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE

-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)

diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index 1b61197..ce389ad 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -88,7 +88,6 @@ extern unsigned long get_clock_freq(void);
/* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE

-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)

diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index c91e032..5ca01e8 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -93,7 +93,6 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE

-#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 2

diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 48eada5..c5f3634 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -91,7 +91,6 @@
#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
#define CONFIG_VERY_BIG_RAM

-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)

diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index d413f21..fb66bb6 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -113,7 +113,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
#define CONFIG_VERY_BIG_RAM

-#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)

diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index 949bdef..7a83c56 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -145,7 +145,6 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE

-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)

diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index 00539ee..8393619 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -163,7 +163,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE

-/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)

diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 8debccb..4ee17f9 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -268,7 +268,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE

-/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)

diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index c3c187f..f68ab2e 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -127,7 +127,6 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE

-/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h
index 3fc326b..8233978 100644
--- a/include/configs/UCP1020.h
+++ b/include/configs/UCP1020.h
@@ -191,7 +191,6 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE

-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1

/* Default settings for DDR3 */
diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h
index 988b96d..d2172e9 100644
--- a/include/configs/controlcenterd.h
+++ b/include/configs/controlcenterd.h
@@ -122,7 +122,6 @@
#define CONFIG_SYS_SDRAM_SIZE 1024
#define CONFIG_VERY_BIG_RAM

-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)

diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index a167bae..13effde 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -331,7 +331,6 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE

-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1

/* Default settings for DDR3 */
diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h
index 94556a7..2d61c19 100644
--- a/include/configs/p1_twr.h
+++ b/include/configs/p1_twr.h
@@ -89,7 +89,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE

-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1

/* Default settings for DDR3 */
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index 7c5961a..281a993 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -116,7 +116,6 @@
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_VERY_BIG_RAM

-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 2

diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index 87056db..f02634b 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -57,7 +57,6 @@
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CACHE_LINE_INTERLEAVING 0x20000000
#define PAGE_INTERLEAVING 0x21000000
#define BANK_INTERLEAVING 0x22000000
@@ -103,7 +102,6 @@
#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
#define CONFIG_VERY_BIG_RAM

-#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)

diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index 806fc27..6480116 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -79,7 +79,6 @@
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_VERY_BIG_RAM

-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 2

diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
index 4fd6f4d..e82df33 100644
--- a/include/configs/t4qds.h
+++ b/include/configs/t4qds.h
@@ -83,7 +83,6 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE

-/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h
index 49c485e..0d5b1ff 100644
--- a/include/configs/xpedite517x.h
+++ b/include/configs/xpedite517x.h
@@ -41,7 +41,6 @@
#define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
#define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
-#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
#define CONFIG_DDR_ECC
diff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h
index cc8b794..b88aeb4 100644
--- a/include/configs/xpedite520x.h
+++ b/include/configs/xpedite520x.h
@@ -37,7 +37,6 @@
#define CONFIG_DDR_SPD
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define SPD_EEPROM_ADDRESS 0x54
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
#define CONFIG_DDR_ECC
diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h
index f37cf88..5d78560 100644
--- a/include/configs/xpedite537x.h
+++ b/include/configs/xpedite537x.h
@@ -48,7 +48,6 @@
#define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
#define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
-#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
#define CONFIG_DDR_ECC
diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h
index 6203142..35e6350 100644
--- a/include/configs/xpedite550x.h
+++ b/include/configs/xpedite550x.h
@@ -47,7 +47,6 @@
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define SPD_EEPROM_ADDRESS 0x54
#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
#define CONFIG_DDR_ECC
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 2d5d30d..37d692e 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -3320,7 +3320,6 @@ CONFIG_NR_DRAM_POPULATED
CONFIG_NS16550_MIN_FUNCTIONS
CONFIG_NS8382X
CONFIG_NS87308
-CONFIG_NUM_DDR_CONTROLLERS
CONFIG_NUM_DSP_CPUS
CONFIG_NUM_PAMU
CONFIG_OCLK_DIV
--
2.7.4