[U-Boot] [PATCH 16/24] mmc: move CONFIG_SYS_FSL_ERRATUM_ESDHC* to Kconfig

York Sun
2016-12-28T16:43:42Z

Add option SYS_FSL_ERRATUM_ESDHC111, SYS_FSL_ERRATUM_ESDHC13,
SYS_FSL_ERRATUM_ESDHC135, SYS_FSL_ERRATUM_ESDHC_A001 to mmc Kconfig.
Move existing macros to related Kconfig.

Signed-off-by: York Sun <york.sun@nxp.com>
---

arch/arm/Kconfig | 7 +++++++
arch/powerpc/cpu/mpc83xx/Kconfig | 3 +++
arch/powerpc/cpu/mpc85xx/Kconfig | 25 +++++++++++++++++++++++++
arch/powerpc/include/asm/config_mpc85xx.h | 22 ----------------------
drivers/mmc/Kconfig | 12 ++++++++++++
include/configs/MPC8308RDB.h | 1 -
include/configs/colibri_vf.h | 2 --
include/configs/hrcon.h | 1 -
include/configs/pcm052.h | 3 ---
include/configs/s32v234evb.h | 2 --
include/configs/strider.h | 1 -
include/configs/ts4800.h | 2 --
include/configs/vf610twr.h | 2 --
scripts/config_whitelist.txt | 4 ----
14 files changed, 47 insertions(+), 40 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index d6a0a23..6a312bd 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -546,6 +546,7 @@ config ARCH_RMOBILE
config TARGET_S32V234EVB
bool "Support s32v234evb"
select ARM64
+ select SYS_FSL_ERRATUM_ESDHC111

config ARCH_SNAPDRAGON
bool "Qualcomm Snapdragon SoCs"
@@ -602,18 +603,24 @@ config TARGET_TS4600
config TARGET_TS4800
bool "Support TS4800"
select CPU_V7
+ select SYS_FSL_ERRATUM_ESDHC_A001

config TARGET_VF610TWR
bool "Support vf610twr"
select CPU_V7
+ select SYS_FSL_ERRATUM_ESDHC111

config TARGET_COLIBRI_VF
bool "Support Colibri VF50/61"
select CPU_V7
+ select SYS_FSL_ERRATUM_ESDHC111

config TARGET_PCM052
bool "Support pcm-052"
select CPU_V7
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_ERRATUM_ESDHC135
+ select SYS_FSL_ERRATUM_ESDHC_A001

config TARGET_BK4R1
bool "Support BK4r1"
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index 6e4a931..184063c 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -22,6 +22,7 @@ config TARGET_VME8349

config TARGET_MPC8308RDB
bool "Support MPC8308RDB"
+ select SYS_FSL_ERRATUM_ESDHC111

config TARGET_MPC8313ERDB
bool "Support MPC8313ERDB"
@@ -69,9 +70,11 @@ config TARGET_TQM834X

config TARGET_HRCON
bool "Support hrcon"
+ select SYS_FSL_ERRATUM_ESDHC111

config TARGET_STRIDER
bool "Support strider"
+ select SYS_FSL_ERRATUM_ESDHC111

endchoice

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 3e90c70..dc81a3b 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -344,6 +344,7 @@ config ARCH_B4860
config ARCH_BSC9131
bool
select FSL_LAW
+ select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -352,6 +353,7 @@ config ARCH_BSC9131
config ARCH_BSC9132
bool
select FSL_LAW
+ select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -361,6 +363,7 @@ config ARCH_BSC9132
config ARCH_C29X
bool
select FSL_LAW
+ select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -450,6 +453,7 @@ config ARCH_MPC8572
config ARCH_P1010
bool
select FSL_LAW
+ select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -459,6 +463,7 @@ config ARCH_P1010
config ARCH_P1011
bool
select FSL_LAW
+ select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -468,6 +473,7 @@ config ARCH_P1011
config ARCH_P1020
bool
select FSL_LAW
+ select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -477,6 +483,7 @@ config ARCH_P1020
config ARCH_P1021
bool
select FSL_LAW
+ select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -486,6 +493,7 @@ config ARCH_P1021
config ARCH_P1022
bool
select FSL_LAW
+ select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -503,6 +511,7 @@ config ARCH_P1023
config ARCH_P1024
bool
select FSL_LAW
+ select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -512,6 +521,7 @@ config ARCH_P1024
config ARCH_P1025
bool
select FSL_LAW
+ select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -521,6 +531,8 @@ config ARCH_P1025
config ARCH_P2020
bool
select FSL_LAW
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_ERRATUM_ESDHC_A001
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -531,6 +543,7 @@ config ARCH_P2041
bool
select E500MC
select FSL_LAW
+ select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -540,6 +553,7 @@ config ARCH_P3041
bool
select E500MC
select FSL_LAW
+ select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -549,6 +563,9 @@ config ARCH_P4080
bool
select E500MC
select FSL_LAW
+ select SYS_FSL_ERRATUM_ESDHC111
+ select SYS_FSL_ERRATUM_ESDHC13
+ select SYS_FSL_ERRATUM_ESDHC135
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -558,6 +575,7 @@ config ARCH_P5020
bool
select E500MC
select FSL_LAW
+ select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -567,6 +585,7 @@ config ARCH_P5040
bool
select E500MC
select FSL_LAW
+ select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -579,6 +598,7 @@ config ARCH_T1023
bool
select E500MC
select FSL_LAW
+ select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_DDR4
select SYS_FSL_HAS_SEC
@@ -589,6 +609,7 @@ config ARCH_T1024
bool
select E500MC
select FSL_LAW
+ select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_DDR4
select SYS_FSL_HAS_SEC
@@ -599,6 +620,7 @@ config ARCH_T1040
bool
select E500MC
select FSL_LAW
+ select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_DDR4
select SYS_FSL_HAS_SEC
@@ -609,6 +631,7 @@ config ARCH_T1042
bool
select E500MC
select FSL_LAW
+ select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_DDR4
select SYS_FSL_HAS_SEC
@@ -619,6 +642,7 @@ config ARCH_T2080
bool
select E500MC
select FSL_LAW
+ select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
@@ -628,6 +652,7 @@ config ARCH_T2081
bool
select E500MC
select FSL_LAW
+ select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_BE
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 6aee5bc..aa06e64 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -81,7 +81,6 @@
#elif defined(CONFIG_ARCH_P1010)
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_TSECV2
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
@@ -107,7 +106,6 @@
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125

@@ -115,7 +113,6 @@
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
@@ -126,7 +123,6 @@
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
@@ -138,7 +134,6 @@
#define CONFIG_TSECV2
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_FSL_SATA_ERRATUM_A001
#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
@@ -164,7 +159,6 @@
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125

@@ -174,7 +168,6 @@
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
@@ -182,8 +175,6 @@
#define CONFIG_SYS_FSL_ERRATUM_A005125

#elif defined(CONFIG_ARCH_P2020)
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
@@ -209,7 +200,6 @@
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
#define CONFIG_SYS_FSL_ERRATUM_USB14
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
@@ -244,7 +234,6 @@
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
#define CONFIG_SYS_FSL_ERRATUM_USB14
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
@@ -283,9 +272,6 @@
#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC13
#define CONFIG_SYS_P4080_ERRATUM_CPU22
#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
#define CONFIG_SYS_P4080_ERRATUM_SERDES8
@@ -328,7 +314,6 @@
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_USB14
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
@@ -362,7 +347,6 @@
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_USB14
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
@@ -383,7 +367,6 @@
#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
#define CONFIG_NAND_FSL_IFC
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_A005125
#define CONFIG_SYS_FSL_ERRATUM_A004477
#define CONFIG_ESDHC_HC_BLK_ADDR
@@ -400,7 +383,6 @@
#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
#define CONFIG_NAND_FSL_IFC
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_FSL_ERRATUM_A005125
@@ -560,7 +542,6 @@
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
@@ -598,7 +579,6 @@
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
@@ -651,7 +631,6 @@
#define CONFIG_SYS_FSL_ERRATUM_A007212
#define CONFIG_SYS_FSL_SFP_VER_3_0
#define CONFIG_SYS_FSL_ISBC_VER 2
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_A006593
#define CONFIG_SYS_FSL_ERRATUM_A007186
#define CONFIG_SYS_FSL_ERRATUM_A006379
@@ -663,7 +642,6 @@
#elif defined(CONFIG_ARCH_C29X)
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_TSECV2_1
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 5e84a41..abe6d17 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -111,3 +111,15 @@ config SANDBOX_MMC
MMC build errors with sandbox.

endmenu
+
+config SYS_FSL_ERRATUM_ESDHC111
+ bool
+
+config SYS_FSL_ERRATUM_ESDHC13
+ bool
+
+config SYS_FSL_ERRATUM_ESDHC135
+ bool
+
+config SYS_FSL_ERRATUM_ESDHC_A001
+ bool
diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h
index 6335c55..47b180b 100644
--- a/include/configs/MPC8308RDB.h
+++ b/include/configs/MPC8308RDB.h
@@ -26,7 +26,6 @@
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ESDHC_USE_PIO

#define CONFIG_GENERIC_MMC
diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index 47dea62..97db83e 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -61,8 +61,6 @@
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 1

-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-
#define CONFIG_GENERIC_MMC
#define CONFIG_DOS_PARTITION

diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h
index 9677aab..a1d9121 100644
--- a/include/configs/hrcon.h
+++ b/include/configs/hrcon.h
@@ -27,7 +27,6 @@
#define CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111

#define CONFIG_GENERIC_MMC
#define CONFIG_DOS_PARTITION
diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h
index e70c3f0..934deb0 100644
--- a/include/configs/pcm052.h
+++ b/include/configs/pcm052.h
@@ -71,9 +71,6 @@
#define CONFIG_SYS_FSL_ESDHC_NUM 1

/*#define CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1*/
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001

#define CONFIG_GENERIC_MMC
#define CONFIG_DOS_PARTITION
diff --git a/include/configs/s32v234evb.h b/include/configs/s32v234evb.h
index 9f85fdc..291af06 100644
--- a/include/configs/s32v234evb.h
+++ b/include/configs/s32v234evb.h
@@ -83,8 +83,6 @@
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC_BASE_ADDR
#define CONFIG_SYS_FSL_ESDHC_NUM 1

-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-
#define CONFIG_CMD_MMC
#define CONFIG_GENERIC_MMC
/* #define CONFIG_CMD_EXT2 EXT2 Support */
diff --git a/include/configs/strider.h b/include/configs/strider.h
index 6604cec..fe7b25b 100644
--- a/include/configs/strider.h
+++ b/include/configs/strider.h
@@ -27,7 +27,6 @@
#define CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111

#define CONFIG_GENERIC_MMC
#define CONFIG_DOS_PARTITION
diff --git a/include/configs/ts4800.h b/include/configs/ts4800.h
index 2e5f38d..6053990 100644
--- a/include/configs/ts4800.h
+++ b/include/configs/ts4800.h
@@ -59,8 +59,6 @@
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR

-#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
-
#define CONFIG_MMC

#define CONFIG_GENERIC_MMC
diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h
index 6aeb078..59a2012 100644
--- a/include/configs/vf610twr.h
+++ b/include/configs/vf610twr.h
@@ -69,8 +69,6 @@
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 1

-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-
#define CONFIG_GENERIC_MMC
#define CONFIG_DOS_PARTITION

diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 3c8845d..b83626d 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -5403,10 +5403,6 @@ CONFIG_SYS_FSL_ERRATUM_DDR_115
CONFIG_SYS_FSL_ERRATUM_DDR_A003
CONFIG_SYS_FSL_ERRATUM_DDR_A003474
CONFIG_SYS_FSL_ERRATUM_ELBC_A001
-CONFIG_SYS_FSL_ERRATUM_ESDHC111
-CONFIG_SYS_FSL_ERRATUM_ESDHC13
-CONFIG_SYS_FSL_ERRATUM_ESDHC135
-CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
CONFIG_SYS_FSL_ERRATUM_I2C_A004447
CONFIG_SYS_FSL_ERRATUM_IFC_A002769
CONFIG_SYS_FSL_ERRATUM_IFC_A003399
--
2.7.4