[U-Boot] [PATCH V2 05/20] imx: mx7ulp: Add soc level initialization codes and functions

[Peng Fan <van.freenix@gmail.com>]

On Sun, Feb 12, 2017 at 10:19:41AM +0100, Stefano Babic wrote:
>Hi Peng,
>
>On 27/12/2016 11:04, Peng Fan wrote:
>> Implement soc level functions to get cpu rev, reset cause, enable cache,
>> etc. We will disable the wdog and init clocks in s_init at very early u-boot
>> phase.
>> 
>> Since the we are seeking the way to get chip id for mx7ulp, the get_cpu_rev
>> is hard coded to a fixed value. This may change in future.
>> 
>
>ok, understood, noted
>
>> Reuse some code in imx-common.
>> 
>> Signed-off-by: Peng Fan <peng.fan@nxp.com>
>> Signed-off-by: Ye Li <ye.li@nxp.com>
>> Cc: Stefano Babic <sbabic@denx.de>
>> ---
>> 
[.......]
>> +
>> +#if defined(CONFIG_DISPLAY_CPUINFO)
>> +const char *get_imx_type(u32 imxtype)
>> +{
>> +#ifdef CONFIG_MXC_OCOTP
>> +
>> +	u8 uid[8];
>> +	u32 val;
>> +
>> +	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
>> +	struct fuse_bank *bank = &ocotp->bank[0];
>> +	struct fuse_bank1_regs *fuse =
>> +		(struct fuse_bank1_regs *)bank->fuse_regs;
>> +
>> +	val = readl(&fuse->cfg0);
>> +	*uid = val & 0xFF;
>> +	*(uid + 1) = (val & 0xFF00) >> 8;
>> +
>> +	val = readl(&fuse->cfg1);
>> +	*(uid + 2) = val & 0xFF;
>> +	*(uid + 3) = (val & 0xFF00) >> 8;
>> +
>> +	val = readl(&fuse->cfg2);
>> +	*(uid + 4) = val & 0xFF;
>> +	*(uid + 5) = (val & 0xFF00) >> 8;
>> +
>> +	val = readl(&fuse->cfg3);
>> +	*(uid + 6) = val & 0xFF;
>> +	*(uid + 7) = (val & 0xFF00) >> 8;
>
>I think it can be better described here, at least what you want to read
>for fuse->cfg0..cfg3.

Discard in V3.

>
>> +
>> +	debug("UID = %02X %02X %02X %02X %02X %02X %02X %02X\r\n",
>> +	      uid[0], uid[1], uid[2], uid[3], uid[4], uid[5], uid[6], uid[7]);
>> +
>> +#endif
>> +	return "7ULP";
>> +}
>> +
[.....]
>> +
>> +u32 get_imx_reset_cause(void)
>> +{
>> +	return reset_cause;
>
>Why do you stored it ain a static variable ? Is it read just once from
>registers ?

This function could be removed, it reuses the one in imx-common.c

>
>> +}
>> +
>> +#ifdef CONFIG_ENV_IS_IN_MMC
>> +__weak int board_mmc_get_env_dev(int devno)
>> +{
>> +	return CONFIG_SYS_MMC_ENV_DEV;
>> +}
>> +
>> +int mmc_get_env_dev(void)
>> +{
>> +	int devno = 0;
>> +	u32 bt1_cfg = 0;
>> +
>> +	/* If not boot from sd/mmc, use default value */
>> +	if (get_boot_mode() == LOW_POWER_BOOT)
>> +		return CONFIG_SYS_MMC_ENV_DEV;
>> +
>> +	bt1_cfg = readl(CMC1_RBASE + 0x40);
>> +	devno = (bt1_cfg >> 9) & 0x7;
>> +
>> +	return board_mmc_get_env_dev(devno);
>> +}
>> +#endif
>> diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
>> index 1873185..68ee60f 100644
>> --- a/arch/arm/imx-common/Makefile
>> +++ b/arch/arm/imx-common/Makefile
>> @@ -31,6 +31,10 @@ obj-$(CONFIG_IMX_RDC) += rdc-sema.o
>>  obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
>>  obj-$(CONFIG_SECURE_BOOT)    += hab.o
>>  endif
>> +ifeq ($(SOC),$(filter $(SOC),mx7ulp))
>> +obj-y  += cache.o
>> +obj-$(CONFIG_SECURE_BOOT) += hab.o
>> +endif
>>  ifeq ($(SOC),$(filter $(SOC),vf610))
>>  obj-y += ddrmc-vf610.o
>>  endif
>> diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h
>> index 8bd1421..b052406 100644
>> --- a/arch/arm/include/asm/arch-imx/cpu.h
>> +++ b/arch/arm/include/asm/arch-imx/cpu.h
>> @@ -25,10 +25,12 @@
>>  #define MXC_CPU_MX6QP		0x69
>>  #define MXC_CPU_MX7S		0x71 /* dummy ID */
>>  #define MXC_CPU_MX7D		0x72
>> +#define MXC_CPU_MX7ULP		0x81 /* Temporally hard code */
>
>ok
>
>>  #define MXC_CPU_VF610		0xF6 /* dummy ID */
>>  
>>  #define MXC_SOC_MX6		0x60
>>  #define MXC_SOC_MX7		0x70
>> +#define MXC_SOC_MX7ULP		0x80 /* dummy */
>>  
>>  #define CHIP_REV_1_0            0x10
>>  #define CHIP_REV_1_1            0x11
>> diff --git a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h
>> index 30d0ba4..cdfbe2e 100644
>> --- a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h
>> +++ b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h
>> @@ -97,6 +97,11 @@
>>  #define CORE_B_ROM_SIZE			(SZ_32K + SZ_64K)
>>  #define CORE_B_ROM_BASE			(0x00000000)
>>  
>> +#define ROMCP_ARB_BASE_ADDR		CORE_B_ROM_BASE
>> +#define ROMCP_ARB_END_ADDR		CORE_B_ROM_SIZE
>> +#define IRAM_BASE_ADDR			OCRAM_0_BASE
>> +#define IRAM_SIZE			(SZ_128K + SZ_128K)
>> +
>
>Why is it here and not in Patch 2/20 ?

Move the 2/20 in V3.


Thanks,
Peng.