* [U-Boot] [PATCH V2 01/12] arm: dts: imx7: sync with Linux
@ 2017-04-13 6:09 Peng Fan
2017-04-13 6:09 ` [U-Boot] [PATCH V2 02/12] arm: dts: imx7d-sdb add basic dts Peng Fan
` (11 more replies)
0 siblings, 12 replies; 24+ messages in thread
From: Peng Fan @ 2017-04-13 6:09 UTC (permalink / raw)
To: u-boot
Sync with Linux commit 308ac756("Merge tag 'gpio-v4.11-3'").
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefan Agner <stefan.agner@toradex.com>
Cc: Stefano Babic <sbabic@denx.de>
---
V2:
remove imx7.dtsi
arch/arm/dts/imx7-colibri.dts | 10 +-
arch/arm/dts/imx7.dtsi | 194 -------
arch/arm/dts/imx7d-pinfunc.h | 111 ++--
arch/arm/dts/imx7d.dtsi | 140 +++++
arch/arm/dts/imx7s.dtsi | 999 ++++++++++++++++++++++++++++++++
include/dt-bindings/clock/imx7d-clock.h | 454 +++++++++++++++
6 files changed, 1657 insertions(+), 251 deletions(-)
delete mode 100644 arch/arm/dts/imx7.dtsi
create mode 100644 arch/arm/dts/imx7d.dtsi
create mode 100644 arch/arm/dts/imx7s.dtsi
create mode 100644 include/dt-bindings/clock/imx7d-clock.h
diff --git a/arch/arm/dts/imx7-colibri.dts b/arch/arm/dts/imx7-colibri.dts
index cbef5d5..f6c2105 100644
--- a/arch/arm/dts/imx7-colibri.dts
+++ b/arch/arm/dts/imx7-colibri.dts
@@ -6,7 +6,7 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
-#include "imx7.dtsi"
+#include "imx7d.dtsi"
/ {
model = "Toradex Colibri iMX7S/D";
@@ -83,15 +83,15 @@
&iomuxc_lpsr {
pinctrl_i2c1: i2c1-grp {
fsl,pins = <
- MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x4000007f
- MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x4000007f
+ MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x4000007f
+ MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x4000007f
>;
};
pinctrl_i2c1_gpio: i2c1-gpio-grp {
fsl,pins = <
- MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x4000007f
- MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x4000007f
+ MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x4000007f
+ MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x4000007f
>;
};
};
diff --git a/arch/arm/dts/imx7.dtsi b/arch/arm/dts/imx7.dtsi
deleted file mode 100644
index 755cc46..0000000
--- a/arch/arm/dts/imx7.dtsi
+++ /dev/null
@@ -1,194 +0,0 @@
-/*
- * Copyright 2016 Toradex AG
- *
- * SPDX-License-Identifier: GPL-2.0+ or X11
- */
-#include "imx7d-pinfunc.h"
-#include "skeleton.dtsi"
-
-/ {
- aliases {
- gpio0 = &gpio1;
- gpio1 = &gpio2;
- gpio2 = &gpio3;
- gpio3 = &gpio4;
- gpio4 = &gpio5;
- gpio5 = &gpio6;
- gpio6 = &gpio7;
- i2c0 = &i2c1;
- i2c1 = &i2c2;
- i2c2 = &i2c3;
- i2c3 = &i2c4;
- serial0 = &uart1;
- serial1 = &uart2;
- serial2 = &uart3;
- serial3 = &uart4;
- serial4 = &uart5;
- serial5 = &uart6;
- serial6 = &uart7;
- };
-
- soc {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- ranges;
-
- aips1: aips-bus at 30000000 {
- compatible = "fsl,aips-bus", "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x30000000 0x400000>;
- ranges;
-
- gpio1: gpio at 30200000 {
- compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
- reg = <0x30200000 0x10000>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpio2: gpio at 30210000 {
- compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
- reg = <0x30210000 0x10000>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpio3: gpio at 30220000 {
- compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
- reg = <0x30220000 0x10000>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpio4: gpio at 30230000 {
- compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
- reg = <0x30230000 0x10000>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpio5: gpio at 30240000 {
- compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
- reg = <0x30240000 0x10000>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpio6: gpio at 30250000 {
- compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
- reg = <0x30250000 0x10000>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpio7: gpio at 30260000 {
- compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
- reg = <0x30260000 0x10000>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- iomuxc_lpsr: iomuxc-lpsr at 302c0000 {
- compatible = "fsl,imx7d-iomuxc-lpsr";
- reg = <0x302c0000 0x10000>;
- fsl,input-sel = <&iomuxc>;
- };
-
- iomuxc: iomuxc at 30330000 {
- compatible = "fsl,imx7d-iomuxc";
- reg = <0x30330000 0x10000>;
- };
- };
-
- aips3: aips-bus at 30800000 {
- compatible = "fsl,aips-bus", "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x30800000 0x400000>;
- ranges;
-
- uart1: serial at 30860000 {
- compatible = "fsl,imx7d-uart",
- "fsl,imx6q-uart";
- reg = <0x30860000 0x10000>;
- status = "disabled";
- };
-
- uart2: serial at 30890000 {
- compatible = "fsl,imx7d-uart",
- "fsl,imx6q-uart";
- reg = <0x30890000 0x10000>;
- status = "disabled";
- };
-
- uart3: serial at 30880000 {
- compatible = "fsl,imx7d-uart",
- "fsl,imx6q-uart";
- reg = <0x30880000 0x10000>;
- status = "disabled";
- };
-
- i2c1: i2c at 30a20000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
- reg = <0x30a20000 0x10000>;
- status = "disabled";
- };
-
- i2c2: i2c at 30a30000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
- reg = <0x30a30000 0x10000>;
- status = "disabled";
- };
-
- i2c3: i2c at 30a40000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
- reg = <0x30a40000 0x10000>;
- status = "disabled";
- };
-
- i2c4: i2c at 30a50000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
- reg = <0x30a50000 0x10000>;
- status = "disabled";
- };
-
- uart4: serial at 30a60000 {
- compatible = "fsl,imx7d-uart",
- "fsl,imx6q-uart";
- reg = <0x30a60000 0x10000>;
- status = "disabled";
- };
-
- uart5: serial at 30a70000 {
- compatible = "fsl,imx7d-uart",
- "fsl,imx6q-uart";
- reg = <0x30a70000 0x10000>;
- status = "disabled";
- };
-
- uart6: serial at 30a80000 {
- compatible = "fsl,imx7d-uart",
- "fsl,imx6q-uart";
- reg = <0x30a80000 0x10000>;
- status = "disabled";
- };
-
- uart7: serial at 30a90000 {
- compatible = "fsl,imx7d-uart",
- "fsl,imx6q-uart";
- reg = <0x30a90000 0x10000>;
- status = "disabled";
- };
- };
- };
-};
diff --git a/arch/arm/dts/imx7d-pinfunc.h b/arch/arm/dts/imx7d-pinfunc.h
index 32d2464..f6f7e78 100644
--- a/arch/arm/dts/imx7d-pinfunc.h
+++ b/arch/arm/dts/imx7d-pinfunc.h
@@ -1,7 +1,10 @@
/*
* Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
*
- * SPDX-License-Identifier: GPL-2.0+
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
*/
#ifndef __DTS_IMX7D_PINFUNC_H
@@ -12,57 +15,61 @@
* <mux_reg conf_reg input_reg mux_mode input_val>
*/
-#define MX7D_PAD_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
-#define MX7D_PAD_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
-#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
-#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
-#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
-#define MX7D_PAD_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
-#define MX7D_PAD_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
-#define MX7D_PAD_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
-#define MX7D_PAD_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
-#define MX7D_PAD_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
-#define MX7D_PAD_GPIO1_IO01__OBSERVE0_OUT 0x0004 0x0034 0x0000 0x6 0x0
-#define MX7D_PAD_GPIO1_IO02__GPIO1_IO2 0x0008 0x0038 0x0000 0x0 0x0
-#define MX7D_PAD_GPIO1_IO02__PWM2_OUT 0x0008 0x0038 0x0000 0x1 0x0
-#define MX7D_PAD_GPIO1_IO02__CCM_ENET_REF_CLK1 0x0008 0x0038 0x0564 0x2 0x3
-#define MX7D_PAD_GPIO1_IO02__SAI2_MCLK 0x0008 0x0038 0x0000 0x3 0x0
-#define MX7D_PAD_GPIO1_IO02__CCM_CLKO1 0x0008 0x0038 0x0000 0x5 0x0
-#define MX7D_PAD_GPIO1_IO02__OBSERVE1_OUT 0x0008 0x0038 0x0000 0x6 0x0
-#define MX7D_PAD_GPIO1_IO02__USB_OTG1_ID 0x0008 0x0038 0x0734 0x7 0x3
-#define MX7D_PAD_GPIO1_IO03__GPIO1_IO3 0x000C 0x003C 0x0000 0x0 0x0
-#define MX7D_PAD_GPIO1_IO03__PWM3_OUT 0x000C 0x003C 0x0000 0x1 0x0
-#define MX7D_PAD_GPIO1_IO03__CCM_ENET_REF_CLK2 0x000C 0x003C 0x0570 0x2 0x3
-#define MX7D_PAD_GPIO1_IO03__SAI3_MCLK 0x000C 0x003C 0x0000 0x3 0x0
-#define MX7D_PAD_GPIO1_IO03__CCM_CLKO2 0x000C 0x003C 0x0000 0x5 0x0
-#define MX7D_PAD_GPIO1_IO03__OBSERVE2_OUT 0x000C 0x003C 0x0000 0x6 0x0
-#define MX7D_PAD_GPIO1_IO03__USB_OTG2_ID 0x000C 0x003C 0x0730 0x7 0x3
-#define MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x0010 0x0040 0x0000 0x0 0x0
-#define MX7D_PAD_GPIO1_IO04__USB_OTG1_OC 0x0010 0x0040 0x072C 0x1 0x1
-#define MX7D_PAD_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x1
-#define MX7D_PAD_GPIO1_IO04__UART5_CTS_B 0x0010 0x0040 0x0710 0x3 0x4
-#define MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x0010 0x0040 0x05D4 0x4 0x2
-#define MX7D_PAD_GPIO1_IO04__OBSERVE3_OUT 0x0010 0x0040 0x0000 0x6 0x0
-#define MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x0014 0x0044 0x0000 0x0 0x0
-#define MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR 0x0014 0x0044 0x0000 0x1 0x0
-#define MX7D_PAD_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0x1
-#define MX7D_PAD_GPIO1_IO05__UART5_RTS_B 0x0014 0x0044 0x0710 0x3 0x5
-#define MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x0014 0x0044 0x05D8 0x4 0x2
-#define MX7D_PAD_GPIO1_IO05__OBSERVE4_OUT 0x0014 0x0044 0x0000 0x6 0x0
-#define MX7D_PAD_GPIO1_IO06__GPIO1_IO6 0x0018 0x0048 0x0000 0x0 0x0
-#define MX7D_PAD_GPIO1_IO06__USB_OTG2_OC 0x0018 0x0048 0x0728 0x1 0x1
-#define MX7D_PAD_GPIO1_IO06__FLEXTIMER1_CH6 0x0018 0x0048 0x059C 0x2 0x1
-#define MX7D_PAD_GPIO1_IO06__UART5_RX_DATA 0x0018 0x0048 0x0714 0x3 0x4
-#define MX7D_PAD_GPIO1_IO06__I2C2_SCL 0x0018 0x0048 0x05DC 0x4 0x2
-#define MX7D_PAD_GPIO1_IO06__CCM_WAIT 0x0018 0x0048 0x0000 0x5 0x0
-#define MX7D_PAD_GPIO1_IO06__KPP_ROW4 0x0018 0x0048 0x0624 0x6 0x1
-#define MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x001C 0x004C 0x0000 0x0 0x0
-#define MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR 0x001C 0x004C 0x0000 0x1 0x0
-#define MX7D_PAD_GPIO1_IO07__FLEXTIMER1_CH7 0x001C 0x004C 0x05A0 0x2 0x1
-#define MX7D_PAD_GPIO1_IO07__UART5_TX_DATA 0x001C 0x004C 0x0714 0x3 0x5
-#define MX7D_PAD_GPIO1_IO07__I2C2_SDA 0x001C 0x004C 0x05E0 0x4 0x2
-#define MX7D_PAD_GPIO1_IO07__CCM_STOP 0x001C 0x004C 0x0000 0x5 0x0
-#define MX7D_PAD_GPIO1_IO07__KPP_COL4 0x001C 0x004C 0x0604 0x6 0x1
+#define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO01__OBSERVE0_OUT 0x0004 0x0034 0x0000 0x6 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x0008 0x0038 0x0000 0x0 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO02__PWM2_OUT 0x0008 0x0038 0x0000 0x1 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO02__CCM_ENET_REF_CLK1 0x0008 0x0038 0x0564 0x2 0x3
+#define MX7D_PAD_LPSR_GPIO1_IO02__SAI2_MCLK 0x0008 0x0038 0x0000 0x3 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO02__CCM_CLKO1 0x0008 0x0038 0x0000 0x5 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO02__OBSERVE1_OUT 0x0008 0x0038 0x0000 0x6 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO02__USB_OTG1_ID 0x0008 0x0038 0x0734 0x7 0x3
+#define MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x000C 0x003C 0x0000 0x0 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO03__PWM3_OUT 0x000C 0x003C 0x0000 0x1 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO03__CCM_ENET_REF_CLK2 0x000C 0x003C 0x0570 0x2 0x3
+#define MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK 0x000C 0x003C 0x0000 0x3 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2 0x000C 0x003C 0x0000 0x5 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO03__OBSERVE2_OUT 0x000C 0x003C 0x0000 0x6 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO03__USB_OTG2_ID 0x000C 0x003C 0x0730 0x7 0x3
+#define MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x0010 0x0040 0x0000 0x0 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x0010 0x0040 0x072C 0x1 0x1
+#define MX7D_PAD_LPSR_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x1
+#define MX7D_PAD_LPSR_GPIO1_IO04__UART5_DCE_CTS 0x0010 0x0040 0x0000 0x3 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO04__UART5_DTE_RTS 0x0010 0x0040 0x0710 0x3 0x4
+#define MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x0010 0x0040 0x05D4 0x4 0x2
+#define MX7D_PAD_LPSR_GPIO1_IO04__OBSERVE3_OUT 0x0010 0x0040 0x0000 0x6 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x0014 0x0044 0x0000 0x0 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO05__USB_OTG1_PWR 0x0014 0x0044 0x0000 0x1 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0x1
+#define MX7D_PAD_LPSR_GPIO1_IO05__UART5_DCE_RTS 0x0014 0x0044 0x0710 0x3 0x5
+#define MX7D_PAD_LPSR_GPIO1_IO05__UART5_DTE_CTS 0x0014 0x0044 0x0000 0x3 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x0014 0x0044 0x05D8 0x4 0x2
+#define MX7D_PAD_LPSR_GPIO1_IO05__OBSERVE4_OUT 0x0014 0x0044 0x0000 0x6 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x0018 0x0048 0x0000 0x0 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC 0x0018 0x0048 0x0728 0x1 0x1
+#define MX7D_PAD_LPSR_GPIO1_IO06__FLEXTIMER1_CH6 0x0018 0x0048 0x059C 0x2 0x1
+#define MX7D_PAD_LPSR_GPIO1_IO06__UART5_DCE_RX 0x0018 0x0048 0x0714 0x3 0x4
+#define MX7D_PAD_LPSR_GPIO1_IO06__UART5_DTE_TX 0x0018 0x0048 0x0000 0x3 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO06__I2C2_SCL 0x0018 0x0048 0x05DC 0x4 0x2
+#define MX7D_PAD_LPSR_GPIO1_IO06__CCM_WAIT 0x0018 0x0048 0x0000 0x5 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO06__KPP_ROW4 0x0018 0x0048 0x0624 0x6 0x1
+#define MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x001C 0x004C 0x0000 0x0 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO07__USB_OTG2_PWR 0x001C 0x004C 0x0000 0x1 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO07__FLEXTIMER1_CH7 0x001C 0x004C 0x05A0 0x2 0x1
+#define MX7D_PAD_LPSR_GPIO1_IO07__UART5_DCE_TX 0x001C 0x004C 0x0000 0x3 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO07__UART5_DTE_RX 0x001C 0x004C 0x0714 0x3 0x5
+#define MX7D_PAD_LPSR_GPIO1_IO07__I2C2_SDA 0x001C 0x004C 0x05E0 0x4 0x2
+#define MX7D_PAD_LPSR_GPIO1_IO07__CCM_STOP 0x001C 0x004C 0x0000 0x5 0x0
+#define MX7D_PAD_LPSR_GPIO1_IO07__KPP_COL4 0x001C 0x004C 0x0604 0x6 0x1
#define MX7D_PAD_GPIO1_IO08__GPIO1_IO8 0x0014 0x026C 0x0000 0x0 0x0
#define MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x0014 0x026C 0x0000 0x1 0x0
#define MX7D_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0014 0x026C 0x0000 0x2 0x0
diff --git a/arch/arm/dts/imx7d.dtsi b/arch/arm/dts/imx7d.dtsi
new file mode 100644
index 0000000..f6dee41
--- /dev/null
+++ b/arch/arm/dts/imx7d.dtsi
@@ -0,0 +1,140 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ * Copyright 2016 Toradex AG
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "imx7s.dtsi"
+
+/ {
+ cpus {
+ cpu0: cpu at 0 {
+ operating-points = <
+ /* KHz uV */
+ 996000 1075000
+ 792000 975000
+ >;
+ clock-frequency = <996000000>;
+ };
+
+ cpu1: cpu at 1 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <1>;
+ clock-frequency = <996000000>;
+ };
+ };
+
+ soc {
+ etm at 3007d000 {
+ compatible = "arm,coresight-etm3x", "arm,primecell";
+ reg = <0x3007d000 0x1000>;
+
+ /*
+ * System will hang if added nosmp in kernel command line
+ * without arm,primecell-periphid because amba bus try to
+ * read id and core1 power off at this time.
+ */
+ arm,primecell-periphid = <0xbb956>;
+ cpu = <&cpu1>;
+ clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ etm1_out_port: endpoint {
+ remote-endpoint = <&ca_funnel_in_port1>;
+ };
+ };
+ };
+ };
+};
+
+&aips3 {
+ usbotg2: usb at 30b20000 {
+ compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
+ reg = <0x30b20000 0x200>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_USB_CTRL_CLK>;
+ fsl,usbphy = <&usbphynop2>;
+ fsl,usbmisc = <&usbmisc2 0>;
+ phy-clkgate-delay-us = <400>;
+ status = "disabled";
+ };
+
+ usbmisc2: usbmisc at 30b20200 {
+ #index-cells = <1>;
+ compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
+ reg = <0x30b20200 0x200>;
+ };
+
+ usbphynop2: usbphynop2 {
+ compatible = "usb-nop-xceiv";
+ clocks = <&clks IMX7D_USB_PHY2_CLK>;
+ clock-names = "main_clk";
+ };
+
+ fec2: ethernet at 30bf0000 {
+ compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
+ reg = <0x30bf0000 0x10000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
+ <&clks IMX7D_ENET_AXI_ROOT_CLK>,
+ <&clks IMX7D_ENET2_TIME_ROOT_CLK>,
+ <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
+ <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
+ clock-names = "ipg", "ahb", "ptp",
+ "enet_clk_ref", "enet_out";
+ fsl,num-tx-queues=<3>;
+ fsl,num-rx-queues=<3>;
+ status = "disabled";
+ };
+};
+
+&ca_funnel_ports {
+ port at 1 {
+ reg = <1>;
+ ca_funnel_in_port1: endpoint {
+ slave-mode;
+ remote-endpoint = <&etm1_out_port>;
+ };
+ };
+};
diff --git a/arch/arm/dts/imx7s.dtsi b/arch/arm/dts/imx7s.dtsi
new file mode 100644
index 0000000..a7d48e7
--- /dev/null
+++ b/arch/arm/dts/imx7s.dtsi
@@ -0,0 +1,999 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ * Copyright 2016 Toradex AG
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/clock/imx7d-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "imx7d-pinfunc.h"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ /*
+ * The decompressor and also some bootloaders rely on a
+ * pre-existing /chosen node to be available to insert the
+ * command line and merge other ATAGS info.
+ * Also for U-Boot there must be a pre-existing /memory node.
+ */
+ chosen {};
+ memory { device_type = "memory"; reg = <0 0>; };
+
+ aliases {
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ gpio4 = &gpio5;
+ gpio5 = &gpio6;
+ gpio6 = &gpio7;
+ i2c0 = &i2c1;
+ i2c1 = &i2c2;
+ i2c2 = &i2c3;
+ i2c3 = &i2c4;
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
+ mmc2 = &usdhc3;
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
+ serial4 = &uart5;
+ serial5 = &uart6;
+ serial6 = &uart7;
+ spi0 = &ecspi1;
+ spi1 = &ecspi2;
+ spi2 = &ecspi3;
+ spi3 = &ecspi4;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu at 0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0>;
+ clock-frequency = <792000000>;
+ clock-latency = <61036>; /* two CLK32 periods */
+ clocks = <&clks IMX7D_CLK_ARM>;
+ };
+ };
+
+ ckil: clock-cki {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "ckil";
+ };
+
+ osc: clock-osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "osc";
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&intc>;
+ ranges;
+
+ funnel at 30041000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0x30041000 0x1000>;
+ clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
+ clock-names = "apb_pclk";
+
+ ca_funnel_ports: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* funnel input ports */
+ port at 0 {
+ reg = <0>;
+ ca_funnel_in_port0: endpoint {
+ slave-mode;
+ remote-endpoint = <&etm0_out_port>;
+ };
+ };
+
+ /* funnel output port */
+ port at 2 {
+ reg = <0>;
+ ca_funnel_out_port0: endpoint {
+ remote-endpoint = <&hugo_funnel_in_port0>;
+ };
+ };
+
+ /* the other input ports are not connect to anything */
+ };
+ };
+
+ etm at 3007c000 {
+ compatible = "arm,coresight-etm3x", "arm,primecell";
+ reg = <0x3007c000 0x1000>;
+ cpu = <&cpu0>;
+ clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ etm0_out_port: endpoint {
+ remote-endpoint = <&ca_funnel_in_port0>;
+ };
+ };
+ };
+
+ funnel at 30083000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0x30083000 0x1000>;
+ clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* funnel input ports */
+ port at 0 {
+ reg = <0>;
+ hugo_funnel_in_port0: endpoint {
+ slave-mode;
+ remote-endpoint = <&ca_funnel_out_port0>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ hugo_funnel_in_port1: endpoint {
+ slave-mode; /* M4 input */
+ };
+ };
+
+ port at 2 {
+ reg = <0>;
+ hugo_funnel_out_port0: endpoint {
+ remote-endpoint = <&etf_in_port>;
+ };
+ };
+
+ /* the other input ports are not connect to anything */
+ };
+ };
+
+ etf at 30084000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x30084000 0x1000>;
+ clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+ etf_in_port: endpoint {
+ slave-mode;
+ remote-endpoint = <&hugo_funnel_out_port0>;
+ };
+ };
+
+ port at 1 {
+ reg = <0>;
+ etf_out_port: endpoint {
+ remote-endpoint = <&replicator_in_port0>;
+ };
+ };
+ };
+ };
+
+ etr at 30086000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x30086000 0x1000>;
+ clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ etr_in_port: endpoint {
+ slave-mode;
+ remote-endpoint = <&replicator_out_port1>;
+ };
+ };
+ };
+
+ tpiu at 30087000 {
+ compatible = "arm,coresight-tpiu", "arm,primecell";
+ reg = <0x30087000 0x1000>;
+ clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ tpiu_in_port: endpoint {
+ slave-mode;
+ remote-endpoint = <&replicator_out_port1>;
+ };
+ };
+ };
+
+ replicator {
+ /*
+ * non-configurable replicators don't show up on the
+ * AMBA bus. As such no need to add "arm,primecell"
+ */
+ compatible = "arm,coresight-replicator";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* replicator output ports */
+ port at 0 {
+ reg = <0>;
+ replicator_out_port0: endpoint {
+ remote-endpoint = <&tpiu_in_port>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ replicator_out_port1: endpoint {
+ remote-endpoint = <&etr_in_port>;
+ };
+ };
+
+ /* replicator input port */
+ port at 2 {
+ reg = <0>;
+ replicator_in_port0: endpoint {
+ slave-mode;
+ remote-endpoint = <&etf_out_port>;
+ };
+ };
+ };
+ };
+
+ intc: interrupt-controller at 31001000 {
+ compatible = "arm,cortex-a7-gic";
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x31001000 0x1000>,
+ <0x31002000 0x2000>,
+ <0x31004000 0x2000>,
+ <0x31006000 0x2000>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ aips1: aips-bus at 30000000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x30000000 0x400000>;
+ ranges;
+
+ gpio1: gpio at 30200000 {
+ compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
+ reg = <0x30200000 0x10000>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */
+ <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>;
+ };
+
+ gpio2: gpio at 30210000 {
+ compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
+ reg = <0x30210000 0x10000>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&iomuxc 0 13 32>;
+ };
+
+ gpio3: gpio at 30220000 {
+ compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
+ reg = <0x30220000 0x10000>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&iomuxc 0 45 29>;
+ };
+
+ gpio4: gpio at 30230000 {
+ compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
+ reg = <0x30230000 0x10000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&iomuxc 0 74 24>;
+ };
+
+ gpio5: gpio at 30240000 {
+ compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
+ reg = <0x30240000 0x10000>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&iomuxc 0 98 18>;
+ };
+
+ gpio6: gpio at 30250000 {
+ compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
+ reg = <0x30250000 0x10000>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&iomuxc 0 116 23>;
+ };
+
+ gpio7: gpio at 30260000 {
+ compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
+ reg = <0x30260000 0x10000>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&iomuxc 0 139 16>;
+ };
+
+ wdog1: wdog at 30280000 {
+ compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
+ reg = <0x30280000 0x10000>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
+ };
+
+ wdog2: wdog at 30290000 {
+ compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
+ reg = <0x30290000 0x10000>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
+ status = "disabled";
+ };
+
+ wdog3: wdog at 302a0000 {
+ compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
+ reg = <0x302a0000 0x10000>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
+ status = "disabled";
+ };
+
+ wdog4: wdog at 302b0000 {
+ compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
+ reg = <0x302b0000 0x10000>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
+ status = "disabled";
+ };
+
+ iomuxc_lpsr: iomuxc-lpsr at 302c0000 {
+ compatible = "fsl,imx7d-iomuxc-lpsr";
+ reg = <0x302c0000 0x10000>;
+ fsl,input-sel = <&iomuxc>;
+ };
+
+ gpt1: gpt at 302d0000 {
+ compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
+ reg = <0x302d0000 0x10000>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_CLK_DUMMY>,
+ <&clks IMX7D_GPT1_ROOT_CLK>;
+ clock-names = "ipg", "per";
+ };
+
+ gpt2: gpt at 302e0000 {
+ compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
+ reg = <0x302e0000 0x10000>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_CLK_DUMMY>,
+ <&clks IMX7D_GPT2_ROOT_CLK>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ gpt3: gpt at 302f0000 {
+ compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
+ reg = <0x302f0000 0x10000>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_CLK_DUMMY>,
+ <&clks IMX7D_GPT3_ROOT_CLK>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ gpt4: gpt at 30300000 {
+ compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
+ reg = <0x30300000 0x10000>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_CLK_DUMMY>,
+ <&clks IMX7D_GPT4_ROOT_CLK>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ iomuxc: iomuxc at 30330000 {
+ compatible = "fsl,imx7d-iomuxc";
+ reg = <0x30330000 0x10000>;
+ };
+
+ gpr: iomuxc-gpr at 30340000 {
+ compatible = "fsl,imx7d-iomuxc-gpr", "syscon";
+ reg = <0x30340000 0x10000>;
+ };
+
+ ocotp: ocotp-ctrl at 30350000 {
+ compatible = "fsl,imx7d-ocotp", "syscon";
+ reg = <0x30350000 0x10000>;
+ clocks = <&clks IMX7D_OCOTP_CLK>;
+ };
+
+ anatop: anatop at 30360000 {
+ compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
+ "syscon", "simple-bus";
+ reg = <0x30360000 0x10000>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+
+ reg_1p0d: regulator-vdd1p0d {
+ compatible = "fsl,anatop-regulator";
+ regulator-name = "vdd1p0d";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1200000>;
+ anatop-reg-offset = <0x210>;
+ anatop-vol-bit-shift = <8>;
+ anatop-vol-bit-width = <5>;
+ anatop-min-bit-val = <8>;
+ anatop-min-voltage = <800000>;
+ anatop-max-voltage = <1200000>;
+ };
+ };
+
+ snvs: snvs at 30370000 {
+ compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
+ reg = <0x30370000 0x10000>;
+
+ snvs_rtc: snvs-rtc-lp {
+ compatible = "fsl,sec-v4.0-mon-rtc-lp";
+ regmap = <&snvs>;
+ offset = <0x34>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ snvs_poweroff: snvs-poweroff {
+ compatible = "syscon-poweroff";
+ regmap = <&snvs>;
+ offset = <0x38>;
+ mask = <0x60>;
+ };
+
+ snvs_pwrkey: snvs-powerkey {
+ compatible = "fsl,sec-v4.0-pwrkey";
+ regmap = <&snvs>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ linux,keycode = <KEY_POWER>;
+ wakeup-source;
+ };
+ };
+
+ clks: ccm at 30380000 {
+ compatible = "fsl,imx7d-ccm";
+ reg = <0x30380000 0x10000>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ #clock-cells = <1>;
+ clocks = <&ckil>, <&osc>;
+ clock-names = "ckil", "osc";
+ };
+
+ src: src at 30390000 {
+ compatible = "fsl,imx7d-src", "fsl,imx51-src", "syscon";
+ reg = <0x30390000 0x10000>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ #reset-cells = <1>;
+ };
+ };
+
+ aips2: aips-bus at 30400000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x30400000 0x400000>;
+ ranges;
+
+ adc1: adc at 30610000 {
+ compatible = "fsl,imx7d-adc";
+ reg = <0x30610000 0x10000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_ADC_ROOT_CLK>;
+ clock-names = "adc";
+ status = "disabled";
+ };
+
+ adc2: adc at 30620000 {
+ compatible = "fsl,imx7d-adc";
+ reg = <0x30620000 0x10000>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_ADC_ROOT_CLK>;
+ clock-names = "adc";
+ status = "disabled";
+ };
+
+ ecspi4: ecspi at 30630000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
+ reg = <0x30630000 0x10000>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>,
+ <&clks IMX7D_ECSPI4_ROOT_CLK>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ pwm1: pwm at 30660000 {
+ compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
+ reg = <0x30660000 0x10000>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
+ <&clks IMX7D_PWM1_ROOT_CLK>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm2: pwm at 30670000 {
+ compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
+ reg = <0x30670000 0x10000>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
+ <&clks IMX7D_PWM2_ROOT_CLK>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm3: pwm at 30680000 {
+ compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
+ reg = <0x30680000 0x10000>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
+ <&clks IMX7D_PWM3_ROOT_CLK>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm4: pwm at 30690000 {
+ compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
+ reg = <0x30690000 0x10000>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
+ <&clks IMX7D_PWM4_ROOT_CLK>;
+ clock-names = "ipg", "per";
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ lcdif: lcdif at 30730000 {
+ compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif";
+ reg = <0x30730000 0x10000>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
+ <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>;
+ clock-names = "pix", "axi";
+ status = "disabled";
+ };
+ };
+
+ aips3: aips-bus at 30800000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x30800000 0x400000>;
+ ranges;
+
+ ecspi1: ecspi at 30820000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
+ reg = <0x30820000 0x10000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
+ <&clks IMX7D_ECSPI1_ROOT_CLK>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ ecspi2: ecspi at 30830000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
+ reg = <0x30830000 0x10000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
+ <&clks IMX7D_ECSPI2_ROOT_CLK>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ ecspi3: ecspi at 30840000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
+ reg = <0x30840000 0x10000>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
+ <&clks IMX7D_ECSPI3_ROOT_CLK>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart1: serial at 30860000 {
+ compatible = "fsl,imx7d-uart",
+ "fsl,imx6q-uart";
+ reg = <0x30860000 0x10000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_UART1_ROOT_CLK>,
+ <&clks IMX7D_UART1_ROOT_CLK>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart2: serial at 30890000 {
+ compatible = "fsl,imx7d-uart",
+ "fsl,imx6q-uart";
+ reg = <0x30890000 0x10000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_UART2_ROOT_CLK>,
+ <&clks IMX7D_UART2_ROOT_CLK>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart3: serial at 30880000 {
+ compatible = "fsl,imx7d-uart",
+ "fsl,imx6q-uart";
+ reg = <0x30880000 0x10000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_UART3_ROOT_CLK>,
+ <&clks IMX7D_UART3_ROOT_CLK>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ sai1: sai at 308a0000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
+ reg = <0x308a0000 0x10000>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_SAI1_IPG_CLK>,
+ <&clks IMX7D_SAI1_ROOT_CLK>,
+ <&clks IMX7D_CLK_DUMMY>,
+ <&clks IMX7D_CLK_DUMMY>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dma-names = "rx", "tx";
+ dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
+ status = "disabled";
+ };
+
+ sai2: sai at 308b0000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
+ reg = <0x308b0000 0x10000>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_SAI2_IPG_CLK>,
+ <&clks IMX7D_SAI2_ROOT_CLK>,
+ <&clks IMX7D_CLK_DUMMY>,
+ <&clks IMX7D_CLK_DUMMY>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dma-names = "rx", "tx";
+ dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
+ status = "disabled";
+ };
+
+ sai3: sai at 308c0000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
+ reg = <0x308c0000 0x10000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_SAI3_IPG_CLK>,
+ <&clks IMX7D_SAI3_ROOT_CLK>,
+ <&clks IMX7D_CLK_DUMMY>,
+ <&clks IMX7D_CLK_DUMMY>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dma-names = "rx", "tx";
+ dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
+ status = "disabled";
+ };
+
+ flexcan1: can at 30a00000 {
+ compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
+ reg = <0x30a00000 0x10000>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_CLK_DUMMY>,
+ <&clks IMX7D_CAN1_ROOT_CLK>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ flexcan2: can at 30a10000 {
+ compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
+ reg = <0x30a10000 0x10000>;
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_CLK_DUMMY>,
+ <&clks IMX7D_CAN2_ROOT_CLK>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ i2c1: i2c at 30a20000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
+ reg = <0x30a20000 0x10000>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
+ status = "disabled";
+ };
+
+ i2c2: i2c at 30a30000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
+ reg = <0x30a30000 0x10000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
+ status = "disabled";
+ };
+
+ i2c3: i2c at 30a40000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
+ reg = <0x30a40000 0x10000>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
+ status = "disabled";
+ };
+
+ i2c4: i2c at 30a50000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
+ reg = <0x30a50000 0x10000>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
+ status = "disabled";
+ };
+
+ uart4: serial at 30a60000 {
+ compatible = "fsl,imx7d-uart",
+ "fsl,imx6q-uart";
+ reg = <0x30a60000 0x10000>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_UART4_ROOT_CLK>,
+ <&clks IMX7D_UART4_ROOT_CLK>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart5: serial at 30a70000 {
+ compatible = "fsl,imx7d-uart",
+ "fsl,imx6q-uart";
+ reg = <0x30a70000 0x10000>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_UART5_ROOT_CLK>,
+ <&clks IMX7D_UART5_ROOT_CLK>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart6: serial at 30a80000 {
+ compatible = "fsl,imx7d-uart",
+ "fsl,imx6q-uart";
+ reg = <0x30a80000 0x10000>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_UART6_ROOT_CLK>,
+ <&clks IMX7D_UART6_ROOT_CLK>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart7: serial at 30a90000 {
+ compatible = "fsl,imx7d-uart",
+ "fsl,imx6q-uart";
+ reg = <0x30a90000 0x10000>;
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_UART7_ROOT_CLK>,
+ <&clks IMX7D_UART7_ROOT_CLK>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ usbotg1: usb at 30b10000 {
+ compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
+ reg = <0x30b10000 0x200>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_USB_CTRL_CLK>;
+ fsl,usbphy = <&usbphynop1>;
+ fsl,usbmisc = <&usbmisc1 0>;
+ phy-clkgate-delay-us = <400>;
+ status = "disabled";
+ };
+
+ usbh: usb at 30b30000 {
+ compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
+ reg = <0x30b30000 0x200>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_USB_CTRL_CLK>;
+ fsl,usbphy = <&usbphynop3>;
+ fsl,usbmisc = <&usbmisc3 0>;
+ phy_type = "hsic";
+ dr_mode = "host";
+ phy-clkgate-delay-us = <400>;
+ status = "disabled";
+ };
+
+ usbmisc1: usbmisc at 30b10200 {
+ #index-cells = <1>;
+ compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
+ reg = <0x30b10200 0x200>;
+ };
+
+ usbmisc3: usbmisc at 30b30200 {
+ #index-cells = <1>;
+ compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
+ reg = <0x30b30200 0x200>;
+ };
+
+ usbphynop1: usbphynop1 {
+ compatible = "usb-nop-xceiv";
+ clocks = <&clks IMX7D_USB_PHY1_CLK>;
+ clock-names = "main_clk";
+ };
+
+ usbphynop3: usbphynop3 {
+ compatible = "usb-nop-xceiv";
+ clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
+ clock-names = "main_clk";
+ };
+
+ usdhc1: usdhc at 30b40000 {
+ compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
+ reg = <0x30b40000 0x10000>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_CLK_DUMMY>,
+ <&clks IMX7D_CLK_DUMMY>,
+ <&clks IMX7D_USDHC1_ROOT_CLK>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ usdhc2: usdhc at 30b50000 {
+ compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
+ reg = <0x30b50000 0x10000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_CLK_DUMMY>,
+ <&clks IMX7D_CLK_DUMMY>,
+ <&clks IMX7D_USDHC2_ROOT_CLK>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ usdhc3: usdhc at 30b60000 {
+ compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
+ reg = <0x30b60000 0x10000>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_CLK_DUMMY>,
+ <&clks IMX7D_CLK_DUMMY>,
+ <&clks IMX7D_USDHC3_ROOT_CLK>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ sdma: sdma at 30bd0000 {
+ compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma";
+ reg = <0x30bd0000 0x10000>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_SDMA_CORE_CLK>,
+ <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
+ clock-names = "ipg", "ahb";
+ #dma-cells = <3>;
+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
+ };
+
+ fec1: ethernet at 30be0000 {
+ compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
+ reg = <0x30be0000 0x10000>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
+ <&clks IMX7D_ENET_AXI_ROOT_CLK>,
+ <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
+ <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
+ <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
+ clock-names = "ipg", "ahb", "ptp",
+ "enet_clk_ref", "enet_out";
+ fsl,num-tx-queues=<3>;
+ fsl,num-rx-queues=<3>;
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/include/dt-bindings/clock/imx7d-clock.h b/include/dt-bindings/clock/imx7d-clock.h
new file mode 100644
index 0000000..a7a1a50
--- /dev/null
+++ b/include/dt-bindings/clock/imx7d-clock.h
@@ -0,0 +1,454 @@
+/*
+ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX7D_H
+#define __DT_BINDINGS_CLOCK_IMX7D_H
+
+#define IMX7D_OSC_24M_CLK 0
+#define IMX7D_PLL_ARM_MAIN 1
+#define IMX7D_PLL_ARM_MAIN_CLK 2
+#define IMX7D_PLL_ARM_MAIN_SRC 3
+#define IMX7D_PLL_ARM_MAIN_BYPASS 4
+#define IMX7D_PLL_SYS_MAIN 5
+#define IMX7D_PLL_SYS_MAIN_CLK 6
+#define IMX7D_PLL_SYS_MAIN_SRC 7
+#define IMX7D_PLL_SYS_MAIN_BYPASS 8
+#define IMX7D_PLL_SYS_MAIN_480M 9
+#define IMX7D_PLL_SYS_MAIN_240M 10
+#define IMX7D_PLL_SYS_MAIN_120M 11
+#define IMX7D_PLL_SYS_MAIN_480M_CLK 12
+#define IMX7D_PLL_SYS_MAIN_240M_CLK 13
+#define IMX7D_PLL_SYS_MAIN_120M_CLK 14
+#define IMX7D_PLL_SYS_PFD0_392M_CLK 15
+#define IMX7D_PLL_SYS_PFD0_196M 16
+#define IMX7D_PLL_SYS_PFD0_196M_CLK 17
+#define IMX7D_PLL_SYS_PFD1_332M_CLK 18
+#define IMX7D_PLL_SYS_PFD1_166M 19
+#define IMX7D_PLL_SYS_PFD1_166M_CLK 20
+#define IMX7D_PLL_SYS_PFD2_270M_CLK 21
+#define IMX7D_PLL_SYS_PFD2_135M 22
+#define IMX7D_PLL_SYS_PFD2_135M_CLK 23
+#define IMX7D_PLL_SYS_PFD3_CLK 24
+#define IMX7D_PLL_SYS_PFD4_CLK 25
+#define IMX7D_PLL_SYS_PFD5_CLK 26
+#define IMX7D_PLL_SYS_PFD6_CLK 27
+#define IMX7D_PLL_SYS_PFD7_CLK 28
+#define IMX7D_PLL_ENET_MAIN 29
+#define IMX7D_PLL_ENET_MAIN_CLK 30
+#define IMX7D_PLL_ENET_MAIN_SRC 31
+#define IMX7D_PLL_ENET_MAIN_BYPASS 32
+#define IMX7D_PLL_ENET_MAIN_500M 33
+#define IMX7D_PLL_ENET_MAIN_250M 34
+#define IMX7D_PLL_ENET_MAIN_125M 35
+#define IMX7D_PLL_ENET_MAIN_100M 36
+#define IMX7D_PLL_ENET_MAIN_50M 37
+#define IMX7D_PLL_ENET_MAIN_40M 38
+#define IMX7D_PLL_ENET_MAIN_25M 39
+#define IMX7D_PLL_ENET_MAIN_500M_CLK 40
+#define IMX7D_PLL_ENET_MAIN_250M_CLK 41
+#define IMX7D_PLL_ENET_MAIN_125M_CLK 42
+#define IMX7D_PLL_ENET_MAIN_100M_CLK 43
+#define IMX7D_PLL_ENET_MAIN_50M_CLK 44
+#define IMX7D_PLL_ENET_MAIN_40M_CLK 45
+#define IMX7D_PLL_ENET_MAIN_25M_CLK 46
+#define IMX7D_PLL_DRAM_MAIN 47
+#define IMX7D_PLL_DRAM_MAIN_CLK 48
+#define IMX7D_PLL_DRAM_MAIN_SRC 49
+#define IMX7D_PLL_DRAM_MAIN_BYPASS 50
+#define IMX7D_PLL_DRAM_MAIN_533M 51
+#define IMX7D_PLL_DRAM_MAIN_533M_CLK 52
+#define IMX7D_PLL_AUDIO_MAIN 53
+#define IMX7D_PLL_AUDIO_MAIN_CLK 54
+#define IMX7D_PLL_AUDIO_MAIN_SRC 55
+#define IMX7D_PLL_AUDIO_MAIN_BYPASS 56
+#define IMX7D_PLL_VIDEO_MAIN_CLK 57
+#define IMX7D_PLL_VIDEO_MAIN 58
+#define IMX7D_PLL_VIDEO_MAIN_SRC 59
+#define IMX7D_PLL_VIDEO_MAIN_BYPASS 60
+#define IMX7D_USB_MAIN_480M_CLK 61
+#define IMX7D_ARM_A7_ROOT_CLK 62
+#define IMX7D_ARM_A7_ROOT_SRC 63
+#define IMX7D_ARM_A7_ROOT_CG 64
+#define IMX7D_ARM_A7_ROOT_DIV 65
+#define IMX7D_ARM_M4_ROOT_CLK 66
+#define IMX7D_ARM_M4_ROOT_SRC 67
+#define IMX7D_ARM_M4_ROOT_CG 68
+#define IMX7D_ARM_M4_ROOT_DIV 69
+#define IMX7D_ARM_M0_ROOT_CLK 70
+#define IMX7D_ARM_M0_ROOT_SRC 71
+#define IMX7D_ARM_M0_ROOT_CG 72
+#define IMX7D_ARM_M0_ROOT_DIV 73
+#define IMX7D_MAIN_AXI_ROOT_CLK 74
+#define IMX7D_MAIN_AXI_ROOT_SRC 75
+#define IMX7D_MAIN_AXI_ROOT_CG 76
+#define IMX7D_MAIN_AXI_ROOT_DIV 77
+#define IMX7D_DISP_AXI_ROOT_CLK 78
+#define IMX7D_DISP_AXI_ROOT_SRC 79
+#define IMX7D_DISP_AXI_ROOT_CG 80
+#define IMX7D_DISP_AXI_ROOT_DIV 81
+#define IMX7D_ENET_AXI_ROOT_CLK 82
+#define IMX7D_ENET_AXI_ROOT_SRC 83
+#define IMX7D_ENET_AXI_ROOT_CG 84
+#define IMX7D_ENET_AXI_ROOT_DIV 85
+#define IMX7D_NAND_USDHC_BUS_ROOT_CLK 86
+#define IMX7D_NAND_USDHC_BUS_ROOT_SRC 87
+#define IMX7D_NAND_USDHC_BUS_ROOT_CG 88
+#define IMX7D_NAND_USDHC_BUS_ROOT_DIV 89
+#define IMX7D_AHB_CHANNEL_ROOT_CLK 90
+#define IMX7D_AHB_CHANNEL_ROOT_SRC 91
+#define IMX7D_AHB_CHANNEL_ROOT_CG 92
+#define IMX7D_AHB_CHANNEL_ROOT_DIV 93
+#define IMX7D_DRAM_PHYM_ROOT_CLK 94
+#define IMX7D_DRAM_PHYM_ROOT_SRC 95
+#define IMX7D_DRAM_PHYM_ROOT_CG 96
+#define IMX7D_DRAM_PHYM_ROOT_DIV 97
+#define IMX7D_DRAM_ROOT_CLK 98
+#define IMX7D_DRAM_ROOT_SRC 99
+#define IMX7D_DRAM_ROOT_CG 100
+#define IMX7D_DRAM_ROOT_DIV 101
+#define IMX7D_DRAM_PHYM_ALT_ROOT_CLK 102
+#define IMX7D_DRAM_PHYM_ALT_ROOT_SRC 103
+#define IMX7D_DRAM_PHYM_ALT_ROOT_CG 104
+#define IMX7D_DRAM_PHYM_ALT_ROOT_DIV 105
+#define IMX7D_DRAM_ALT_ROOT_CLK 106
+#define IMX7D_DRAM_ALT_ROOT_SRC 107
+#define IMX7D_DRAM_ALT_ROOT_CG 108
+#define IMX7D_DRAM_ALT_ROOT_DIV 109
+#define IMX7D_USB_HSIC_ROOT_CLK 110
+#define IMX7D_USB_HSIC_ROOT_SRC 111
+#define IMX7D_USB_HSIC_ROOT_CG 112
+#define IMX7D_USB_HSIC_ROOT_DIV 113
+#define IMX7D_PCIE_CTRL_ROOT_CLK 114
+#define IMX7D_PCIE_CTRL_ROOT_SRC 115
+#define IMX7D_PCIE_CTRL_ROOT_CG 116
+#define IMX7D_PCIE_CTRL_ROOT_DIV 117
+#define IMX7D_PCIE_PHY_ROOT_CLK 118
+#define IMX7D_PCIE_PHY_ROOT_SRC 119
+#define IMX7D_PCIE_PHY_ROOT_CG 120
+#define IMX7D_PCIE_PHY_ROOT_DIV 121
+#define IMX7D_EPDC_PIXEL_ROOT_CLK 122
+#define IMX7D_EPDC_PIXEL_ROOT_SRC 123
+#define IMX7D_EPDC_PIXEL_ROOT_CG 124
+#define IMX7D_EPDC_PIXEL_ROOT_DIV 125
+#define IMX7D_LCDIF_PIXEL_ROOT_CLK 126
+#define IMX7D_LCDIF_PIXEL_ROOT_SRC 127
+#define IMX7D_LCDIF_PIXEL_ROOT_CG 128
+#define IMX7D_LCDIF_PIXEL_ROOT_DIV 129
+#define IMX7D_MIPI_DSI_ROOT_CLK 130
+#define IMX7D_MIPI_DSI_ROOT_SRC 131
+#define IMX7D_MIPI_DSI_ROOT_CG 132
+#define IMX7D_MIPI_DSI_ROOT_DIV 133
+#define IMX7D_MIPI_CSI_ROOT_CLK 134
+#define IMX7D_MIPI_CSI_ROOT_SRC 135
+#define IMX7D_MIPI_CSI_ROOT_CG 136
+#define IMX7D_MIPI_CSI_ROOT_DIV 137
+#define IMX7D_MIPI_DPHY_ROOT_CLK 138
+#define IMX7D_MIPI_DPHY_ROOT_SRC 139
+#define IMX7D_MIPI_DPHY_ROOT_CG 140
+#define IMX7D_MIPI_DPHY_ROOT_DIV 141
+#define IMX7D_SAI1_ROOT_CLK 142
+#define IMX7D_SAI1_ROOT_SRC 143
+#define IMX7D_SAI1_ROOT_CG 144
+#define IMX7D_SAI1_ROOT_DIV 145
+#define IMX7D_SAI2_ROOT_CLK 146
+#define IMX7D_SAI2_ROOT_SRC 147
+#define IMX7D_SAI2_ROOT_CG 148
+#define IMX7D_SAI2_ROOT_DIV 149
+#define IMX7D_SAI3_ROOT_CLK 150
+#define IMX7D_SAI3_ROOT_SRC 151
+#define IMX7D_SAI3_ROOT_CG 152
+#define IMX7D_SAI3_ROOT_DIV 153
+#define IMX7D_SPDIF_ROOT_CLK 154
+#define IMX7D_SPDIF_ROOT_SRC 155
+#define IMX7D_SPDIF_ROOT_CG 156
+#define IMX7D_SPDIF_ROOT_DIV 157
+#define IMX7D_ENET1_REF_ROOT_CLK 158
+#define IMX7D_ENET1_REF_ROOT_SRC 159
+#define IMX7D_ENET1_REF_ROOT_CG 160
+#define IMX7D_ENET1_REF_ROOT_DIV 161
+#define IMX7D_ENET1_TIME_ROOT_CLK 162
+#define IMX7D_ENET1_TIME_ROOT_SRC 163
+#define IMX7D_ENET1_TIME_ROOT_CG 164
+#define IMX7D_ENET1_TIME_ROOT_DIV 165
+#define IMX7D_ENET2_REF_ROOT_CLK 166
+#define IMX7D_ENET2_REF_ROOT_SRC 167
+#define IMX7D_ENET2_REF_ROOT_CG 168
+#define IMX7D_ENET2_REF_ROOT_DIV 169
+#define IMX7D_ENET2_TIME_ROOT_CLK 170
+#define IMX7D_ENET2_TIME_ROOT_SRC 171
+#define IMX7D_ENET2_TIME_ROOT_CG 172
+#define IMX7D_ENET2_TIME_ROOT_DIV 173
+#define IMX7D_ENET_PHY_REF_ROOT_CLK 174
+#define IMX7D_ENET_PHY_REF_ROOT_SRC 175
+#define IMX7D_ENET_PHY_REF_ROOT_CG 176
+#define IMX7D_ENET_PHY_REF_ROOT_DIV 177
+#define IMX7D_EIM_ROOT_CLK 178
+#define IMX7D_EIM_ROOT_SRC 179
+#define IMX7D_EIM_ROOT_CG 180
+#define IMX7D_EIM_ROOT_DIV 181
+#define IMX7D_NAND_ROOT_CLK 182
+#define IMX7D_NAND_ROOT_SRC 183
+#define IMX7D_NAND_ROOT_CG 184
+#define IMX7D_NAND_ROOT_DIV 185
+#define IMX7D_QSPI_ROOT_CLK 186
+#define IMX7D_QSPI_ROOT_SRC 187
+#define IMX7D_QSPI_ROOT_CG 188
+#define IMX7D_QSPI_ROOT_DIV 189
+#define IMX7D_USDHC1_ROOT_CLK 190
+#define IMX7D_USDHC1_ROOT_SRC 191
+#define IMX7D_USDHC1_ROOT_CG 192
+#define IMX7D_USDHC1_ROOT_DIV 193
+#define IMX7D_USDHC2_ROOT_CLK 194
+#define IMX7D_USDHC2_ROOT_SRC 195
+#define IMX7D_USDHC2_ROOT_CG 196
+#define IMX7D_USDHC2_ROOT_DIV 197
+#define IMX7D_USDHC3_ROOT_CLK 198
+#define IMX7D_USDHC3_ROOT_SRC 199
+#define IMX7D_USDHC3_ROOT_CG 200
+#define IMX7D_USDHC3_ROOT_DIV 201
+#define IMX7D_CAN1_ROOT_CLK 202
+#define IMX7D_CAN1_ROOT_SRC 203
+#define IMX7D_CAN1_ROOT_CG 204
+#define IMX7D_CAN1_ROOT_DIV 205
+#define IMX7D_CAN2_ROOT_CLK 206
+#define IMX7D_CAN2_ROOT_SRC 207
+#define IMX7D_CAN2_ROOT_CG 208
+#define IMX7D_CAN2_ROOT_DIV 209
+#define IMX7D_I2C1_ROOT_CLK 210
+#define IMX7D_I2C1_ROOT_SRC 211
+#define IMX7D_I2C1_ROOT_CG 212
+#define IMX7D_I2C1_ROOT_DIV 213
+#define IMX7D_I2C2_ROOT_CLK 214
+#define IMX7D_I2C2_ROOT_SRC 215
+#define IMX7D_I2C2_ROOT_CG 216
+#define IMX7D_I2C2_ROOT_DIV 217
+#define IMX7D_I2C3_ROOT_CLK 218
+#define IMX7D_I2C3_ROOT_SRC 219
+#define IMX7D_I2C3_ROOT_CG 220
+#define IMX7D_I2C3_ROOT_DIV 221
+#define IMX7D_I2C4_ROOT_CLK 222
+#define IMX7D_I2C4_ROOT_SRC 223
+#define IMX7D_I2C4_ROOT_CG 224
+#define IMX7D_I2C4_ROOT_DIV 225
+#define IMX7D_UART1_ROOT_CLK 226
+#define IMX7D_UART1_ROOT_SRC 227
+#define IMX7D_UART1_ROOT_CG 228
+#define IMX7D_UART1_ROOT_DIV 229
+#define IMX7D_UART2_ROOT_CLK 230
+#define IMX7D_UART2_ROOT_SRC 231
+#define IMX7D_UART2_ROOT_CG 232
+#define IMX7D_UART2_ROOT_DIV 233
+#define IMX7D_UART3_ROOT_CLK 234
+#define IMX7D_UART3_ROOT_SRC 235
+#define IMX7D_UART3_ROOT_CG 236
+#define IMX7D_UART3_ROOT_DIV 237
+#define IMX7D_UART4_ROOT_CLK 238
+#define IMX7D_UART4_ROOT_SRC 239
+#define IMX7D_UART4_ROOT_CG 240
+#define IMX7D_UART4_ROOT_DIV 241
+#define IMX7D_UART5_ROOT_CLK 242
+#define IMX7D_UART5_ROOT_SRC 243
+#define IMX7D_UART5_ROOT_CG 244
+#define IMX7D_UART5_ROOT_DIV 245
+#define IMX7D_UART6_ROOT_CLK 246
+#define IMX7D_UART6_ROOT_SRC 247
+#define IMX7D_UART6_ROOT_CG 248
+#define IMX7D_UART6_ROOT_DIV 249
+#define IMX7D_UART7_ROOT_CLK 250
+#define IMX7D_UART7_ROOT_SRC 251
+#define IMX7D_UART7_ROOT_CG 252
+#define IMX7D_UART7_ROOT_DIV 253
+#define IMX7D_ECSPI1_ROOT_CLK 254
+#define IMX7D_ECSPI1_ROOT_SRC 255
+#define IMX7D_ECSPI1_ROOT_CG 256
+#define IMX7D_ECSPI1_ROOT_DIV 257
+#define IMX7D_ECSPI2_ROOT_CLK 258
+#define IMX7D_ECSPI2_ROOT_SRC 259
+#define IMX7D_ECSPI2_ROOT_CG 260
+#define IMX7D_ECSPI2_ROOT_DIV 261
+#define IMX7D_ECSPI3_ROOT_CLK 262
+#define IMX7D_ECSPI3_ROOT_SRC 263
+#define IMX7D_ECSPI3_ROOT_CG 264
+#define IMX7D_ECSPI3_ROOT_DIV 265
+#define IMX7D_ECSPI4_ROOT_CLK 266
+#define IMX7D_ECSPI4_ROOT_SRC 267
+#define IMX7D_ECSPI4_ROOT_CG 268
+#define IMX7D_ECSPI4_ROOT_DIV 269
+#define IMX7D_PWM1_ROOT_CLK 270
+#define IMX7D_PWM1_ROOT_SRC 271
+#define IMX7D_PWM1_ROOT_CG 272
+#define IMX7D_PWM1_ROOT_DIV 273
+#define IMX7D_PWM2_ROOT_CLK 274
+#define IMX7D_PWM2_ROOT_SRC 275
+#define IMX7D_PWM2_ROOT_CG 276
+#define IMX7D_PWM2_ROOT_DIV 277
+#define IMX7D_PWM3_ROOT_CLK 278
+#define IMX7D_PWM3_ROOT_SRC 279
+#define IMX7D_PWM3_ROOT_CG 280
+#define IMX7D_PWM3_ROOT_DIV 281
+#define IMX7D_PWM4_ROOT_CLK 282
+#define IMX7D_PWM4_ROOT_SRC 283
+#define IMX7D_PWM4_ROOT_CG 284
+#define IMX7D_PWM4_ROOT_DIV 285
+#define IMX7D_FLEXTIMER1_ROOT_CLK 286
+#define IMX7D_FLEXTIMER1_ROOT_SRC 287
+#define IMX7D_FLEXTIMER1_ROOT_CG 288
+#define IMX7D_FLEXTIMER1_ROOT_DIV 289
+#define IMX7D_FLEXTIMER2_ROOT_CLK 290
+#define IMX7D_FLEXTIMER2_ROOT_SRC 291
+#define IMX7D_FLEXTIMER2_ROOT_CG 292
+#define IMX7D_FLEXTIMER2_ROOT_DIV 293
+#define IMX7D_SIM1_ROOT_CLK 294
+#define IMX7D_SIM1_ROOT_SRC 295
+#define IMX7D_SIM1_ROOT_CG 296
+#define IMX7D_SIM1_ROOT_DIV 297
+#define IMX7D_SIM2_ROOT_CLK 298
+#define IMX7D_SIM2_ROOT_SRC 299
+#define IMX7D_SIM2_ROOT_CG 300
+#define IMX7D_SIM2_ROOT_DIV 301
+#define IMX7D_GPT1_ROOT_CLK 302
+#define IMX7D_GPT1_ROOT_SRC 303
+#define IMX7D_GPT1_ROOT_CG 304
+#define IMX7D_GPT1_ROOT_DIV 305
+#define IMX7D_GPT2_ROOT_CLK 306
+#define IMX7D_GPT2_ROOT_SRC 307
+#define IMX7D_GPT2_ROOT_CG 308
+#define IMX7D_GPT2_ROOT_DIV 309
+#define IMX7D_GPT3_ROOT_CLK 310
+#define IMX7D_GPT3_ROOT_SRC 311
+#define IMX7D_GPT3_ROOT_CG 312
+#define IMX7D_GPT3_ROOT_DIV 313
+#define IMX7D_GPT4_ROOT_CLK 314
+#define IMX7D_GPT4_ROOT_SRC 315
+#define IMX7D_GPT4_ROOT_CG 316
+#define IMX7D_GPT4_ROOT_DIV 317
+#define IMX7D_TRACE_ROOT_CLK 318
+#define IMX7D_TRACE_ROOT_SRC 319
+#define IMX7D_TRACE_ROOT_CG 320
+#define IMX7D_TRACE_ROOT_DIV 321
+#define IMX7D_WDOG1_ROOT_CLK 322
+#define IMX7D_WDOG_ROOT_SRC 323
+#define IMX7D_WDOG_ROOT_CG 324
+#define IMX7D_WDOG_ROOT_DIV 325
+#define IMX7D_CSI_MCLK_ROOT_CLK 326
+#define IMX7D_CSI_MCLK_ROOT_SRC 327
+#define IMX7D_CSI_MCLK_ROOT_CG 328
+#define IMX7D_CSI_MCLK_ROOT_DIV 329
+#define IMX7D_AUDIO_MCLK_ROOT_CLK 330
+#define IMX7D_AUDIO_MCLK_ROOT_SRC 331
+#define IMX7D_AUDIO_MCLK_ROOT_CG 332
+#define IMX7D_AUDIO_MCLK_ROOT_DIV 333
+#define IMX7D_WRCLK_ROOT_CLK 334
+#define IMX7D_WRCLK_ROOT_SRC 335
+#define IMX7D_WRCLK_ROOT_CG 336
+#define IMX7D_WRCLK_ROOT_DIV 337
+#define IMX7D_CLKO1_ROOT_SRC 338
+#define IMX7D_CLKO1_ROOT_CG 339
+#define IMX7D_CLKO1_ROOT_DIV 340
+#define IMX7D_CLKO2_ROOT_SRC 341
+#define IMX7D_CLKO2_ROOT_CG 342
+#define IMX7D_CLKO2_ROOT_DIV 343
+#define IMX7D_MAIN_AXI_ROOT_PRE_DIV 344
+#define IMX7D_DISP_AXI_ROOT_PRE_DIV 345
+#define IMX7D_ENET_AXI_ROOT_PRE_DIV 346
+#define IMX7D_NAND_USDHC_BUS_ROOT_PRE_DIV 347
+#define IMX7D_AHB_CHANNEL_ROOT_PRE_DIV 348
+#define IMX7D_USB_HSIC_ROOT_PRE_DIV 349
+#define IMX7D_PCIE_CTRL_ROOT_PRE_DIV 350
+#define IMX7D_PCIE_PHY_ROOT_PRE_DIV 351
+#define IMX7D_EPDC_PIXEL_ROOT_PRE_DIV 352
+#define IMX7D_LCDIF_PIXEL_ROOT_PRE_DIV 353
+#define IMX7D_MIPI_DSI_ROOT_PRE_DIV 354
+#define IMX7D_MIPI_CSI_ROOT_PRE_DIV 355
+#define IMX7D_MIPI_DPHY_ROOT_PRE_DIV 356
+#define IMX7D_SAI1_ROOT_PRE_DIV 357
+#define IMX7D_SAI2_ROOT_PRE_DIV 358
+#define IMX7D_SAI3_ROOT_PRE_DIV 359
+#define IMX7D_SPDIF_ROOT_PRE_DIV 360
+#define IMX7D_ENET1_REF_ROOT_PRE_DIV 361
+#define IMX7D_ENET1_TIME_ROOT_PRE_DIV 362
+#define IMX7D_ENET2_REF_ROOT_PRE_DIV 363
+#define IMX7D_ENET2_TIME_ROOT_PRE_DIV 364
+#define IMX7D_ENET_PHY_REF_ROOT_PRE_DIV 365
+#define IMX7D_EIM_ROOT_PRE_DIV 366
+#define IMX7D_NAND_ROOT_PRE_DIV 367
+#define IMX7D_QSPI_ROOT_PRE_DIV 368
+#define IMX7D_USDHC1_ROOT_PRE_DIV 369
+#define IMX7D_USDHC2_ROOT_PRE_DIV 370
+#define IMX7D_USDHC3_ROOT_PRE_DIV 371
+#define IMX7D_CAN1_ROOT_PRE_DIV 372
+#define IMX7D_CAN2_ROOT_PRE_DIV 373
+#define IMX7D_I2C1_ROOT_PRE_DIV 374
+#define IMX7D_I2C2_ROOT_PRE_DIV 375
+#define IMX7D_I2C3_ROOT_PRE_DIV 376
+#define IMX7D_I2C4_ROOT_PRE_DIV 377
+#define IMX7D_UART1_ROOT_PRE_DIV 378
+#define IMX7D_UART2_ROOT_PRE_DIV 379
+#define IMX7D_UART3_ROOT_PRE_DIV 380
+#define IMX7D_UART4_ROOT_PRE_DIV 381
+#define IMX7D_UART5_ROOT_PRE_DIV 382
+#define IMX7D_UART6_ROOT_PRE_DIV 383
+#define IMX7D_UART7_ROOT_PRE_DIV 384
+#define IMX7D_ECSPI1_ROOT_PRE_DIV 385
+#define IMX7D_ECSPI2_ROOT_PRE_DIV 386
+#define IMX7D_ECSPI3_ROOT_PRE_DIV 387
+#define IMX7D_ECSPI4_ROOT_PRE_DIV 388
+#define IMX7D_PWM1_ROOT_PRE_DIV 389
+#define IMX7D_PWM2_ROOT_PRE_DIV 390
+#define IMX7D_PWM3_ROOT_PRE_DIV 391
+#define IMX7D_PWM4_ROOT_PRE_DIV 392
+#define IMX7D_FLEXTIMER1_ROOT_PRE_DIV 393
+#define IMX7D_FLEXTIMER2_ROOT_PRE_DIV 394
+#define IMX7D_SIM1_ROOT_PRE_DIV 395
+#define IMX7D_SIM2_ROOT_PRE_DIV 396
+#define IMX7D_GPT1_ROOT_PRE_DIV 397
+#define IMX7D_GPT2_ROOT_PRE_DIV 398
+#define IMX7D_GPT3_ROOT_PRE_DIV 399
+#define IMX7D_GPT4_ROOT_PRE_DIV 400
+#define IMX7D_TRACE_ROOT_PRE_DIV 401
+#define IMX7D_WDOG_ROOT_PRE_DIV 402
+#define IMX7D_CSI_MCLK_ROOT_PRE_DIV 403
+#define IMX7D_AUDIO_MCLK_ROOT_PRE_DIV 404
+#define IMX7D_WRCLK_ROOT_PRE_DIV 405
+#define IMX7D_CLKO1_ROOT_PRE_DIV 406
+#define IMX7D_CLKO2_ROOT_PRE_DIV 407
+#define IMX7D_DRAM_PHYM_ALT_ROOT_PRE_DIV 408
+#define IMX7D_DRAM_ALT_ROOT_PRE_DIV 409
+#define IMX7D_LVDS1_IN_CLK 410
+#define IMX7D_LVDS1_OUT_SEL 411
+#define IMX7D_LVDS1_OUT_CLK 412
+#define IMX7D_CLK_DUMMY 413
+#define IMX7D_GPT_3M_CLK 414
+#define IMX7D_OCRAM_CLK 415
+#define IMX7D_OCRAM_S_CLK 416
+#define IMX7D_WDOG2_ROOT_CLK 417
+#define IMX7D_WDOG3_ROOT_CLK 418
+#define IMX7D_WDOG4_ROOT_CLK 419
+#define IMX7D_SDMA_CORE_CLK 420
+#define IMX7D_USB1_MAIN_480M_CLK 421
+#define IMX7D_USB_CTRL_CLK 422
+#define IMX7D_USB_PHY1_CLK 423
+#define IMX7D_USB_PHY2_CLK 424
+#define IMX7D_IPG_ROOT_CLK 425
+#define IMX7D_SAI1_IPG_CLK 426
+#define IMX7D_SAI2_IPG_CLK 427
+#define IMX7D_SAI3_IPG_CLK 428
+#define IMX7D_PLL_AUDIO_TEST_DIV 429
+#define IMX7D_PLL_AUDIO_POST_DIV 430
+#define IMX7D_PLL_VIDEO_TEST_DIV 431
+#define IMX7D_PLL_VIDEO_POST_DIV 432
+#define IMX7D_MU_ROOT_CLK 433
+#define IMX7D_SEMA4_HS_ROOT_CLK 434
+#define IMX7D_PLL_DRAM_TEST_DIV 435
+#define IMX7D_ADC_ROOT_CLK 436
+#define IMX7D_CLK_ARM 437
+#define IMX7D_CKIL 438
+#define IMX7D_OCOTP_CLK 439
+#define IMX7D_CLK_END 440
+#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */
--
2.6.2
^ permalink raw reply related [flat|nested] 24+ messages in thread* [U-Boot] [PATCH V2 02/12] arm: dts: imx7d-sdb add basic dts 2017-04-13 6:09 [U-Boot] [PATCH V2 01/12] arm: dts: imx7: sync with Linux Peng Fan @ 2017-04-13 6:09 ` Peng Fan 2017-04-13 6:09 ` [U-Boot] [PATCH V2 03/12] arm: dts: imx7d-sdb: add spi gpio node Peng Fan ` (10 subsequent siblings) 11 siblings, 0 replies; 24+ messages in thread From: Peng Fan @ 2017-04-13 6:09 UTC (permalink / raw) To: u-boot Add basic dts for i.MX7D-SDB board. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> --- V2: Drop dts file from NXP vendor tree. arch/arm/dts/Makefile | 3 ++- arch/arm/dts/imx7d-sdb.dts | 19 +++++++++++++++++++ configs/mx7dsabresd_defconfig | 3 ++- 3 files changed, 23 insertions(+), 2 deletions(-) create mode 100644 arch/arm/dts/imx7d-sdb.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 8187f65..d4eaf35 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -325,7 +325,8 @@ dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \ imx6ul-isiot-nand.dtb \ imx6ul-opos6uldev.dtb -dtb-$(CONFIG_MX7) += imx7-colibri.dtb +dtb-$(CONFIG_MX7) += imx7-colibri.dtb \ + imx7d-sdb.dtb dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb diff --git a/arch/arm/dts/imx7d-sdb.dts b/arch/arm/dts/imx7d-sdb.dts new file mode 100644 index 0000000..0378897 --- /dev/null +++ b/arch/arm/dts/imx7d-sdb.dts @@ -0,0 +1,19 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "imx7d.dtsi" + +/ { + model = "Freescale i.MX7 SabreSD Board"; + compatible = "fsl,imx7d-sdb", "fsl,imx7d"; + + memory { + reg = <0x80000000 0x80000000>; + }; + +}; diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig index 9541e12..5bdc638 100644 --- a/configs/mx7dsabresd_defconfig +++ b/configs/mx7dsabresd_defconfig @@ -5,6 +5,7 @@ CONFIG_TARGET_MX7DSABRESD=y CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb" CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set @@ -32,6 +33,7 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_USB=y @@ -44,4 +46,3 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="FSL" CONFIG_G_DNL_VENDOR_NUM=0x0525 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 -CONFIG_OF_LIBFDT=y -- 2.6.2 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH V2 03/12] arm: dts: imx7d-sdb: add spi gpio node 2017-04-13 6:09 [U-Boot] [PATCH V2 01/12] arm: dts: imx7: sync with Linux Peng Fan 2017-04-13 6:09 ` [U-Boot] [PATCH V2 02/12] arm: dts: imx7d-sdb add basic dts Peng Fan @ 2017-04-13 6:09 ` Peng Fan 2017-04-13 6:09 ` [U-Boot] [PATCH V2 04/12] arm: dts: imx7d-sdb: add regulator node for usb and mmc Peng Fan ` (9 subsequent siblings) 11 siblings, 0 replies; 24+ messages in thread From: Peng Fan @ 2017-04-13 6:09 UTC (permalink / raw) To: u-boot Add spi gpio node for 74LV595. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> --- V2: New arch/arm/dts/imx7d-sdb.dts | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/dts/imx7d-sdb.dts b/arch/arm/dts/imx7d-sdb.dts index 0378897..3b8f1cb 100644 --- a/arch/arm/dts/imx7d-sdb.dts +++ b/arch/arm/dts/imx7d-sdb.dts @@ -16,4 +16,39 @@ reg = <0x80000000 0x80000000>; }; + spi4 { + compatible = "spi-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + status = "okay"; + gpio-sck = <&gpio1 13 0>; + gpio-mosi = <&gpio1 9 0>; + cs-gpios = <&gpio1 12 0>; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; + + gpio_spi: gpio_spi at 0 { + compatible = "fairchild,74hc595"; + gpio-controller; + #gpio-cells = <2>; + reg = <0>; + registers-number = <1>; + registers-default = /bits/ 8 <0x74>; /* Enable PERI_3V3, SENSOR_RST_B and HDMI_RST*/ + spi-max-frequency = <100000>; + }; + }; +}; + +&iomuxc { + imx7d-sdb { + pinctrl_spi1: spi1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59 + MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59 + MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59 + >; + }; + }; + }; -- 2.6.2 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH V2 04/12] arm: dts: imx7d-sdb: add regulator node for usb and mmc 2017-04-13 6:09 [U-Boot] [PATCH V2 01/12] arm: dts: imx7: sync with Linux Peng Fan 2017-04-13 6:09 ` [U-Boot] [PATCH V2 02/12] arm: dts: imx7d-sdb add basic dts Peng Fan 2017-04-13 6:09 ` [U-Boot] [PATCH V2 03/12] arm: dts: imx7d-sdb: add spi gpio node Peng Fan @ 2017-04-13 6:09 ` Peng Fan 2017-04-13 6:09 ` [U-Boot] [PATCH V2 05/12] arm: dts: imx7d-sdb: add i2c support Peng Fan ` (8 subsequent siblings) 11 siblings, 0 replies; 24+ messages in thread From: Peng Fan @ 2017-04-13 6:09 UTC (permalink / raw) To: u-boot Add regulator node for usb and mmc. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> --- V2: New arch/arm/dts/imx7d-sdb.dts | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm/dts/imx7d-sdb.dts b/arch/arm/dts/imx7d-sdb.dts index 3b8f1cb..df9dfb9 100644 --- a/arch/arm/dts/imx7d-sdb.dts +++ b/arch/arm/dts/imx7d-sdb.dts @@ -38,6 +38,42 @@ spi-max-frequency = <100000>; }; }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_otg1_vbus: regulator at 0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator at 1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_sd1_vmmc: regulator at 3 { + compatible = "regulator-fixed"; + regulator-name = "VDD_SD1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + startup-delay-us = <200000>; + enable-active-high; + }; + }; }; &iomuxc { -- 2.6.2 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH V2 05/12] arm: dts: imx7d-sdb: add i2c support 2017-04-13 6:09 [U-Boot] [PATCH V2 01/12] arm: dts: imx7: sync with Linux Peng Fan ` (2 preceding siblings ...) 2017-04-13 6:09 ` [U-Boot] [PATCH V2 04/12] arm: dts: imx7d-sdb: add regulator node for usb and mmc Peng Fan @ 2017-04-13 6:09 ` Peng Fan 2017-04-13 6:09 ` [U-Boot] [PATCH V2 06/12] arm: dts: imx7d-sdb: add usdhc support Peng Fan ` (7 subsequent siblings) 11 siblings, 0 replies; 24+ messages in thread From: Peng Fan @ 2017-04-13 6:09 UTC (permalink / raw) To: u-boot Add i2c support. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> --- V2: New arch/arm/dts/imx7d-sdb.dts | 146 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 146 insertions(+) diff --git a/arch/arm/dts/imx7d-sdb.dts b/arch/arm/dts/imx7d-sdb.dts index df9dfb9..7fab6f2 100644 --- a/arch/arm/dts/imx7d-sdb.dts +++ b/arch/arm/dts/imx7d-sdb.dts @@ -85,6 +85,152 @@ MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59 >; }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f + MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f + MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f + >; + }; }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pfuze3000 at 08 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; }; -- 2.6.2 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH V2 06/12] arm: dts: imx7d-sdb: add usdhc support 2017-04-13 6:09 [U-Boot] [PATCH V2 01/12] arm: dts: imx7: sync with Linux Peng Fan ` (3 preceding siblings ...) 2017-04-13 6:09 ` [U-Boot] [PATCH V2 05/12] arm: dts: imx7d-sdb: add i2c support Peng Fan @ 2017-04-13 6:09 ` Peng Fan 2017-04-13 6:09 ` [U-Boot] [PATCH V2 07/12] spi: kconfig: add soft spi Kconfig entry Peng Fan ` (6 subsequent siblings) 11 siblings, 0 replies; 24+ messages in thread From: Peng Fan @ 2017-04-13 6:09 UTC (permalink / raw) To: u-boot Add usdhc support Signed-off-by: Peng Fan <peng.fan@nxp.com> --- V2: New arch/arm/dts/imx7d-sdb.dts | 73 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/arch/arm/dts/imx7d-sdb.dts b/arch/arm/dts/imx7d-sdb.dts index 7fab6f2..85b83c3 100644 --- a/arch/arm/dts/imx7d-sdb.dts +++ b/arch/arm/dts/imx7d-sdb.dts @@ -113,6 +113,55 @@ MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f >; }; + + pinctrl_usdhc1_gpio: usdhc1_gpiogrp { + fsl,pins = < + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ + MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ + MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */ + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x59 + MX7D_PAD_SD2_CLK__SD2_CLK 0x19 + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 + MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x19 /* WL_REG_ON */ + MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x19 /* WL_HOST_WAKE */ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 + >; + }; }; }; @@ -234,3 +283,27 @@ pinctrl-0 = <&pinctrl_i2c4>; status = "okay"; }; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + non-removable; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + non-removable; + status = "okay"; +}; -- 2.6.2 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH V2 07/12] spi: kconfig: add soft spi Kconfig entry 2017-04-13 6:09 [U-Boot] [PATCH V2 01/12] arm: dts: imx7: sync with Linux Peng Fan ` (4 preceding siblings ...) 2017-04-13 6:09 ` [U-Boot] [PATCH V2 06/12] arm: dts: imx7d-sdb: add usdhc support Peng Fan @ 2017-04-13 6:09 ` Peng Fan 2017-05-03 6:06 ` Jagan Teki 2017-04-13 6:09 ` [U-Boot] [PATCH V2 08/12] gpio: 74x164: make oe-pins optional Peng Fan ` (5 subsequent siblings) 11 siblings, 1 reply; 24+ messages in thread From: Peng Fan @ 2017-04-13 6:09 UTC (permalink / raw) To: u-boot Add the Kconfig entry for SOFT_SPI which uses gpio to simulate the SPI signals. We use it for accessing 74x164 on some i.MX boards. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Jagan Teki <jagan@openedev.com> Cc: Stefano Babic <sbabic@denx.de> --- V2: None drivers/spi/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index f3f7dbe..bef864f 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -197,6 +197,12 @@ config OMAP3_SPI endif # if DM_SPI +config SOFT_SPI + bool "Soft SPI driver" + help + Enable Soft SPI driver. This driver is to use GPIO simulate + the SPI protocol. + config FSL_ESPI bool "Freescale eSPI driver" help -- 2.6.2 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH V2 07/12] spi: kconfig: add soft spi Kconfig entry 2017-04-13 6:09 ` [U-Boot] [PATCH V2 07/12] spi: kconfig: add soft spi Kconfig entry Peng Fan @ 2017-05-03 6:06 ` Jagan Teki 2017-05-08 2:47 ` Peng Fan 0 siblings, 1 reply; 24+ messages in thread From: Jagan Teki @ 2017-05-03 6:06 UTC (permalink / raw) To: u-boot On Thu, Apr 13, 2017 at 11:39 AM, Peng Fan <peng.fan@nxp.com> wrote: > Add the Kconfig entry for SOFT_SPI which uses gpio to simulate the > SPI signals. We use it for accessing 74x164 on some i.MX boards. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > Cc: Jagan Teki <jagan@openedev.com> > Cc: Stefano Babic <sbabic@denx.de> > --- > > V2: > None > > drivers/spi/Kconfig | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig > index f3f7dbe..bef864f 100644 > --- a/drivers/spi/Kconfig > +++ b/drivers/spi/Kconfig > @@ -197,6 +197,12 @@ config OMAP3_SPI > > endif # if DM_SPI > > +config SOFT_SPI > + bool "Soft SPI driver" Did you move this for dm-driven file? since we've two files with same config > + help > + Enable Soft SPI driver. This driver is to use GPIO simulate > + the SPI protocol. If possible please write few lines about this thanks! -- Jagan Teki Free Software Engineer | www.openedev.com U-Boot, Linux | Upstream Maintainer Hyderabad, India. ^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH V2 07/12] spi: kconfig: add soft spi Kconfig entry 2017-05-03 6:06 ` Jagan Teki @ 2017-05-08 2:47 ` Peng Fan 0 siblings, 0 replies; 24+ messages in thread From: Peng Fan @ 2017-05-08 2:47 UTC (permalink / raw) To: u-boot On Wed, May 03, 2017 at 11:36:06AM +0530, Jagan Teki wrote: >On Thu, Apr 13, 2017 at 11:39 AM, Peng Fan <peng.fan@nxp.com> wrote: >> Add the Kconfig entry for SOFT_SPI which uses gpio to simulate the >> SPI signals. We use it for accessing 74x164 on some i.MX boards. >> >> Signed-off-by: Peng Fan <peng.fan@nxp.com> >> Cc: Jagan Teki <jagan@openedev.com> >> Cc: Stefano Babic <sbabic@denx.de> >> --- >> >> V2: >> None >> >> drivers/spi/Kconfig | 6 ++++++ >> 1 file changed, 6 insertions(+) >> >> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig >> index f3f7dbe..bef864f 100644 >> --- a/drivers/spi/Kconfig >> +++ b/drivers/spi/Kconfig >> @@ -197,6 +197,12 @@ config OMAP3_SPI >> >> endif # if DM_SPI >> >> +config SOFT_SPI >> + bool "Soft SPI driver" > >Did you move this for dm-driven file? since we've two files with same config This config is for dm and non-dm both. > >> + help >> + Enable Soft SPI driver. This driver is to use GPIO simulate >> + the SPI protocol. > >If possible please write few lines about this I understand this two line help message will trigger check patch warning, but I think this is clear to tell user what this option is. Thanks, Peng. > >thanks! >-- >Jagan Teki >Free Software Engineer | www.openedev.com >U-Boot, Linux | Upstream Maintainer >Hyderabad, India. >_______________________________________________ >U-Boot mailing list >U-Boot at lists.denx.de >https://lists.denx.de/listinfo/u-boot ^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH V2 08/12] gpio: 74x164: make oe-pins optional 2017-04-13 6:09 [U-Boot] [PATCH V2 01/12] arm: dts: imx7: sync with Linux Peng Fan ` (5 preceding siblings ...) 2017-04-13 6:09 ` [U-Boot] [PATCH V2 07/12] spi: kconfig: add soft spi Kconfig entry Peng Fan @ 2017-04-13 6:09 ` Peng Fan 2017-04-16 19:32 ` Simon Glass 2017-04-13 6:09 ` [U-Boot] [PATCH V2 09/12] imx: mx7dsabresd: enable more DM drivers Peng Fan ` (4 subsequent siblings) 11 siblings, 1 reply; 24+ messages in thread From: Peng Fan @ 2017-04-13 6:09 UTC (permalink / raw) To: u-boot Make oe-pins optional because some boards have fixed it to enable. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de> --- V2: None drivers/gpio/74x164_gpio.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpio/74x164_gpio.c b/drivers/gpio/74x164_gpio.c index 750eedf..53a639a 100644 --- a/drivers/gpio/74x164_gpio.c +++ b/drivers/gpio/74x164_gpio.c @@ -156,8 +156,7 @@ static int gen_74x164_probe(struct udevice *dev) ret = gpio_request_by_name(dev, "oe-gpios", 0, &priv->oe, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); if (ret) { - dev_err(dev, "No oe-pins property\n"); - goto free_buf; + dev_dbg(dev, "No oe-pins property\n"); } uc_priv->bank_name = str; -- 2.6.2 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH V2 08/12] gpio: 74x164: make oe-pins optional 2017-04-13 6:09 ` [U-Boot] [PATCH V2 08/12] gpio: 74x164: make oe-pins optional Peng Fan @ 2017-04-16 19:32 ` Simon Glass 0 siblings, 0 replies; 24+ messages in thread From: Simon Glass @ 2017-04-16 19:32 UTC (permalink / raw) To: u-boot On 13 April 2017 at 00:09, Peng Fan <peng.fan@nxp.com> wrote: > Make oe-pins optional because some boards have fixed it to enable. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > Cc: Simon Glass <sjg@chromium.org> > Cc: Stefano Babic <sbabic@denx.de> > --- > > V2: > None > > drivers/gpio/74x164_gpio.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) Reviewed-by: Simon Glass <sjg@chromium.org> ^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH V2 09/12] imx: mx7dsabresd: enable more DM drivers 2017-04-13 6:09 [U-Boot] [PATCH V2 01/12] arm: dts: imx7: sync with Linux Peng Fan ` (6 preceding siblings ...) 2017-04-13 6:09 ` [U-Boot] [PATCH V2 08/12] gpio: 74x164: make oe-pins optional Peng Fan @ 2017-04-13 6:09 ` Peng Fan 2017-05-18 8:46 ` Stefano Babic 2017-04-13 6:09 ` [U-Boot] [PATCH V2 10/12] imx: mx7dsabresd: reset ENET_RST_B Peng Fan ` (3 subsequent siblings) 11 siblings, 1 reply; 24+ messages in thread From: Peng Fan @ 2017-04-13 6:09 UTC (permalink / raw) To: u-boot Enable more DM drivers. The imx I2C/MMC DM drivers needs DM_GPIO enabled. The 74x164 drivers needs SOFT_SPI and DM_GPIO enabled. So needs to enable them together. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> --- V2: None board/freescale/mx7dsabresd/mx7dsabresd.c | 288 ++---------------------------- configs/mx7dsabresd_defconfig | 21 +++ include/configs/mx7dsabresd.h | 11 -- 3 files changed, 37 insertions(+), 283 deletions(-) diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c index 6ccdd4b..d6ba364 100644 --- a/board/freescale/mx7dsabresd/mx7dsabresd.c +++ b/board/freescale/mx7dsabresd/mx7dsabresd.c @@ -31,17 +31,11 @@ DECLARE_GLOBAL_DATA_PTR; #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) -#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ - PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) - #define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) #define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM) #define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) -#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ - PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM) - #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \ PAD_CTL_DSE_3P3V_49OHM) @@ -54,23 +48,8 @@ DECLARE_GLOBAL_DATA_PTR; (PAD_CTL_HYS | PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST) #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM) -#ifdef CONFIG_SYS_I2C_MXC -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -/* I2C1 for PMIC */ -static struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC, - .gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC, - .gp = IMX_GPIO_NR(4, 8), - }, - .sda = { - .i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC, - .gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC, - .gp = IMX_GPIO_NR(4, 9), - }, -}; -#endif +#ifdef CONFIG_MXC_SPI static iomux_v3_cfg_t const ecspi3_pads[] = { MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), @@ -87,6 +66,7 @@ static void setup_spi(void) { imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads)); } +#endif int dram_init(void) { @@ -104,34 +84,6 @@ static iomux_v3_cfg_t const uart1_pads[] = { MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), }; -static iomux_v3_cfg_t const usdhc1_pads[] = { - MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - - MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), -}; - -static iomux_v3_cfg_t const usdhc3_emmc_pads[] = { - MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL), - - MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL), -}; - static iomux_v3_cfg_t const usb_otg1_pads[] = { MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), }; @@ -140,94 +92,6 @@ static iomux_v3_cfg_t const usb_otg2_pads[] = { MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), }; -#define IOX_SDI IMX_GPIO_NR(1, 9) -#define IOX_STCP IMX_GPIO_NR(1, 12) -#define IOX_SHCP IMX_GPIO_NR(1, 13) - -static iomux_v3_cfg_t const iox_pads[] = { - /* IOX_SDI */ - MX7D_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* IOX_STCP */ - MX7D_PAD_GPIO1_IO12__GPIO1_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* IOX_SHCP */ - MX7D_PAD_GPIO1_IO13__GPIO1_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -/* - * PCIE_DIS_B --> Q0 - * PCIE_RST_B --> Q1 - * HDMI_RST_B --> Q2 - * PERI_RST_B --> Q3 - * SENSOR_RST_B --> Q4 - * ENET_RST_B --> Q5 - * PERI_3V3_EN --> Q6 - * LCD_PWR_EN --> Q7 - */ -enum qn { - PCIE_DIS_B, - PCIE_RST_B, - HDMI_RST_B, - PERI_RST_B, - SENSOR_RST_B, - ENET_RST_B, - PERI_3V3_EN, - LCD_PWR_EN, -}; - -enum qn_func { - qn_reset, - qn_enable, - qn_disable, -}; - -enum qn_level { - qn_low = 0, - qn_high = 1, -}; - -static enum qn_level seq[3][2] = { - {0, 1}, {1, 1}, {0, 0} -}; - -static enum qn_func qn_output[8] = { - qn_disable, qn_reset, qn_reset, qn_reset, qn_reset, qn_reset, qn_enable, - qn_disable -}; - -static void iox74lv_init(void) -{ - int i; - - for (i = 7; i >= 0; i--) { - gpio_direction_output(IOX_SHCP, 0); - gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]); - udelay(500); - gpio_direction_output(IOX_SHCP, 1); - udelay(500); - } - - gpio_direction_output(IOX_STCP, 0); - udelay(500); - /* - * shift register will be output to pins - */ - gpio_direction_output(IOX_STCP, 1); - - for (i = 7; i >= 0; i--) { - gpio_direction_output(IOX_SHCP, 0); - gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); - udelay(500); - gpio_direction_output(IOX_SHCP, 1); - udelay(500); - } - gpio_direction_output(IOX_STCP, 0); - udelay(500); - /* - * shift register will be output to pins - */ - gpio_direction_output(IOX_STCP, 1); -}; - #ifdef CONFIG_NAND_MXS static iomux_v3_cfg_t const gpmi_pads[] = { MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), @@ -306,11 +170,13 @@ static int setup_lcd(void) imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads)); /* Reset LCD */ + gpio_request(IMX_GPIO_NR(3, 4), "lcd reset"); gpio_direction_output(IMX_GPIO_NR(3, 4) , 0); udelay(500); gpio_direction_output(IMX_GPIO_NR(3, 4) , 1); /* Set Brightness to high */ + gpio_request(IMX_GPIO_NR(1, 1), "lcd backlight"); gpio_direction_output(IMX_GPIO_NR(1, 1) , 1); return 0; @@ -346,17 +212,6 @@ static void setup_iomux_uart(void) imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } -#ifdef CONFIG_FSL_ESDHC - -#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0) -#define USDHC1_PWR_GPIO IMX_GPIO_NR(5, 2) -#define USDHC3_PWR_GPIO IMX_GPIO_NR(6, 11) - -static struct fsl_esdhc_cfg usdhc_cfg[3] = { - {USDHC1_BASE_ADDR, 0, 4}, - {USDHC3_BASE_ADDR}, -}; - int board_mmc_get_env_dev(int devno) { if (devno == 2) @@ -365,7 +220,7 @@ int board_mmc_get_env_dev(int devno) return devno; } -static int mmc_map_to_kernel_blk(int dev_no) +int mmc_map_to_kernel_blk(int dev_no) { if (dev_no == 1) dev_no++; @@ -373,102 +228,6 @@ static int mmc_map_to_kernel_blk(int dev_no) return dev_no; } -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC1_BASE_ADDR: - ret = !gpio_get_value(USDHC1_CD_GPIO); - break; - case USDHC3_BASE_ADDR: - ret = 1; /* Assume uSDHC3 emmc is always present */ - break; - } - - return ret; -} - -int board_mmc_init(bd_t *bis) -{ - int i, ret; - /* - * According to the board_mmc_init() the following map is done: - * (U-Boot device node) (Physical Port) - * mmc0 USDHC1 - * mmc2 USDHC3 (eMMC) - */ - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { - switch (i) { - case 0: - imx_iomux_v3_setup_multiple_pads( - usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); - gpio_request(USDHC1_CD_GPIO, "usdhc1_cd"); - gpio_direction_input(USDHC1_CD_GPIO); - gpio_request(USDHC1_PWR_GPIO, "usdhc1_pwr"); - gpio_direction_output(USDHC1_PWR_GPIO, 0); - udelay(500); - gpio_direction_output(USDHC1_PWR_GPIO, 1); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - break; - case 1: - imx_iomux_v3_setup_multiple_pads( - usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads)); - gpio_request(USDHC3_PWR_GPIO, "usdhc3_pwr"); - gpio_direction_output(USDHC3_PWR_GPIO, 0); - udelay(500); - gpio_direction_output(USDHC3_PWR_GPIO, 1); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - break; - default: - printf("Warning: you configured more USDHC controllers" - "(%d) than supported by the board\n", i + 1); - return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); - if (ret) - return ret; - } - - return 0; -} - -static int check_mmc_autodetect(void) -{ - char *autodetect_str = getenv("mmcautodetect"); - - if ((autodetect_str != NULL) && - (strcmp(autodetect_str, "yes") == 0)) { - return 1; - } - - return 0; -} - -static void mmc_late_init(void) -{ - char cmd[32]; - char mmcblk[32]; - u32 dev_no = mmc_get_env_dev(); - - if (!check_mmc_autodetect()) - return; - - setenv_ulong("mmcdev", dev_no); - - /* Set mmcblk env */ - sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", - mmc_map_to_kernel_blk(dev_no)); - setenv("mmcroot", mmcblk); - - sprintf(cmd, "mmc dev %d", dev_no); - run_command(cmd, 0); -} - -#endif - #ifdef CONFIG_FEC_MXC int board_eth_init(bd_t *bis) { @@ -539,7 +298,6 @@ int board_early_init_f(void) { setup_iomux_uart(); - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); imx_iomux_v3_setup_multiple_pads(usb_otg1_pads, ARRAY_SIZE(usb_otg1_pads)); imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, @@ -553,10 +311,6 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads)); - - iox74lv_init(); - #ifdef CONFIG_FEC_MXC setup_fec(); #endif @@ -580,29 +334,23 @@ int board_init(void) return 0; } -#ifdef CONFIG_POWER -#define I2C_PMIC 0 +#ifdef CONFIG_DM_PMIC int power_init_board(void) { - struct pmic *p; - int ret; - unsigned int reg, rev_id; + struct udevice *dev; + int ret, dev_id, rev_id; - ret = power_pfuze3000_init(I2C_PMIC); - if (ret) + ret = pmic_get("pfuze3000", &dev); + if (ret == -ENODEV) + return 0; + if (ret != 0) return ret; - p = pmic_get("PFUZE3000"); - ret = pmic_probe(p); - if (ret) - return ret; - - pmic_reg_read(p, PFUZE3000_DEVICEID, ®); - pmic_reg_read(p, PFUZE3000_REVID, &rev_id); - printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); + dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE3000_REVID); + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); - /* disable Low Power Mode during standby mode */ - pmic_reg_write(p, PFUZE3000_LDOGCTL, 0x1); + pmic_clrsetbits(dev, PFUZE3000_LDOGCTL, 0, 1); return 0; } @@ -612,10 +360,6 @@ int board_late_init(void) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; -#ifdef CONFIG_ENV_IS_IN_MMC - mmc_late_init(); -#endif - imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); set_wdog_reset(wdog); diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig index 5bdc638..7ab65dc 100644 --- a/configs/mx7dsabresd_defconfig +++ b/configs/mx7dsabresd_defconfig @@ -29,13 +29,33 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y +# CONFIG_BLK is not set CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +# CONFIG_DM_MMC_OPS is not set +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SPI=y +CONFIG_SOFT_SPI=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_MXC_USB_OTG_HACTIVE=y @@ -46,3 +66,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="FSL" CONFIG_G_DNL_VENDOR_NUM=0x0525 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 +CONFIG_ERRNO_STR=y diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index 81d769f..840a220 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -34,20 +34,12 @@ /* MMC Config*/ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 -/* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_PFUZE3000 -#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 - #undef CONFIG_BOOTM_NETBSD #undef CONFIG_BOOTM_PLAN9 #undef CONFIG_BOOTM_RTEMS /* I2C configs */ -#define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ @@ -197,9 +189,6 @@ #define CONFIG_ENV_SIZE SZ_8K #define CONFIG_ENV_IS_IN_MMC -/* MXC SPI driver support */ -#define CONFIG_MXC_SPI - /* * If want to use nand, define CONFIG_NAND_MXS and rework board * to support nand, since emmc has pin conflicts with nand -- 2.6.2 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH V2 09/12] imx: mx7dsabresd: enable more DM drivers 2017-04-13 6:09 ` [U-Boot] [PATCH V2 09/12] imx: mx7dsabresd: enable more DM drivers Peng Fan @ 2017-05-18 8:46 ` Stefano Babic 0 siblings, 0 replies; 24+ messages in thread From: Stefano Babic @ 2017-05-18 8:46 UTC (permalink / raw) To: u-boot Hi Peng, On 13/04/2017 08:09, Peng Fan wrote: > Enable more DM drivers. The imx I2C/MMC DM drivers needs DM_GPIO > enabled. The 74x164 drivers needs SOFT_SPI and DM_GPIO enabled. > So needs to enable them together. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > Cc: Stefano Babic <sbabic@denx.de> > --- > > V2: > None > > board/freescale/mx7dsabresd/mx7dsabresd.c | 288 ++---------------------------- > configs/mx7dsabresd_defconfig | 21 +++ This does not patch mx7dsabresd_secure_defconfig, that results then broken. I have just fixed in my local branch and I send a patch for it (I can just test build). Regards, Stefano -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH V2 10/12] imx: mx7dsabresd: reset ENET_RST_B 2017-04-13 6:09 [U-Boot] [PATCH V2 01/12] arm: dts: imx7: sync with Linux Peng Fan ` (7 preceding siblings ...) 2017-04-13 6:09 ` [U-Boot] [PATCH V2 09/12] imx: mx7dsabresd: enable more DM drivers Peng Fan @ 2017-04-13 6:09 ` Peng Fan 2017-04-13 6:09 ` [U-Boot] [PATCH V2 11/12] imx: mx7dsabresd: switch to DM USB Peng Fan ` (2 subsequent siblings) 11 siblings, 0 replies; 24+ messages in thread From: Peng Fan @ 2017-04-13 6:09 UTC (permalink / raw) To: u-boot Reset ENET_RST_B to make ENET function stable. Since DM_GPIO enabled, we use "gpio_spi at 0_5" which corresponds to ENET_RST_B. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> --- V2: None board/freescale/mx7dsabresd/mx7dsabresd.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c index d6ba364..f7a5f0d 100644 --- a/board/freescale/mx7dsabresd/mx7dsabresd.c +++ b/board/freescale/mx7dsabresd/mx7dsabresd.c @@ -232,6 +232,23 @@ int mmc_map_to_kernel_blk(int dev_no) int board_eth_init(bd_t *bis) { int ret; + unsigned int gpio; + + ret = gpio_lookup_name("gpio_spi at 0_5", NULL, NULL, &gpio); + if (ret) { + printf("GPIO: 'gpio_spi at 0_5' not found\n"); + return -ENODEV; + } + + ret = gpio_request(gpio, "fec_rst"); + if (ret && ret != -EBUSY) { + printf("gpio: requesting pin %u failed\n", gpio); + return ret; + } + + gpio_direction_output(gpio, 0); + udelay(500); + gpio_direction_output(gpio, 1); setup_iomux_fec(); -- 2.6.2 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH V2 11/12] imx: mx7dsabresd: switch to DM USB 2017-04-13 6:09 [U-Boot] [PATCH V2 01/12] arm: dts: imx7: sync with Linux Peng Fan ` (8 preceding siblings ...) 2017-04-13 6:09 ` [U-Boot] [PATCH V2 10/12] imx: mx7dsabresd: reset ENET_RST_B Peng Fan @ 2017-04-13 6:09 ` Peng Fan 2017-04-13 6:10 ` [U-Boot] [PATCH V2 12/12] imx: mx7dsabresd: add board revision check Peng Fan 2017-05-11 11:35 ` [U-Boot] [PATCH V2 01/12] arm: dts: imx7: sync with Linux Stefano Babic 11 siblings, 0 replies; 24+ messages in thread From: Peng Fan @ 2017-04-13 6:09 UTC (permalink / raw) To: u-boot Switch to use DM USB. Signed-off-by: Peng Fan <peng.fan@nxp.com> --- board/freescale/mx7dsabresd/mx7dsabresd.c | 25 ------------------------- configs/mx7dsabresd_defconfig | 1 + include/configs/mx7dsabresd.h | 3 --- 3 files changed, 1 insertion(+), 28 deletions(-) diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c index f7a5f0d..ecea5a5 100644 --- a/board/freescale/mx7dsabresd/mx7dsabresd.c +++ b/board/freescale/mx7dsabresd/mx7dsabresd.c @@ -23,8 +23,6 @@ #include <i2c.h> #include <asm/imx-common/mxc_i2c.h> #include <asm/arch/crm_regs.h> -#include <usb.h> -#include <usb/ehci-ci.h> DECLARE_GLOBAL_DATA_PTR; @@ -84,14 +82,6 @@ static iomux_v3_cfg_t const uart1_pads[] = { MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), }; -static iomux_v3_cfg_t const usb_otg1_pads[] = { - MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static iomux_v3_cfg_t const usb_otg2_pads[] = { - MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - #ifdef CONFIG_NAND_MXS static iomux_v3_cfg_t const gpmi_pads[] = { MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), @@ -315,11 +305,6 @@ int board_early_init_f(void) { setup_iomux_uart(); - imx_iomux_v3_setup_multiple_pads(usb_otg1_pads, - ARRAY_SIZE(usb_otg1_pads)); - imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, - ARRAY_SIZE(usb_otg2_pads)); - return 0; } @@ -403,13 +388,3 @@ int checkboard(void) return 0; } - -#ifdef CONFIG_USB_EHCI_MX7 -int board_usb_phy_mode(int port) -{ - if (port == 0) - return USB_INIT_DEVICE; - else - return USB_INIT_HOST; -} -#endif diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig index 7ab65dc..2405dd1 100644 --- a/configs/mx7dsabresd_defconfig +++ b/configs/mx7dsabresd_defconfig @@ -57,6 +57,7 @@ CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SPI=y CONFIG_SOFT_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_MXC_USB_OTG_HACTIVE=y CONFIG_USB_STORAGE=y diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index 840a220..41a6006 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -221,12 +221,9 @@ #define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ /* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_IMX_THERMAL -- 2.6.2 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH V2 12/12] imx: mx7dsabresd: add board revision check 2017-04-13 6:09 [U-Boot] [PATCH V2 01/12] arm: dts: imx7: sync with Linux Peng Fan ` (9 preceding siblings ...) 2017-04-13 6:09 ` [U-Boot] [PATCH V2 11/12] imx: mx7dsabresd: switch to DM USB Peng Fan @ 2017-04-13 6:10 ` Peng Fan 2017-04-17 15:00 ` Fabio Estevam 2017-05-11 11:35 ` [U-Boot] [PATCH V2 01/12] arm: dts: imx7: sync with Linux Stefano Babic 11 siblings, 1 reply; 24+ messages in thread From: Peng Fan @ 2017-04-13 6:10 UTC (permalink / raw) To: u-boot Add board revision check Signed-off-by: Peng Fan <peng.fan@nxp.com> --- board/freescale/mx7dsabresd/mx7dsabresd.c | 59 ++++++++++++++++++++++++++++++- 1 file changed, 58 insertions(+), 1 deletion(-) diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c index ecea5a5..07392fa 100644 --- a/board/freescale/mx7dsabresd/mx7dsabresd.c +++ b/board/freescale/mx7dsabresd/mx7dsabresd.c @@ -82,6 +82,48 @@ static iomux_v3_cfg_t const uart1_pads[] = { MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), }; +#define BOARD_REV_C 0x300 +#define BOARD_REV_B 0x200 +#define BOARD_REV_A 0x100 + +static int mx7sabre_rev(void) +{ + /* + * Get Board ID information from OCOTP_GP1[15:8] + * i.MX7D SDB RevA: 0x41 + * i.MX7D SDB RevB: 0x42 + */ + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[14]; + int reg = readl(&bank->fuse_regs[0]); + int ret; + + if (reg != 0) { + switch (reg >> 8 & 0x0F) { + case 0x3: + ret = BOARD_REV_C; + break; + case 0x02: + ret = BOARD_REV_B; + break; + case 0x01: + default: + ret = BOARD_REV_A; + break; + } + } else { + /* If the gp1 fuse is not burn, we have to use TO rev for the board rev */ + if (is_soc_rev(CHIP_REV_1_0)) + ret = BOARD_REV_A; + else if (is_soc_rev(CHIP_REV_1_1)) + ret = BOARD_REV_B; + else + ret = BOARD_REV_C; + } + + return ret; +} + #ifdef CONFIG_NAND_MXS static iomux_v3_cfg_t const gpmi_pads[] = { MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), @@ -377,14 +419,29 @@ int board_late_init(void) int checkboard(void) { + int rev = mx7sabre_rev(); char *mode; + char *revname; if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT)) mode = "secure"; else mode = "non-secure"; - printf("Board: i.MX7D SABRESD in %s mode\n", mode); + switch (rev) { + case BOARD_REV_C: + revname = "C"; + break; + case BOARD_REV_B: + revname = "B"; + break; + case BOARD_REV_A: + default: + revname = "A"; + break; + } + + printf("Board: i.MX7D SABRESD Rev%s in %s mode\n", revname, mode); return 0; } -- 2.6.2 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH V2 12/12] imx: mx7dsabresd: add board revision check 2017-04-13 6:10 ` [U-Boot] [PATCH V2 12/12] imx: mx7dsabresd: add board revision check Peng Fan @ 2017-04-17 15:00 ` Fabio Estevam 2017-04-18 0:54 ` Peng Fan 0 siblings, 1 reply; 24+ messages in thread From: Fabio Estevam @ 2017-04-17 15:00 UTC (permalink / raw) To: u-boot On Thu, Apr 13, 2017 at 3:10 AM, Peng Fan <peng.fan@nxp.com> wrote: > +#define BOARD_REV_C 0x300 > +#define BOARD_REV_B 0x200 > +#define BOARD_REV_A 0x100 > + > +static int mx7sabre_rev(void) > +{ > + /* > + * Get Board ID information from OCOTP_GP1[15:8] > + * i.MX7D SDB RevA: 0x41 > + * i.MX7D SDB RevB: 0x42 Isn't this versioning scheme shared with other NXP boards? If so, it would be better to put this in common code. ^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH V2 12/12] imx: mx7dsabresd: add board revision check 2017-04-17 15:00 ` Fabio Estevam @ 2017-04-18 0:54 ` Peng Fan 2017-05-11 11:33 ` Stefano Babic 2017-05-18 8:19 ` Stefano Babic 0 siblings, 2 replies; 24+ messages in thread From: Peng Fan @ 2017-04-18 0:54 UTC (permalink / raw) To: u-boot Hi Fabio, > -----Original Message----- > From: Fabio Estevam [mailto:festevam at gmail.com] > Sent: Monday, April 17, 2017 11:00 PM > To: Peng Fan <peng.fan@nxp.com> > Cc: Stefano Babic <sbabic@denx.de>; U-Boot-Denx <u-boot@lists.denx.de> > Subject: Re: [U-Boot] [PATCH V2 12/12] imx: mx7dsabresd: add board revision > check > > On Thu, Apr 13, 2017 at 3:10 AM, Peng Fan <peng.fan@nxp.com> wrote: > > > +#define BOARD_REV_C 0x300 > > +#define BOARD_REV_B 0x200 > > +#define BOARD_REV_A 0x100 > > + > > +static int mx7sabre_rev(void) > > +{ > > + /* > > + * Get Board ID information from OCOTP_GP1[15:8] > > + * i.MX7D SDB RevA: 0x41 > > + * i.MX7D SDB RevB: 0x42 > > Isn't this versioning scheme shared with other NXP boards? If so, it would be > better to put this in common code. I prefer to keep the code here. There are board revision fuse for the boards from NXP, but this is not always true, I think. Thanks, Peng. ^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH V2 12/12] imx: mx7dsabresd: add board revision check 2017-04-18 0:54 ` Peng Fan @ 2017-05-11 11:33 ` Stefano Babic 2017-05-11 12:52 ` Peng Fan 2017-05-18 8:19 ` Stefano Babic 1 sibling, 1 reply; 24+ messages in thread From: Stefano Babic @ 2017-05-11 11:33 UTC (permalink / raw) To: u-boot Hi Peng, On 18/04/2017 02:54, Peng Fan wrote: > Hi Fabio, > >> -----Original Message----- >> From: Fabio Estevam [mailto:festevam at gmail.com] >> Sent: Monday, April 17, 2017 11:00 PM >> To: Peng Fan <peng.fan@nxp.com> >> Cc: Stefano Babic <sbabic@denx.de>; U-Boot-Denx <u-boot@lists.denx.de> >> Subject: Re: [U-Boot] [PATCH V2 12/12] imx: mx7dsabresd: add board revision >> check >> >> On Thu, Apr 13, 2017 at 3:10 AM, Peng Fan <peng.fan@nxp.com> wrote: >> >>> +#define BOARD_REV_C 0x300 >>> +#define BOARD_REV_B 0x200 >>> +#define BOARD_REV_A 0x100 >>> + >>> +static int mx7sabre_rev(void) >>> +{ >>> + /* >>> + * Get Board ID information from OCOTP_GP1[15:8] >>> + * i.MX7D SDB RevA: 0x41 >>> + * i.MX7D SDB RevB: 0x42 >> >> Isn't this versioning scheme shared with other NXP boards? If so, it would be >> better to put this in common code. > > I prefer to keep the code here. There are board revision fuse for the boards from NXP, but > this is not always true, I think. Anyway, there is "quite" same code for mx6 sabre: static int mx6sabre_rev(void) { /* * Get Board ID information from OCOTP_GP1[15:8] * i.MX6Q ARD RevA: 0x01 * i.MX6Q ARD RevB: 0x02 */ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; struct fuse_bank *bank = &ocotp->bank[4]; struct fuse_bank4_regs *fuse = (struct fuse_bank4_regs *)bank->fuse_regs; int reg = readl(&fuse->gp1); int ret; switch (reg >> 8 & 0x0F) { case 0x02: ret = BOARD_REV_B; break; case 0x01: default: And the version number is simple an integer and we do not need to add defines - if we simply returns the read value (1,2,3,..), the code works even with future versions. Are you sure that this is not at least "sabre common code " ? Regards, Stefano -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH V2 12/12] imx: mx7dsabresd: add board revision check 2017-05-11 11:33 ` Stefano Babic @ 2017-05-11 12:52 ` Peng Fan 0 siblings, 0 replies; 24+ messages in thread From: Peng Fan @ 2017-05-11 12:52 UTC (permalink / raw) To: u-boot Hi Stefano, > -----Original Message----- > From: Stefano Babic [mailto:sbabic at denx.de] > Sent: Thursday, May 11, 2017 7:33 PM > To: Peng Fan <peng.fan@nxp.com>; Fabio Estevam <festevam@gmail.com> > Cc: Stefano Babic <sbabic@denx.de>; U-Boot-Denx <u-boot@lists.denx.de> > Subject: Re: [U-Boot] [PATCH V2 12/12] imx: mx7dsabresd: add board revision > check > > Hi Peng, > > On 18/04/2017 02:54, Peng Fan wrote: > > Hi Fabio, > > > >> -----Original Message----- > >> From: Fabio Estevam [mailto:festevam at gmail.com] > >> Sent: Monday, April 17, 2017 11:00 PM > >> To: Peng Fan <peng.fan@nxp.com> > >> Cc: Stefano Babic <sbabic@denx.de>; U-Boot-Denx > >> <u-boot@lists.denx.de> > >> Subject: Re: [U-Boot] [PATCH V2 12/12] imx: mx7dsabresd: add board > >> revision check > >> > >> On Thu, Apr 13, 2017 at 3:10 AM, Peng Fan <peng.fan@nxp.com> wrote: > >> > >>> +#define BOARD_REV_C 0x300 > >>> +#define BOARD_REV_B 0x200 > >>> +#define BOARD_REV_A 0x100 > >>> + > >>> +static int mx7sabre_rev(void) > >>> +{ > >>> + /* > >>> + * Get Board ID information from OCOTP_GP1[15:8] > >>> + * i.MX7D SDB RevA: 0x41 > >>> + * i.MX7D SDB RevB: 0x42 > >> > >> Isn't this versioning scheme shared with other NXP boards? If so, it > >> would be better to put this in common code. > > > > I prefer to keep the code here. There are board revision fuse for the > > boards from NXP, but this is not always true, I think. > > Anyway, there is "quite" same code for mx6 sabre: > > static int mx6sabre_rev(void) > { > /* > * Get Board ID information from OCOTP_GP1[15:8] > * i.MX6Q ARD RevA: 0x01 > * i.MX6Q ARD RevB: 0x02 > */ > struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; > struct fuse_bank *bank = &ocotp->bank[4]; > struct fuse_bank4_regs *fuse = > (struct fuse_bank4_regs *)bank->fuse_regs; > int reg = readl(&fuse->gp1); > int ret; > > switch (reg >> 8 & 0x0F) { > case 0x02: > ret = BOARD_REV_B; > break; > case 0x01: > default: > > And the version number is simple an integer and we do not need to add > defines - if we simply returns the read value (1,2,3,..), the code works even > with future versions. Are you sure that this is not at least "sabre common code > " ? Could I use a follow up patch to move the revision check to a common place? I would not send a whole V3 patch set if no more comments. Thanks, Peng. > > Regards, > Stefano > > -- > ============================================================ > ========= > DENX Software Engineering GmbH, Managing Director: Wolfgang Denk > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany > Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de > ============================================================ > ========= ^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH V2 12/12] imx: mx7dsabresd: add board revision check 2017-04-18 0:54 ` Peng Fan 2017-05-11 11:33 ` Stefano Babic @ 2017-05-18 8:19 ` Stefano Babic 2017-05-18 8:51 ` Peng Fan 1 sibling, 1 reply; 24+ messages in thread From: Stefano Babic @ 2017-05-18 8:19 UTC (permalink / raw) To: u-boot Hi Peng, On 18/04/2017 02:54, Peng Fan wrote: > Hi Fabio, > >> -----Original Message----- >> From: Fabio Estevam [mailto:festevam at gmail.com] >> Sent: Monday, April 17, 2017 11:00 PM >> To: Peng Fan <peng.fan@nxp.com> >> Cc: Stefano Babic <sbabic@denx.de>; U-Boot-Denx <u-boot@lists.denx.de> >> Subject: Re: [U-Boot] [PATCH V2 12/12] imx: mx7dsabresd: add board revision >> check >> >> On Thu, Apr 13, 2017 at 3:10 AM, Peng Fan <peng.fan@nxp.com> wrote: >> >>> +#define BOARD_REV_C 0x300 >>> +#define BOARD_REV_B 0x200 >>> +#define BOARD_REV_A 0x100 >>> + >>> +static int mx7sabre_rev(void) >>> +{ >>> + /* >>> + * Get Board ID information from OCOTP_GP1[15:8] >>> + * i.MX7D SDB RevA: 0x41 >>> + * i.MX7D SDB RevB: 0x42 >> >> Isn't this versioning scheme shared with other NXP boards? If so, it would be >> better to put this in common code. > > I prefer to keep the code here. There are board revision fuse for the boards from NXP, but > this is not always true, I think. > Patches 1..11 are free of comments. I am merging them and I will send PR to Tom for inclusion after my build test. I will just let this last one out. Regards, Stefano -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH V2 12/12] imx: mx7dsabresd: add board revision check 2017-05-18 8:19 ` Stefano Babic @ 2017-05-18 8:51 ` Peng Fan 2017-05-18 9:00 ` Stefano Babic 0 siblings, 1 reply; 24+ messages in thread From: Peng Fan @ 2017-05-18 8:51 UTC (permalink / raw) To: u-boot > -----Original Message----- > From: Stefano Babic [mailto:sbabic at denx.de] > Sent: Thursday, May 18, 2017 4:20 PM > To: Peng Fan <peng.fan@nxp.com>; Fabio Estevam <festevam@gmail.com> > Cc: Stefano Babic <sbabic@denx.de>; U-Boot-Denx <u-boot@lists.denx.de> > Subject: Re: [U-Boot] [PATCH V2 12/12] imx: mx7dsabresd: add board revision > check > > Hi Peng, Hi Stefano, > > On 18/04/2017 02:54, Peng Fan wrote: > > Hi Fabio, > > > >> -----Original Message----- > >> From: Fabio Estevam [mailto:festevam at gmail.com] > >> Sent: Monday, April 17, 2017 11:00 PM > >> To: Peng Fan <peng.fan@nxp.com> > >> Cc: Stefano Babic <sbabic@denx.de>; U-Boot-Denx > >> <u-boot@lists.denx.de> > >> Subject: Re: [U-Boot] [PATCH V2 12/12] imx: mx7dsabresd: add board > >> revision check > >> > >> On Thu, Apr 13, 2017 at 3:10 AM, Peng Fan <peng.fan@nxp.com> wrote: > >> > >>> +#define BOARD_REV_C 0x300 > >>> +#define BOARD_REV_B 0x200 > >>> +#define BOARD_REV_A 0x100 > >>> + > >>> +static int mx7sabre_rev(void) > >>> +{ > >>> + /* > >>> + * Get Board ID information from OCOTP_GP1[15:8] > >>> + * i.MX7D SDB RevA: 0x41 > >>> + * i.MX7D SDB RevB: 0x42 > >> > >> Isn't this versioning scheme shared with other NXP boards? If so, it > >> would be better to put this in common code. > > > > I prefer to keep the code here. There are board revision fuse for the > > boards from NXP, but this is not always true, I think. > > > > Patches 1..11 are free of comments. I am merging them and I will send PR to > Tom for inclusion after my build test. I will just let this last one out. It is ok for me to let this out. Thanks. Thanks, Peng. > > Regards, > Stefano > > > -- > ============================================================ > ========= > DENX Software Engineering GmbH, Managing Director: Wolfgang Denk > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany > Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de > ============================================================ > ========= ^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH V2 12/12] imx: mx7dsabresd: add board revision check 2017-05-18 8:51 ` Peng Fan @ 2017-05-18 9:00 ` Stefano Babic 0 siblings, 0 replies; 24+ messages in thread From: Stefano Babic @ 2017-05-18 9:00 UTC (permalink / raw) To: u-boot On 18/05/2017 10:51, Peng Fan wrote: >> Patches 1..11 are free of comments. I am merging them and I will send PR to >> Tom for inclusion after my build test. I will just let this last one out. > > It is ok for me to let this out. Thanks. ok - just check with patch I send today to fix the "secure" variant, then I could insert this to my PR. Thanks, Stefano -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH V2 01/12] arm: dts: imx7: sync with Linux 2017-04-13 6:09 [U-Boot] [PATCH V2 01/12] arm: dts: imx7: sync with Linux Peng Fan ` (10 preceding siblings ...) 2017-04-13 6:10 ` [U-Boot] [PATCH V2 12/12] imx: mx7dsabresd: add board revision check Peng Fan @ 2017-05-11 11:35 ` Stefano Babic 11 siblings, 0 replies; 24+ messages in thread From: Stefano Babic @ 2017-05-11 11:35 UTC (permalink / raw) To: u-boot On 13/04/2017 08:09, Peng Fan wrote: > Sync with Linux commit 308ac756("Merge tag 'gpio-v4.11-3'"). > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > Cc: Stefan Agner <stefan.agner@toradex.com> > Cc: Stefano Babic <sbabic@denx.de> > --- > > V2: > remove imx7.dtsi Reviewed-by: Stefano Babic <sbabic@denx.de> Regards, Stefano > > arch/arm/dts/imx7-colibri.dts | 10 +- > arch/arm/dts/imx7.dtsi | 194 ------- > arch/arm/dts/imx7d-pinfunc.h | 111 ++-- > arch/arm/dts/imx7d.dtsi | 140 +++++ > arch/arm/dts/imx7s.dtsi | 999 ++++++++++++++++++++++++++++++++ > include/dt-bindings/clock/imx7d-clock.h | 454 +++++++++++++++ > 6 files changed, 1657 insertions(+), 251 deletions(-) > delete mode 100644 arch/arm/dts/imx7.dtsi > create mode 100644 arch/arm/dts/imx7d.dtsi > create mode 100644 arch/arm/dts/imx7s.dtsi > create mode 100644 include/dt-bindings/clock/imx7d-clock.h > > diff --git a/arch/arm/dts/imx7-colibri.dts b/arch/arm/dts/imx7-colibri.dts > index cbef5d5..f6c2105 100644 > --- a/arch/arm/dts/imx7-colibri.dts > +++ b/arch/arm/dts/imx7-colibri.dts > @@ -6,7 +6,7 @@ > > /dts-v1/; > #include <dt-bindings/gpio/gpio.h> > -#include "imx7.dtsi" > +#include "imx7d.dtsi" > > / { > model = "Toradex Colibri iMX7S/D"; > @@ -83,15 +83,15 @@ > &iomuxc_lpsr { > pinctrl_i2c1: i2c1-grp { > fsl,pins = < > - MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x4000007f > - MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x4000007f > + MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x4000007f > + MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x4000007f > >; > }; > > pinctrl_i2c1_gpio: i2c1-gpio-grp { > fsl,pins = < > - MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x4000007f > - MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x4000007f > + MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x4000007f > + MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x4000007f > >; > }; > }; > diff --git a/arch/arm/dts/imx7.dtsi b/arch/arm/dts/imx7.dtsi > deleted file mode 100644 > index 755cc46..0000000 > --- a/arch/arm/dts/imx7.dtsi > +++ /dev/null > @@ -1,194 +0,0 @@ > -/* > - * Copyright 2016 Toradex AG > - * > - * SPDX-License-Identifier: GPL-2.0+ or X11 > - */ > -#include "imx7d-pinfunc.h" > -#include "skeleton.dtsi" > - > -/ { > - aliases { > - gpio0 = &gpio1; > - gpio1 = &gpio2; > - gpio2 = &gpio3; > - gpio3 = &gpio4; > - gpio4 = &gpio5; > - gpio5 = &gpio6; > - gpio6 = &gpio7; > - i2c0 = &i2c1; > - i2c1 = &i2c2; > - i2c2 = &i2c3; > - i2c3 = &i2c4; > - serial0 = &uart1; > - serial1 = &uart2; > - serial2 = &uart3; > - serial3 = &uart4; > - serial4 = &uart5; > - serial5 = &uart6; > - serial6 = &uart7; > - }; > - > - soc { > - #address-cells = <1>; > - #size-cells = <1>; > - compatible = "simple-bus"; > - ranges; > - > - aips1: aips-bus at 30000000 { > - compatible = "fsl,aips-bus", "simple-bus"; > - #address-cells = <1>; > - #size-cells = <1>; > - reg = <0x30000000 0x400000>; > - ranges; > - > - gpio1: gpio at 30200000 { > - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; > - reg = <0x30200000 0x10000>; > - gpio-controller; > - #gpio-cells = <2>; > - }; > - > - gpio2: gpio at 30210000 { > - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; > - reg = <0x30210000 0x10000>; > - gpio-controller; > - #gpio-cells = <2>; > - }; > - > - gpio3: gpio at 30220000 { > - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; > - reg = <0x30220000 0x10000>; > - gpio-controller; > - #gpio-cells = <2>; > - }; > - > - gpio4: gpio at 30230000 { > - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; > - reg = <0x30230000 0x10000>; > - gpio-controller; > - #gpio-cells = <2>; > - }; > - > - gpio5: gpio at 30240000 { > - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; > - reg = <0x30240000 0x10000>; > - gpio-controller; > - #gpio-cells = <2>; > - }; > - > - gpio6: gpio at 30250000 { > - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; > - reg = <0x30250000 0x10000>; > - gpio-controller; > - #gpio-cells = <2>; > - }; > - > - gpio7: gpio at 30260000 { > - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; > - reg = <0x30260000 0x10000>; > - gpio-controller; > - #gpio-cells = <2>; > - }; > - > - iomuxc_lpsr: iomuxc-lpsr at 302c0000 { > - compatible = "fsl,imx7d-iomuxc-lpsr"; > - reg = <0x302c0000 0x10000>; > - fsl,input-sel = <&iomuxc>; > - }; > - > - iomuxc: iomuxc at 30330000 { > - compatible = "fsl,imx7d-iomuxc"; > - reg = <0x30330000 0x10000>; > - }; > - }; > - > - aips3: aips-bus at 30800000 { > - compatible = "fsl,aips-bus", "simple-bus"; > - #address-cells = <1>; > - #size-cells = <1>; > - reg = <0x30800000 0x400000>; > - ranges; > - > - uart1: serial at 30860000 { > - compatible = "fsl,imx7d-uart", > - "fsl,imx6q-uart"; > - reg = <0x30860000 0x10000>; > - status = "disabled"; > - }; > - > - uart2: serial at 30890000 { > - compatible = "fsl,imx7d-uart", > - "fsl,imx6q-uart"; > - reg = <0x30890000 0x10000>; > - status = "disabled"; > - }; > - > - uart3: serial at 30880000 { > - compatible = "fsl,imx7d-uart", > - "fsl,imx6q-uart"; > - reg = <0x30880000 0x10000>; > - status = "disabled"; > - }; > - > - i2c1: i2c at 30a20000 { > - #address-cells = <1>; > - #size-cells = <0>; > - compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; > - reg = <0x30a20000 0x10000>; > - status = "disabled"; > - }; > - > - i2c2: i2c at 30a30000 { > - #address-cells = <1>; > - #size-cells = <0>; > - compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; > - reg = <0x30a30000 0x10000>; > - status = "disabled"; > - }; > - > - i2c3: i2c at 30a40000 { > - #address-cells = <1>; > - #size-cells = <0>; > - compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; > - reg = <0x30a40000 0x10000>; > - status = "disabled"; > - }; > - > - i2c4: i2c at 30a50000 { > - #address-cells = <1>; > - #size-cells = <0>; > - compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; > - reg = <0x30a50000 0x10000>; > - status = "disabled"; > - }; > - > - uart4: serial at 30a60000 { > - compatible = "fsl,imx7d-uart", > - "fsl,imx6q-uart"; > - reg = <0x30a60000 0x10000>; > - status = "disabled"; > - }; > - > - uart5: serial at 30a70000 { > - compatible = "fsl,imx7d-uart", > - "fsl,imx6q-uart"; > - reg = <0x30a70000 0x10000>; > - status = "disabled"; > - }; > - > - uart6: serial at 30a80000 { > - compatible = "fsl,imx7d-uart", > - "fsl,imx6q-uart"; > - reg = <0x30a80000 0x10000>; > - status = "disabled"; > - }; > - > - uart7: serial at 30a90000 { > - compatible = "fsl,imx7d-uart", > - "fsl,imx6q-uart"; > - reg = <0x30a90000 0x10000>; > - status = "disabled"; > - }; > - }; > - }; > -}; > diff --git a/arch/arm/dts/imx7d-pinfunc.h b/arch/arm/dts/imx7d-pinfunc.h > index 32d2464..f6f7e78 100644 > --- a/arch/arm/dts/imx7d-pinfunc.h > +++ b/arch/arm/dts/imx7d-pinfunc.h > @@ -1,7 +1,10 @@ > /* > * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. > * > - * SPDX-License-Identifier: GPL-2.0+ > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > */ > > #ifndef __DTS_IMX7D_PINFUNC_H > @@ -12,57 +15,61 @@ > * <mux_reg conf_reg input_reg mux_mode input_val> > */ > > -#define MX7D_PAD_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0 > -#define MX7D_PAD_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0 > -#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0 > -#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0 > -#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0 > -#define MX7D_PAD_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0 > -#define MX7D_PAD_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0 > -#define MX7D_PAD_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0 > -#define MX7D_PAD_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0 > -#define MX7D_PAD_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0 > -#define MX7D_PAD_GPIO1_IO01__OBSERVE0_OUT 0x0004 0x0034 0x0000 0x6 0x0 > -#define MX7D_PAD_GPIO1_IO02__GPIO1_IO2 0x0008 0x0038 0x0000 0x0 0x0 > -#define MX7D_PAD_GPIO1_IO02__PWM2_OUT 0x0008 0x0038 0x0000 0x1 0x0 > -#define MX7D_PAD_GPIO1_IO02__CCM_ENET_REF_CLK1 0x0008 0x0038 0x0564 0x2 0x3 > -#define MX7D_PAD_GPIO1_IO02__SAI2_MCLK 0x0008 0x0038 0x0000 0x3 0x0 > -#define MX7D_PAD_GPIO1_IO02__CCM_CLKO1 0x0008 0x0038 0x0000 0x5 0x0 > -#define MX7D_PAD_GPIO1_IO02__OBSERVE1_OUT 0x0008 0x0038 0x0000 0x6 0x0 > -#define MX7D_PAD_GPIO1_IO02__USB_OTG1_ID 0x0008 0x0038 0x0734 0x7 0x3 > -#define MX7D_PAD_GPIO1_IO03__GPIO1_IO3 0x000C 0x003C 0x0000 0x0 0x0 > -#define MX7D_PAD_GPIO1_IO03__PWM3_OUT 0x000C 0x003C 0x0000 0x1 0x0 > -#define MX7D_PAD_GPIO1_IO03__CCM_ENET_REF_CLK2 0x000C 0x003C 0x0570 0x2 0x3 > -#define MX7D_PAD_GPIO1_IO03__SAI3_MCLK 0x000C 0x003C 0x0000 0x3 0x0 > -#define MX7D_PAD_GPIO1_IO03__CCM_CLKO2 0x000C 0x003C 0x0000 0x5 0x0 > -#define MX7D_PAD_GPIO1_IO03__OBSERVE2_OUT 0x000C 0x003C 0x0000 0x6 0x0 > -#define MX7D_PAD_GPIO1_IO03__USB_OTG2_ID 0x000C 0x003C 0x0730 0x7 0x3 > -#define MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x0010 0x0040 0x0000 0x0 0x0 > -#define MX7D_PAD_GPIO1_IO04__USB_OTG1_OC 0x0010 0x0040 0x072C 0x1 0x1 > -#define MX7D_PAD_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x1 > -#define MX7D_PAD_GPIO1_IO04__UART5_CTS_B 0x0010 0x0040 0x0710 0x3 0x4 > -#define MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x0010 0x0040 0x05D4 0x4 0x2 > -#define MX7D_PAD_GPIO1_IO04__OBSERVE3_OUT 0x0010 0x0040 0x0000 0x6 0x0 > -#define MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x0014 0x0044 0x0000 0x0 0x0 > -#define MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR 0x0014 0x0044 0x0000 0x1 0x0 > -#define MX7D_PAD_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0x1 > -#define MX7D_PAD_GPIO1_IO05__UART5_RTS_B 0x0014 0x0044 0x0710 0x3 0x5 > -#define MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x0014 0x0044 0x05D8 0x4 0x2 > -#define MX7D_PAD_GPIO1_IO05__OBSERVE4_OUT 0x0014 0x0044 0x0000 0x6 0x0 > -#define MX7D_PAD_GPIO1_IO06__GPIO1_IO6 0x0018 0x0048 0x0000 0x0 0x0 > -#define MX7D_PAD_GPIO1_IO06__USB_OTG2_OC 0x0018 0x0048 0x0728 0x1 0x1 > -#define MX7D_PAD_GPIO1_IO06__FLEXTIMER1_CH6 0x0018 0x0048 0x059C 0x2 0x1 > -#define MX7D_PAD_GPIO1_IO06__UART5_RX_DATA 0x0018 0x0048 0x0714 0x3 0x4 > -#define MX7D_PAD_GPIO1_IO06__I2C2_SCL 0x0018 0x0048 0x05DC 0x4 0x2 > -#define MX7D_PAD_GPIO1_IO06__CCM_WAIT 0x0018 0x0048 0x0000 0x5 0x0 > -#define MX7D_PAD_GPIO1_IO06__KPP_ROW4 0x0018 0x0048 0x0624 0x6 0x1 > -#define MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x001C 0x004C 0x0000 0x0 0x0 > -#define MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR 0x001C 0x004C 0x0000 0x1 0x0 > -#define MX7D_PAD_GPIO1_IO07__FLEXTIMER1_CH7 0x001C 0x004C 0x05A0 0x2 0x1 > -#define MX7D_PAD_GPIO1_IO07__UART5_TX_DATA 0x001C 0x004C 0x0714 0x3 0x5 > -#define MX7D_PAD_GPIO1_IO07__I2C2_SDA 0x001C 0x004C 0x05E0 0x4 0x2 > -#define MX7D_PAD_GPIO1_IO07__CCM_STOP 0x001C 0x004C 0x0000 0x5 0x0 > -#define MX7D_PAD_GPIO1_IO07__KPP_COL4 0x001C 0x004C 0x0604 0x6 0x1 > +#define MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0 > +#define MX7D_PAD_LPSR_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0 > +#define MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0 > +#define MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0 > +#define MX7D_PAD_LPSR_GPIO1_IO00__WDOD1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0 > +#define MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0 > +#define MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0 > +#define MX7D_PAD_LPSR_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0 > +#define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0 > +#define MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0 > +#define MX7D_PAD_LPSR_GPIO1_IO01__OBSERVE0_OUT 0x0004 0x0034 0x0000 0x6 0x0 > +#define MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x0008 0x0038 0x0000 0x0 0x0 > +#define MX7D_PAD_LPSR_GPIO1_IO02__PWM2_OUT 0x0008 0x0038 0x0000 0x1 0x0 > +#define MX7D_PAD_LPSR_GPIO1_IO02__CCM_ENET_REF_CLK1 0x0008 0x0038 0x0564 0x2 0x3 > +#define MX7D_PAD_LPSR_GPIO1_IO02__SAI2_MCLK 0x0008 0x0038 0x0000 0x3 0x0 > +#define MX7D_PAD_LPSR_GPIO1_IO02__CCM_CLKO1 0x0008 0x0038 0x0000 0x5 0x0 > +#define MX7D_PAD_LPSR_GPIO1_IO02__OBSERVE1_OUT 0x0008 0x0038 0x0000 0x6 0x0 > +#define MX7D_PAD_LPSR_GPIO1_IO02__USB_OTG1_ID 0x0008 0x0038 0x0734 0x7 0x3 > +#define MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x000C 0x003C 0x0000 0x0 0x0 > +#define MX7D_PAD_LPSR_GPIO1_IO03__PWM3_OUT 0x000C 0x003C 0x0000 0x1 0x0 > +#define MX7D_PAD_LPSR_GPIO1_IO03__CCM_ENET_REF_CLK2 0x000C 0x003C 0x0570 0x2 0x3 > +#define MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK 0x000C 0x003C 0x0000 0x3 0x0 > +#define MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2 0x000C 0x003C 0x0000 0x5 0x0 > +#define MX7D_PAD_LPSR_GPIO1_IO03__OBSERVE2_OUT 0x000C 0x003C 0x0000 0x6 0x0 > +#define MX7D_PAD_LPSR_GPIO1_IO03__USB_OTG2_ID 0x000C 0x003C 0x0730 0x7 0x3 > +#define MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x0010 0x0040 0x0000 0x0 0x0 > +#define MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x0010 0x0040 0x072C 0x1 0x1 > +#define MX7D_PAD_LPSR_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x1 > +#define MX7D_PAD_LPSR_GPIO1_IO04__UART5_DCE_CTS 0x0010 0x0040 0x0000 0x3 0x0 > +#define MX7D_PAD_LPSR_GPIO1_IO04__UART5_DTE_RTS 0x0010 0x0040 0x0710 0x3 0x4 > +#define MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x0010 0x0040 0x05D4 0x4 0x2 > +#define MX7D_PAD_LPSR_GPIO1_IO04__OBSERVE3_OUT 0x0010 0x0040 0x0000 0x6 0x0 > +#define MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x0014 0x0044 0x0000 0x0 0x0 > +#define MX7D_PAD_LPSR_GPIO1_IO05__USB_OTG1_PWR 0x0014 0x0044 0x0000 0x1 0x0 > +#define MX7D_PAD_LPSR_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0x1 > +#define MX7D_PAD_LPSR_GPIO1_IO05__UART5_DCE_RTS 0x0014 0x0044 0x0710 0x3 0x5 > +#define MX7D_PAD_LPSR_GPIO1_IO05__UART5_DTE_CTS 0x0014 0x0044 0x0000 0x3 0x0 > +#define MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x0014 0x0044 0x05D8 0x4 0x2 > +#define MX7D_PAD_LPSR_GPIO1_IO05__OBSERVE4_OUT 0x0014 0x0044 0x0000 0x6 0x0 > +#define MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x0018 0x0048 0x0000 0x0 0x0 > +#define MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC 0x0018 0x0048 0x0728 0x1 0x1 > +#define MX7D_PAD_LPSR_GPIO1_IO06__FLEXTIMER1_CH6 0x0018 0x0048 0x059C 0x2 0x1 > +#define MX7D_PAD_LPSR_GPIO1_IO06__UART5_DCE_RX 0x0018 0x0048 0x0714 0x3 0x4 > +#define MX7D_PAD_LPSR_GPIO1_IO06__UART5_DTE_TX 0x0018 0x0048 0x0000 0x3 0x0 > +#define MX7D_PAD_LPSR_GPIO1_IO06__I2C2_SCL 0x0018 0x0048 0x05DC 0x4 0x2 > +#define MX7D_PAD_LPSR_GPIO1_IO06__CCM_WAIT 0x0018 0x0048 0x0000 0x5 0x0 > +#define MX7D_PAD_LPSR_GPIO1_IO06__KPP_ROW4 0x0018 0x0048 0x0624 0x6 0x1 > +#define MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x001C 0x004C 0x0000 0x0 0x0 > +#define MX7D_PAD_LPSR_GPIO1_IO07__USB_OTG2_PWR 0x001C 0x004C 0x0000 0x1 0x0 > +#define MX7D_PAD_LPSR_GPIO1_IO07__FLEXTIMER1_CH7 0x001C 0x004C 0x05A0 0x2 0x1 > +#define MX7D_PAD_LPSR_GPIO1_IO07__UART5_DCE_TX 0x001C 0x004C 0x0000 0x3 0x0 > +#define MX7D_PAD_LPSR_GPIO1_IO07__UART5_DTE_RX 0x001C 0x004C 0x0714 0x3 0x5 > +#define MX7D_PAD_LPSR_GPIO1_IO07__I2C2_SDA 0x001C 0x004C 0x05E0 0x4 0x2 > +#define MX7D_PAD_LPSR_GPIO1_IO07__CCM_STOP 0x001C 0x004C 0x0000 0x5 0x0 > +#define MX7D_PAD_LPSR_GPIO1_IO07__KPP_COL4 0x001C 0x004C 0x0604 0x6 0x1 > #define MX7D_PAD_GPIO1_IO08__GPIO1_IO8 0x0014 0x026C 0x0000 0x0 0x0 > #define MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x0014 0x026C 0x0000 0x1 0x0 > #define MX7D_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0014 0x026C 0x0000 0x2 0x0 > diff --git a/arch/arm/dts/imx7d.dtsi b/arch/arm/dts/imx7d.dtsi > new file mode 100644 > index 0000000..f6dee41 > --- /dev/null > +++ b/arch/arm/dts/imx7d.dtsi > @@ -0,0 +1,140 @@ > +/* > + * Copyright 2015 Freescale Semiconductor, Inc. > + * Copyright 2016 Toradex AG > + * > + * This file is dual-licensed: you can use it either under the terms > + * of the GPL or the X11 license, at your option. Note that this dual > + * licensing only applies to this file, and not this project as a > + * whole. > + * > + * a) This file is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of the > + * License, or (at your option) any later version. > + * > + * This file is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * Or, alternatively, > + * > + * b) Permission is hereby granted, free of charge, to any person > + * obtaining a copy of this software and associated documentation > + * files (the "Software"), to deal in the Software without > + * restriction, including without limitation the rights to use, > + * copy, modify, merge, publish, distribute, sublicense, and/or > + * sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following > + * conditions: > + * > + * The above copyright notice and this permission notice shall be > + * included in all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES > + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT > + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, > + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + */ > + > +#include "imx7s.dtsi" > + > +/ { > + cpus { > + cpu0: cpu at 0 { > + operating-points = < > + /* KHz uV */ > + 996000 1075000 > + 792000 975000 > + >; > + clock-frequency = <996000000>; > + }; > + > + cpu1: cpu at 1 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <1>; > + clock-frequency = <996000000>; > + }; > + }; > + > + soc { > + etm at 3007d000 { > + compatible = "arm,coresight-etm3x", "arm,primecell"; > + reg = <0x3007d000 0x1000>; > + > + /* > + * System will hang if added nosmp in kernel command line > + * without arm,primecell-periphid because amba bus try to > + * read id and core1 power off at this time. > + */ > + arm,primecell-periphid = <0xbb956>; > + cpu = <&cpu1>; > + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; > + clock-names = "apb_pclk"; > + > + port { > + etm1_out_port: endpoint { > + remote-endpoint = <&ca_funnel_in_port1>; > + }; > + }; > + }; > + }; > +}; > + > +&aips3 { > + usbotg2: usb at 30b20000 { > + compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; > + reg = <0x30b20000 0x200>; > + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_USB_CTRL_CLK>; > + fsl,usbphy = <&usbphynop2>; > + fsl,usbmisc = <&usbmisc2 0>; > + phy-clkgate-delay-us = <400>; > + status = "disabled"; > + }; > + > + usbmisc2: usbmisc at 30b20200 { > + #index-cells = <1>; > + compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; > + reg = <0x30b20200 0x200>; > + }; > + > + usbphynop2: usbphynop2 { > + compatible = "usb-nop-xceiv"; > + clocks = <&clks IMX7D_USB_PHY2_CLK>; > + clock-names = "main_clk"; > + }; > + > + fec2: ethernet at 30bf0000 { > + compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; > + reg = <0x30bf0000 0x10000>; > + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, > + <&clks IMX7D_ENET_AXI_ROOT_CLK>, > + <&clks IMX7D_ENET2_TIME_ROOT_CLK>, > + <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, > + <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; > + clock-names = "ipg", "ahb", "ptp", > + "enet_clk_ref", "enet_out"; > + fsl,num-tx-queues=<3>; > + fsl,num-rx-queues=<3>; > + status = "disabled"; > + }; > +}; > + > +&ca_funnel_ports { > + port at 1 { > + reg = <1>; > + ca_funnel_in_port1: endpoint { > + slave-mode; > + remote-endpoint = <&etm1_out_port>; > + }; > + }; > +}; > diff --git a/arch/arm/dts/imx7s.dtsi b/arch/arm/dts/imx7s.dtsi > new file mode 100644 > index 0000000..a7d48e7 > --- /dev/null > +++ b/arch/arm/dts/imx7s.dtsi > @@ -0,0 +1,999 @@ > +/* > + * Copyright 2015 Freescale Semiconductor, Inc. > + * Copyright 2016 Toradex AG > + * > + * This file is dual-licensed: you can use it either under the terms > + * of the GPL or the X11 license, at your option. Note that this dual > + * licensing only applies to this file, and not this project as a > + * whole. > + * > + * a) This file is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of the > + * License, or (at your option) any later version. > + * > + * This file is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * Or, alternatively, > + * > + * b) Permission is hereby granted, free of charge, to any person > + * obtaining a copy of this software and associated documentation > + * files (the "Software"), to deal in the Software without > + * restriction, including without limitation the rights to use, > + * copy, modify, merge, publish, distribute, sublicense, and/or > + * sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following > + * conditions: > + * > + * The above copyright notice and this permission notice shall be > + * included in all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES > + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT > + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, > + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + */ > + > +#include <dt-bindings/clock/imx7d-clock.h> > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/input/input.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include "imx7d-pinfunc.h" > + > +/ { > + #address-cells = <1>; > + #size-cells = <1>; > + /* > + * The decompressor and also some bootloaders rely on a > + * pre-existing /chosen node to be available to insert the > + * command line and merge other ATAGS info. > + * Also for U-Boot there must be a pre-existing /memory node. > + */ > + chosen {}; > + memory { device_type = "memory"; reg = <0 0>; }; > + > + aliases { > + gpio0 = &gpio1; > + gpio1 = &gpio2; > + gpio2 = &gpio3; > + gpio3 = &gpio4; > + gpio4 = &gpio5; > + gpio5 = &gpio6; > + gpio6 = &gpio7; > + i2c0 = &i2c1; > + i2c1 = &i2c2; > + i2c2 = &i2c3; > + i2c3 = &i2c4; > + mmc0 = &usdhc1; > + mmc1 = &usdhc2; > + mmc2 = &usdhc3; > + serial0 = &uart1; > + serial1 = &uart2; > + serial2 = &uart3; > + serial3 = &uart4; > + serial4 = &uart5; > + serial5 = &uart6; > + serial6 = &uart7; > + spi0 = &ecspi1; > + spi1 = &ecspi2; > + spi2 = &ecspi3; > + spi3 = &ecspi4; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu0: cpu at 0 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <0>; > + clock-frequency = <792000000>; > + clock-latency = <61036>; /* two CLK32 periods */ > + clocks = <&clks IMX7D_CLK_ARM>; > + }; > + }; > + > + ckil: clock-cki { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <32768>; > + clock-output-names = "ckil"; > + }; > + > + osc: clock-osc { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <24000000>; > + clock-output-names = "osc"; > + }; > + > + soc { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "simple-bus"; > + interrupt-parent = <&intc>; > + ranges; > + > + funnel at 30041000 { > + compatible = "arm,coresight-funnel", "arm,primecell"; > + reg = <0x30041000 0x1000>; > + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; > + clock-names = "apb_pclk"; > + > + ca_funnel_ports: ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + /* funnel input ports */ > + port at 0 { > + reg = <0>; > + ca_funnel_in_port0: endpoint { > + slave-mode; > + remote-endpoint = <&etm0_out_port>; > + }; > + }; > + > + /* funnel output port */ > + port at 2 { > + reg = <0>; > + ca_funnel_out_port0: endpoint { > + remote-endpoint = <&hugo_funnel_in_port0>; > + }; > + }; > + > + /* the other input ports are not connect to anything */ > + }; > + }; > + > + etm at 3007c000 { > + compatible = "arm,coresight-etm3x", "arm,primecell"; > + reg = <0x3007c000 0x1000>; > + cpu = <&cpu0>; > + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; > + clock-names = "apb_pclk"; > + > + port { > + etm0_out_port: endpoint { > + remote-endpoint = <&ca_funnel_in_port0>; > + }; > + }; > + }; > + > + funnel at 30083000 { > + compatible = "arm,coresight-funnel", "arm,primecell"; > + reg = <0x30083000 0x1000>; > + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; > + clock-names = "apb_pclk"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + /* funnel input ports */ > + port at 0 { > + reg = <0>; > + hugo_funnel_in_port0: endpoint { > + slave-mode; > + remote-endpoint = <&ca_funnel_out_port0>; > + }; > + }; > + > + port at 1 { > + reg = <1>; > + hugo_funnel_in_port1: endpoint { > + slave-mode; /* M4 input */ > + }; > + }; > + > + port at 2 { > + reg = <0>; > + hugo_funnel_out_port0: endpoint { > + remote-endpoint = <&etf_in_port>; > + }; > + }; > + > + /* the other input ports are not connect to anything */ > + }; > + }; > + > + etf at 30084000 { > + compatible = "arm,coresight-tmc", "arm,primecell"; > + reg = <0x30084000 0x1000>; > + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; > + clock-names = "apb_pclk"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port at 0 { > + reg = <0>; > + etf_in_port: endpoint { > + slave-mode; > + remote-endpoint = <&hugo_funnel_out_port0>; > + }; > + }; > + > + port at 1 { > + reg = <0>; > + etf_out_port: endpoint { > + remote-endpoint = <&replicator_in_port0>; > + }; > + }; > + }; > + }; > + > + etr at 30086000 { > + compatible = "arm,coresight-tmc", "arm,primecell"; > + reg = <0x30086000 0x1000>; > + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; > + clock-names = "apb_pclk"; > + > + port { > + etr_in_port: endpoint { > + slave-mode; > + remote-endpoint = <&replicator_out_port1>; > + }; > + }; > + }; > + > + tpiu at 30087000 { > + compatible = "arm,coresight-tpiu", "arm,primecell"; > + reg = <0x30087000 0x1000>; > + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; > + clock-names = "apb_pclk"; > + > + port { > + tpiu_in_port: endpoint { > + slave-mode; > + remote-endpoint = <&replicator_out_port1>; > + }; > + }; > + }; > + > + replicator { > + /* > + * non-configurable replicators don't show up on the > + * AMBA bus. As such no need to add "arm,primecell" > + */ > + compatible = "arm,coresight-replicator"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + /* replicator output ports */ > + port at 0 { > + reg = <0>; > + replicator_out_port0: endpoint { > + remote-endpoint = <&tpiu_in_port>; > + }; > + }; > + > + port at 1 { > + reg = <1>; > + replicator_out_port1: endpoint { > + remote-endpoint = <&etr_in_port>; > + }; > + }; > + > + /* replicator input port */ > + port at 2 { > + reg = <0>; > + replicator_in_port0: endpoint { > + slave-mode; > + remote-endpoint = <&etf_out_port>; > + }; > + }; > + }; > + }; > + > + intc: interrupt-controller at 31001000 { > + compatible = "arm,cortex-a7-gic"; > + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > + #interrupt-cells = <3>; > + interrupt-controller; > + reg = <0x31001000 0x1000>, > + <0x31002000 0x2000>, > + <0x31004000 0x2000>, > + <0x31006000 0x2000>; > + }; > + > + timer { > + compatible = "arm,armv7-timer"; > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; > + }; > + > + aips1: aips-bus at 30000000 { > + compatible = "fsl,aips-bus", "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + reg = <0x30000000 0x400000>; > + ranges; > + > + gpio1: gpio at 30200000 { > + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; > + reg = <0x30200000 0x10000>; > + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */ > + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */ > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>; > + }; > + > + gpio2: gpio at 30210000 { > + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; > + reg = <0x30210000 0x10000>; > + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + gpio-ranges = <&iomuxc 0 13 32>; > + }; > + > + gpio3: gpio at 30220000 { > + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; > + reg = <0x30220000 0x10000>; > + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + gpio-ranges = <&iomuxc 0 45 29>; > + }; > + > + gpio4: gpio at 30230000 { > + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; > + reg = <0x30230000 0x10000>; > + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + gpio-ranges = <&iomuxc 0 74 24>; > + }; > + > + gpio5: gpio at 30240000 { > + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; > + reg = <0x30240000 0x10000>; > + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + gpio-ranges = <&iomuxc 0 98 18>; > + }; > + > + gpio6: gpio at 30250000 { > + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; > + reg = <0x30250000 0x10000>; > + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + gpio-ranges = <&iomuxc 0 116 23>; > + }; > + > + gpio7: gpio at 30260000 { > + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; > + reg = <0x30260000 0x10000>; > + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + gpio-ranges = <&iomuxc 0 139 16>; > + }; > + > + wdog1: wdog at 30280000 { > + compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; > + reg = <0x30280000 0x10000>; > + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_WDOG1_ROOT_CLK>; > + }; > + > + wdog2: wdog at 30290000 { > + compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; > + reg = <0x30290000 0x10000>; > + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_WDOG2_ROOT_CLK>; > + status = "disabled"; > + }; > + > + wdog3: wdog at 302a0000 { > + compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; > + reg = <0x302a0000 0x10000>; > + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_WDOG3_ROOT_CLK>; > + status = "disabled"; > + }; > + > + wdog4: wdog at 302b0000 { > + compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; > + reg = <0x302b0000 0x10000>; > + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_WDOG4_ROOT_CLK>; > + status = "disabled"; > + }; > + > + iomuxc_lpsr: iomuxc-lpsr at 302c0000 { > + compatible = "fsl,imx7d-iomuxc-lpsr"; > + reg = <0x302c0000 0x10000>; > + fsl,input-sel = <&iomuxc>; > + }; > + > + gpt1: gpt at 302d0000 { > + compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; > + reg = <0x302d0000 0x10000>; > + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_CLK_DUMMY>, > + <&clks IMX7D_GPT1_ROOT_CLK>; > + clock-names = "ipg", "per"; > + }; > + > + gpt2: gpt at 302e0000 { > + compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; > + reg = <0x302e0000 0x10000>; > + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_CLK_DUMMY>, > + <&clks IMX7D_GPT2_ROOT_CLK>; > + clock-names = "ipg", "per"; > + status = "disabled"; > + }; > + > + gpt3: gpt at 302f0000 { > + compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; > + reg = <0x302f0000 0x10000>; > + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_CLK_DUMMY>, > + <&clks IMX7D_GPT3_ROOT_CLK>; > + clock-names = "ipg", "per"; > + status = "disabled"; > + }; > + > + gpt4: gpt at 30300000 { > + compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; > + reg = <0x30300000 0x10000>; > + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_CLK_DUMMY>, > + <&clks IMX7D_GPT4_ROOT_CLK>; > + clock-names = "ipg", "per"; > + status = "disabled"; > + }; > + > + iomuxc: iomuxc at 30330000 { > + compatible = "fsl,imx7d-iomuxc"; > + reg = <0x30330000 0x10000>; > + }; > + > + gpr: iomuxc-gpr at 30340000 { > + compatible = "fsl,imx7d-iomuxc-gpr", "syscon"; > + reg = <0x30340000 0x10000>; > + }; > + > + ocotp: ocotp-ctrl at 30350000 { > + compatible = "fsl,imx7d-ocotp", "syscon"; > + reg = <0x30350000 0x10000>; > + clocks = <&clks IMX7D_OCOTP_CLK>; > + }; > + > + anatop: anatop at 30360000 { > + compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop", > + "syscon", "simple-bus"; > + reg = <0x30360000 0x10000>; > + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; > + > + reg_1p0d: regulator-vdd1p0d { > + compatible = "fsl,anatop-regulator"; > + regulator-name = "vdd1p0d"; > + regulator-min-microvolt = <800000>; > + regulator-max-microvolt = <1200000>; > + anatop-reg-offset = <0x210>; > + anatop-vol-bit-shift = <8>; > + anatop-vol-bit-width = <5>; > + anatop-min-bit-val = <8>; > + anatop-min-voltage = <800000>; > + anatop-max-voltage = <1200000>; > + }; > + }; > + > + snvs: snvs at 30370000 { > + compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; > + reg = <0x30370000 0x10000>; > + > + snvs_rtc: snvs-rtc-lp { > + compatible = "fsl,sec-v4.0-mon-rtc-lp"; > + regmap = <&snvs>; > + offset = <0x34>; > + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + snvs_poweroff: snvs-poweroff { > + compatible = "syscon-poweroff"; > + regmap = <&snvs>; > + offset = <0x38>; > + mask = <0x60>; > + }; > + > + snvs_pwrkey: snvs-powerkey { > + compatible = "fsl,sec-v4.0-pwrkey"; > + regmap = <&snvs>; > + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; > + linux,keycode = <KEY_POWER>; > + wakeup-source; > + }; > + }; > + > + clks: ccm at 30380000 { > + compatible = "fsl,imx7d-ccm"; > + reg = <0x30380000 0x10000>; > + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; > + #clock-cells = <1>; > + clocks = <&ckil>, <&osc>; > + clock-names = "ckil", "osc"; > + }; > + > + src: src at 30390000 { > + compatible = "fsl,imx7d-src", "fsl,imx51-src", "syscon"; > + reg = <0x30390000 0x10000>; > + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; > + #reset-cells = <1>; > + }; > + }; > + > + aips2: aips-bus at 30400000 { > + compatible = "fsl,aips-bus", "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + reg = <0x30400000 0x400000>; > + ranges; > + > + adc1: adc at 30610000 { > + compatible = "fsl,imx7d-adc"; > + reg = <0x30610000 0x10000>; > + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_ADC_ROOT_CLK>; > + clock-names = "adc"; > + status = "disabled"; > + }; > + > + adc2: adc at 30620000 { > + compatible = "fsl,imx7d-adc"; > + reg = <0x30620000 0x10000>; > + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_ADC_ROOT_CLK>; > + clock-names = "adc"; > + status = "disabled"; > + }; > + > + ecspi4: ecspi at 30630000 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; > + reg = <0x30630000 0x10000>; > + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>, > + <&clks IMX7D_ECSPI4_ROOT_CLK>; > + clock-names = "ipg", "per"; > + status = "disabled"; > + }; > + > + pwm1: pwm at 30660000 { > + compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; > + reg = <0x30660000 0x10000>; > + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_PWM1_ROOT_CLK>, > + <&clks IMX7D_PWM1_ROOT_CLK>; > + clock-names = "ipg", "per"; > + #pwm-cells = <2>; > + status = "disabled"; > + }; > + > + pwm2: pwm at 30670000 { > + compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; > + reg = <0x30670000 0x10000>; > + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_PWM2_ROOT_CLK>, > + <&clks IMX7D_PWM2_ROOT_CLK>; > + clock-names = "ipg", "per"; > + #pwm-cells = <2>; > + status = "disabled"; > + }; > + > + pwm3: pwm at 30680000 { > + compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; > + reg = <0x30680000 0x10000>; > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_PWM3_ROOT_CLK>, > + <&clks IMX7D_PWM3_ROOT_CLK>; > + clock-names = "ipg", "per"; > + #pwm-cells = <2>; > + status = "disabled"; > + }; > + > + pwm4: pwm at 30690000 { > + compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; > + reg = <0x30690000 0x10000>; > + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_PWM4_ROOT_CLK>, > + <&clks IMX7D_PWM4_ROOT_CLK>; > + clock-names = "ipg", "per"; > + #pwm-cells = <2>; > + status = "disabled"; > + }; > + > + lcdif: lcdif at 30730000 { > + compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif"; > + reg = <0x30730000 0x10000>; > + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>, > + <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>; > + clock-names = "pix", "axi"; > + status = "disabled"; > + }; > + }; > + > + aips3: aips-bus at 30800000 { > + compatible = "fsl,aips-bus", "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + reg = <0x30800000 0x400000>; > + ranges; > + > + ecspi1: ecspi at 30820000 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; > + reg = <0x30820000 0x10000>; > + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>, > + <&clks IMX7D_ECSPI1_ROOT_CLK>; > + clock-names = "ipg", "per"; > + status = "disabled"; > + }; > + > + ecspi2: ecspi at 30830000 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; > + reg = <0x30830000 0x10000>; > + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>, > + <&clks IMX7D_ECSPI2_ROOT_CLK>; > + clock-names = "ipg", "per"; > + status = "disabled"; > + }; > + > + ecspi3: ecspi at 30840000 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; > + reg = <0x30840000 0x10000>; > + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>, > + <&clks IMX7D_ECSPI3_ROOT_CLK>; > + clock-names = "ipg", "per"; > + status = "disabled"; > + }; > + > + uart1: serial at 30860000 { > + compatible = "fsl,imx7d-uart", > + "fsl,imx6q-uart"; > + reg = <0x30860000 0x10000>; > + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_UART1_ROOT_CLK>, > + <&clks IMX7D_UART1_ROOT_CLK>; > + clock-names = "ipg", "per"; > + status = "disabled"; > + }; > + > + uart2: serial at 30890000 { > + compatible = "fsl,imx7d-uart", > + "fsl,imx6q-uart"; > + reg = <0x30890000 0x10000>; > + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_UART2_ROOT_CLK>, > + <&clks IMX7D_UART2_ROOT_CLK>; > + clock-names = "ipg", "per"; > + status = "disabled"; > + }; > + > + uart3: serial at 30880000 { > + compatible = "fsl,imx7d-uart", > + "fsl,imx6q-uart"; > + reg = <0x30880000 0x10000>; > + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_UART3_ROOT_CLK>, > + <&clks IMX7D_UART3_ROOT_CLK>; > + clock-names = "ipg", "per"; > + status = "disabled"; > + }; > + > + sai1: sai at 308a0000 { > + #sound-dai-cells = <0>; > + compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; > + reg = <0x308a0000 0x10000>; > + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_SAI1_IPG_CLK>, > + <&clks IMX7D_SAI1_ROOT_CLK>, > + <&clks IMX7D_CLK_DUMMY>, > + <&clks IMX7D_CLK_DUMMY>; > + clock-names = "bus", "mclk1", "mclk2", "mclk3"; > + dma-names = "rx", "tx"; > + dmas = <&sdma 8 24 0>, <&sdma 9 24 0>; > + status = "disabled"; > + }; > + > + sai2: sai at 308b0000 { > + #sound-dai-cells = <0>; > + compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; > + reg = <0x308b0000 0x10000>; > + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_SAI2_IPG_CLK>, > + <&clks IMX7D_SAI2_ROOT_CLK>, > + <&clks IMX7D_CLK_DUMMY>, > + <&clks IMX7D_CLK_DUMMY>; > + clock-names = "bus", "mclk1", "mclk2", "mclk3"; > + dma-names = "rx", "tx"; > + dmas = <&sdma 10 24 0>, <&sdma 11 24 0>; > + status = "disabled"; > + }; > + > + sai3: sai at 308c0000 { > + #sound-dai-cells = <0>; > + compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; > + reg = <0x308c0000 0x10000>; > + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_SAI3_IPG_CLK>, > + <&clks IMX7D_SAI3_ROOT_CLK>, > + <&clks IMX7D_CLK_DUMMY>, > + <&clks IMX7D_CLK_DUMMY>; > + clock-names = "bus", "mclk1", "mclk2", "mclk3"; > + dma-names = "rx", "tx"; > + dmas = <&sdma 12 24 0>, <&sdma 13 24 0>; > + status = "disabled"; > + }; > + > + flexcan1: can at 30a00000 { > + compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; > + reg = <0x30a00000 0x10000>; > + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_CLK_DUMMY>, > + <&clks IMX7D_CAN1_ROOT_CLK>; > + clock-names = "ipg", "per"; > + status = "disabled"; > + }; > + > + flexcan2: can at 30a10000 { > + compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; > + reg = <0x30a10000 0x10000>; > + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_CLK_DUMMY>, > + <&clks IMX7D_CAN2_ROOT_CLK>; > + clock-names = "ipg", "per"; > + status = "disabled"; > + }; > + > + i2c1: i2c at 30a20000 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; > + reg = <0x30a20000 0x10000>; > + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_I2C1_ROOT_CLK>; > + status = "disabled"; > + }; > + > + i2c2: i2c at 30a30000 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; > + reg = <0x30a30000 0x10000>; > + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_I2C2_ROOT_CLK>; > + status = "disabled"; > + }; > + > + i2c3: i2c at 30a40000 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; > + reg = <0x30a40000 0x10000>; > + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_I2C3_ROOT_CLK>; > + status = "disabled"; > + }; > + > + i2c4: i2c at 30a50000 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; > + reg = <0x30a50000 0x10000>; > + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_I2C4_ROOT_CLK>; > + status = "disabled"; > + }; > + > + uart4: serial at 30a60000 { > + compatible = "fsl,imx7d-uart", > + "fsl,imx6q-uart"; > + reg = <0x30a60000 0x10000>; > + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_UART4_ROOT_CLK>, > + <&clks IMX7D_UART4_ROOT_CLK>; > + clock-names = "ipg", "per"; > + status = "disabled"; > + }; > + > + uart5: serial at 30a70000 { > + compatible = "fsl,imx7d-uart", > + "fsl,imx6q-uart"; > + reg = <0x30a70000 0x10000>; > + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_UART5_ROOT_CLK>, > + <&clks IMX7D_UART5_ROOT_CLK>; > + clock-names = "ipg", "per"; > + status = "disabled"; > + }; > + > + uart6: serial at 30a80000 { > + compatible = "fsl,imx7d-uart", > + "fsl,imx6q-uart"; > + reg = <0x30a80000 0x10000>; > + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_UART6_ROOT_CLK>, > + <&clks IMX7D_UART6_ROOT_CLK>; > + clock-names = "ipg", "per"; > + status = "disabled"; > + }; > + > + uart7: serial at 30a90000 { > + compatible = "fsl,imx7d-uart", > + "fsl,imx6q-uart"; > + reg = <0x30a90000 0x10000>; > + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_UART7_ROOT_CLK>, > + <&clks IMX7D_UART7_ROOT_CLK>; > + clock-names = "ipg", "per"; > + status = "disabled"; > + }; > + > + usbotg1: usb at 30b10000 { > + compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; > + reg = <0x30b10000 0x200>; > + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_USB_CTRL_CLK>; > + fsl,usbphy = <&usbphynop1>; > + fsl,usbmisc = <&usbmisc1 0>; > + phy-clkgate-delay-us = <400>; > + status = "disabled"; > + }; > + > + usbh: usb at 30b30000 { > + compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; > + reg = <0x30b30000 0x200>; > + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_USB_CTRL_CLK>; > + fsl,usbphy = <&usbphynop3>; > + fsl,usbmisc = <&usbmisc3 0>; > + phy_type = "hsic"; > + dr_mode = "host"; > + phy-clkgate-delay-us = <400>; > + status = "disabled"; > + }; > + > + usbmisc1: usbmisc at 30b10200 { > + #index-cells = <1>; > + compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; > + reg = <0x30b10200 0x200>; > + }; > + > + usbmisc3: usbmisc at 30b30200 { > + #index-cells = <1>; > + compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; > + reg = <0x30b30200 0x200>; > + }; > + > + usbphynop1: usbphynop1 { > + compatible = "usb-nop-xceiv"; > + clocks = <&clks IMX7D_USB_PHY1_CLK>; > + clock-names = "main_clk"; > + }; > + > + usbphynop3: usbphynop3 { > + compatible = "usb-nop-xceiv"; > + clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>; > + clock-names = "main_clk"; > + }; > + > + usdhc1: usdhc at 30b40000 { > + compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; > + reg = <0x30b40000 0x10000>; > + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_CLK_DUMMY>, > + <&clks IMX7D_CLK_DUMMY>, > + <&clks IMX7D_USDHC1_ROOT_CLK>; > + clock-names = "ipg", "ahb", "per"; > + bus-width = <4>; > + status = "disabled"; > + }; > + > + usdhc2: usdhc at 30b50000 { > + compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; > + reg = <0x30b50000 0x10000>; > + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_CLK_DUMMY>, > + <&clks IMX7D_CLK_DUMMY>, > + <&clks IMX7D_USDHC2_ROOT_CLK>; > + clock-names = "ipg", "ahb", "per"; > + bus-width = <4>; > + status = "disabled"; > + }; > + > + usdhc3: usdhc at 30b60000 { > + compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; > + reg = <0x30b60000 0x10000>; > + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_CLK_DUMMY>, > + <&clks IMX7D_CLK_DUMMY>, > + <&clks IMX7D_USDHC3_ROOT_CLK>; > + clock-names = "ipg", "ahb", "per"; > + bus-width = <4>; > + status = "disabled"; > + }; > + > + sdma: sdma at 30bd0000 { > + compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma"; > + reg = <0x30bd0000 0x10000>; > + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_SDMA_CORE_CLK>, > + <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>; > + clock-names = "ipg", "ahb"; > + #dma-cells = <3>; > + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; > + }; > + > + fec1: ethernet at 30be0000 { > + compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; > + reg = <0x30be0000 0x10000>; > + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, > + <&clks IMX7D_ENET_AXI_ROOT_CLK>, > + <&clks IMX7D_ENET1_TIME_ROOT_CLK>, > + <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, > + <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; > + clock-names = "ipg", "ahb", "ptp", > + "enet_clk_ref", "enet_out"; > + fsl,num-tx-queues=<3>; > + fsl,num-rx-queues=<3>; > + status = "disabled"; > + }; > + }; > + }; > +}; > diff --git a/include/dt-bindings/clock/imx7d-clock.h b/include/dt-bindings/clock/imx7d-clock.h > new file mode 100644 > index 0000000..a7a1a50 > --- /dev/null > +++ b/include/dt-bindings/clock/imx7d-clock.h > @@ -0,0 +1,454 @@ > +/* > + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + */ > + > +#ifndef __DT_BINDINGS_CLOCK_IMX7D_H > +#define __DT_BINDINGS_CLOCK_IMX7D_H > + > +#define IMX7D_OSC_24M_CLK 0 > +#define IMX7D_PLL_ARM_MAIN 1 > +#define IMX7D_PLL_ARM_MAIN_CLK 2 > +#define IMX7D_PLL_ARM_MAIN_SRC 3 > +#define IMX7D_PLL_ARM_MAIN_BYPASS 4 > +#define IMX7D_PLL_SYS_MAIN 5 > +#define IMX7D_PLL_SYS_MAIN_CLK 6 > +#define IMX7D_PLL_SYS_MAIN_SRC 7 > +#define IMX7D_PLL_SYS_MAIN_BYPASS 8 > +#define IMX7D_PLL_SYS_MAIN_480M 9 > +#define IMX7D_PLL_SYS_MAIN_240M 10 > +#define IMX7D_PLL_SYS_MAIN_120M 11 > +#define IMX7D_PLL_SYS_MAIN_480M_CLK 12 > +#define IMX7D_PLL_SYS_MAIN_240M_CLK 13 > +#define IMX7D_PLL_SYS_MAIN_120M_CLK 14 > +#define IMX7D_PLL_SYS_PFD0_392M_CLK 15 > +#define IMX7D_PLL_SYS_PFD0_196M 16 > +#define IMX7D_PLL_SYS_PFD0_196M_CLK 17 > +#define IMX7D_PLL_SYS_PFD1_332M_CLK 18 > +#define IMX7D_PLL_SYS_PFD1_166M 19 > +#define IMX7D_PLL_SYS_PFD1_166M_CLK 20 > +#define IMX7D_PLL_SYS_PFD2_270M_CLK 21 > +#define IMX7D_PLL_SYS_PFD2_135M 22 > +#define IMX7D_PLL_SYS_PFD2_135M_CLK 23 > +#define IMX7D_PLL_SYS_PFD3_CLK 24 > +#define IMX7D_PLL_SYS_PFD4_CLK 25 > +#define IMX7D_PLL_SYS_PFD5_CLK 26 > +#define IMX7D_PLL_SYS_PFD6_CLK 27 > +#define IMX7D_PLL_SYS_PFD7_CLK 28 > +#define IMX7D_PLL_ENET_MAIN 29 > +#define IMX7D_PLL_ENET_MAIN_CLK 30 > +#define IMX7D_PLL_ENET_MAIN_SRC 31 > +#define IMX7D_PLL_ENET_MAIN_BYPASS 32 > +#define IMX7D_PLL_ENET_MAIN_500M 33 > +#define IMX7D_PLL_ENET_MAIN_250M 34 > +#define IMX7D_PLL_ENET_MAIN_125M 35 > +#define IMX7D_PLL_ENET_MAIN_100M 36 > +#define IMX7D_PLL_ENET_MAIN_50M 37 > +#define IMX7D_PLL_ENET_MAIN_40M 38 > +#define IMX7D_PLL_ENET_MAIN_25M 39 > +#define IMX7D_PLL_ENET_MAIN_500M_CLK 40 > +#define IMX7D_PLL_ENET_MAIN_250M_CLK 41 > +#define IMX7D_PLL_ENET_MAIN_125M_CLK 42 > +#define IMX7D_PLL_ENET_MAIN_100M_CLK 43 > +#define IMX7D_PLL_ENET_MAIN_50M_CLK 44 > +#define IMX7D_PLL_ENET_MAIN_40M_CLK 45 > +#define IMX7D_PLL_ENET_MAIN_25M_CLK 46 > +#define IMX7D_PLL_DRAM_MAIN 47 > +#define IMX7D_PLL_DRAM_MAIN_CLK 48 > +#define IMX7D_PLL_DRAM_MAIN_SRC 49 > +#define IMX7D_PLL_DRAM_MAIN_BYPASS 50 > +#define IMX7D_PLL_DRAM_MAIN_533M 51 > +#define IMX7D_PLL_DRAM_MAIN_533M_CLK 52 > +#define IMX7D_PLL_AUDIO_MAIN 53 > +#define IMX7D_PLL_AUDIO_MAIN_CLK 54 > +#define IMX7D_PLL_AUDIO_MAIN_SRC 55 > +#define IMX7D_PLL_AUDIO_MAIN_BYPASS 56 > +#define IMX7D_PLL_VIDEO_MAIN_CLK 57 > +#define IMX7D_PLL_VIDEO_MAIN 58 > +#define IMX7D_PLL_VIDEO_MAIN_SRC 59 > +#define IMX7D_PLL_VIDEO_MAIN_BYPASS 60 > +#define IMX7D_USB_MAIN_480M_CLK 61 > +#define IMX7D_ARM_A7_ROOT_CLK 62 > +#define IMX7D_ARM_A7_ROOT_SRC 63 > +#define IMX7D_ARM_A7_ROOT_CG 64 > +#define IMX7D_ARM_A7_ROOT_DIV 65 > +#define IMX7D_ARM_M4_ROOT_CLK 66 > +#define IMX7D_ARM_M4_ROOT_SRC 67 > +#define IMX7D_ARM_M4_ROOT_CG 68 > +#define IMX7D_ARM_M4_ROOT_DIV 69 > +#define IMX7D_ARM_M0_ROOT_CLK 70 > +#define IMX7D_ARM_M0_ROOT_SRC 71 > +#define IMX7D_ARM_M0_ROOT_CG 72 > +#define IMX7D_ARM_M0_ROOT_DIV 73 > +#define IMX7D_MAIN_AXI_ROOT_CLK 74 > +#define IMX7D_MAIN_AXI_ROOT_SRC 75 > +#define IMX7D_MAIN_AXI_ROOT_CG 76 > +#define IMX7D_MAIN_AXI_ROOT_DIV 77 > +#define IMX7D_DISP_AXI_ROOT_CLK 78 > +#define IMX7D_DISP_AXI_ROOT_SRC 79 > +#define IMX7D_DISP_AXI_ROOT_CG 80 > +#define IMX7D_DISP_AXI_ROOT_DIV 81 > +#define IMX7D_ENET_AXI_ROOT_CLK 82 > +#define IMX7D_ENET_AXI_ROOT_SRC 83 > +#define IMX7D_ENET_AXI_ROOT_CG 84 > +#define IMX7D_ENET_AXI_ROOT_DIV 85 > +#define IMX7D_NAND_USDHC_BUS_ROOT_CLK 86 > +#define IMX7D_NAND_USDHC_BUS_ROOT_SRC 87 > +#define IMX7D_NAND_USDHC_BUS_ROOT_CG 88 > +#define IMX7D_NAND_USDHC_BUS_ROOT_DIV 89 > +#define IMX7D_AHB_CHANNEL_ROOT_CLK 90 > +#define IMX7D_AHB_CHANNEL_ROOT_SRC 91 > +#define IMX7D_AHB_CHANNEL_ROOT_CG 92 > +#define IMX7D_AHB_CHANNEL_ROOT_DIV 93 > +#define IMX7D_DRAM_PHYM_ROOT_CLK 94 > +#define IMX7D_DRAM_PHYM_ROOT_SRC 95 > +#define IMX7D_DRAM_PHYM_ROOT_CG 96 > +#define IMX7D_DRAM_PHYM_ROOT_DIV 97 > +#define IMX7D_DRAM_ROOT_CLK 98 > +#define IMX7D_DRAM_ROOT_SRC 99 > +#define IMX7D_DRAM_ROOT_CG 100 > +#define IMX7D_DRAM_ROOT_DIV 101 > +#define IMX7D_DRAM_PHYM_ALT_ROOT_CLK 102 > +#define IMX7D_DRAM_PHYM_ALT_ROOT_SRC 103 > +#define IMX7D_DRAM_PHYM_ALT_ROOT_CG 104 > +#define IMX7D_DRAM_PHYM_ALT_ROOT_DIV 105 > +#define IMX7D_DRAM_ALT_ROOT_CLK 106 > +#define IMX7D_DRAM_ALT_ROOT_SRC 107 > +#define IMX7D_DRAM_ALT_ROOT_CG 108 > +#define IMX7D_DRAM_ALT_ROOT_DIV 109 > +#define IMX7D_USB_HSIC_ROOT_CLK 110 > +#define IMX7D_USB_HSIC_ROOT_SRC 111 > +#define IMX7D_USB_HSIC_ROOT_CG 112 > +#define IMX7D_USB_HSIC_ROOT_DIV 113 > +#define IMX7D_PCIE_CTRL_ROOT_CLK 114 > +#define IMX7D_PCIE_CTRL_ROOT_SRC 115 > +#define IMX7D_PCIE_CTRL_ROOT_CG 116 > +#define IMX7D_PCIE_CTRL_ROOT_DIV 117 > +#define IMX7D_PCIE_PHY_ROOT_CLK 118 > +#define IMX7D_PCIE_PHY_ROOT_SRC 119 > +#define IMX7D_PCIE_PHY_ROOT_CG 120 > +#define IMX7D_PCIE_PHY_ROOT_DIV 121 > +#define IMX7D_EPDC_PIXEL_ROOT_CLK 122 > +#define IMX7D_EPDC_PIXEL_ROOT_SRC 123 > +#define IMX7D_EPDC_PIXEL_ROOT_CG 124 > +#define IMX7D_EPDC_PIXEL_ROOT_DIV 125 > +#define IMX7D_LCDIF_PIXEL_ROOT_CLK 126 > +#define IMX7D_LCDIF_PIXEL_ROOT_SRC 127 > +#define IMX7D_LCDIF_PIXEL_ROOT_CG 128 > +#define IMX7D_LCDIF_PIXEL_ROOT_DIV 129 > +#define IMX7D_MIPI_DSI_ROOT_CLK 130 > +#define IMX7D_MIPI_DSI_ROOT_SRC 131 > +#define IMX7D_MIPI_DSI_ROOT_CG 132 > +#define IMX7D_MIPI_DSI_ROOT_DIV 133 > +#define IMX7D_MIPI_CSI_ROOT_CLK 134 > +#define IMX7D_MIPI_CSI_ROOT_SRC 135 > +#define IMX7D_MIPI_CSI_ROOT_CG 136 > +#define IMX7D_MIPI_CSI_ROOT_DIV 137 > +#define IMX7D_MIPI_DPHY_ROOT_CLK 138 > +#define IMX7D_MIPI_DPHY_ROOT_SRC 139 > +#define IMX7D_MIPI_DPHY_ROOT_CG 140 > +#define IMX7D_MIPI_DPHY_ROOT_DIV 141 > +#define IMX7D_SAI1_ROOT_CLK 142 > +#define IMX7D_SAI1_ROOT_SRC 143 > +#define IMX7D_SAI1_ROOT_CG 144 > +#define IMX7D_SAI1_ROOT_DIV 145 > +#define IMX7D_SAI2_ROOT_CLK 146 > +#define IMX7D_SAI2_ROOT_SRC 147 > +#define IMX7D_SAI2_ROOT_CG 148 > +#define IMX7D_SAI2_ROOT_DIV 149 > +#define IMX7D_SAI3_ROOT_CLK 150 > +#define IMX7D_SAI3_ROOT_SRC 151 > +#define IMX7D_SAI3_ROOT_CG 152 > +#define IMX7D_SAI3_ROOT_DIV 153 > +#define IMX7D_SPDIF_ROOT_CLK 154 > +#define IMX7D_SPDIF_ROOT_SRC 155 > +#define IMX7D_SPDIF_ROOT_CG 156 > +#define IMX7D_SPDIF_ROOT_DIV 157 > +#define IMX7D_ENET1_REF_ROOT_CLK 158 > +#define IMX7D_ENET1_REF_ROOT_SRC 159 > +#define IMX7D_ENET1_REF_ROOT_CG 160 > +#define IMX7D_ENET1_REF_ROOT_DIV 161 > +#define IMX7D_ENET1_TIME_ROOT_CLK 162 > +#define IMX7D_ENET1_TIME_ROOT_SRC 163 > +#define IMX7D_ENET1_TIME_ROOT_CG 164 > +#define IMX7D_ENET1_TIME_ROOT_DIV 165 > +#define IMX7D_ENET2_REF_ROOT_CLK 166 > +#define IMX7D_ENET2_REF_ROOT_SRC 167 > +#define IMX7D_ENET2_REF_ROOT_CG 168 > +#define IMX7D_ENET2_REF_ROOT_DIV 169 > +#define IMX7D_ENET2_TIME_ROOT_CLK 170 > +#define IMX7D_ENET2_TIME_ROOT_SRC 171 > +#define IMX7D_ENET2_TIME_ROOT_CG 172 > +#define IMX7D_ENET2_TIME_ROOT_DIV 173 > +#define IMX7D_ENET_PHY_REF_ROOT_CLK 174 > +#define IMX7D_ENET_PHY_REF_ROOT_SRC 175 > +#define IMX7D_ENET_PHY_REF_ROOT_CG 176 > +#define IMX7D_ENET_PHY_REF_ROOT_DIV 177 > +#define IMX7D_EIM_ROOT_CLK 178 > +#define IMX7D_EIM_ROOT_SRC 179 > +#define IMX7D_EIM_ROOT_CG 180 > +#define IMX7D_EIM_ROOT_DIV 181 > +#define IMX7D_NAND_ROOT_CLK 182 > +#define IMX7D_NAND_ROOT_SRC 183 > +#define IMX7D_NAND_ROOT_CG 184 > +#define IMX7D_NAND_ROOT_DIV 185 > +#define IMX7D_QSPI_ROOT_CLK 186 > +#define IMX7D_QSPI_ROOT_SRC 187 > +#define IMX7D_QSPI_ROOT_CG 188 > +#define IMX7D_QSPI_ROOT_DIV 189 > +#define IMX7D_USDHC1_ROOT_CLK 190 > +#define IMX7D_USDHC1_ROOT_SRC 191 > +#define IMX7D_USDHC1_ROOT_CG 192 > +#define IMX7D_USDHC1_ROOT_DIV 193 > +#define IMX7D_USDHC2_ROOT_CLK 194 > +#define IMX7D_USDHC2_ROOT_SRC 195 > +#define IMX7D_USDHC2_ROOT_CG 196 > +#define IMX7D_USDHC2_ROOT_DIV 197 > +#define IMX7D_USDHC3_ROOT_CLK 198 > +#define IMX7D_USDHC3_ROOT_SRC 199 > +#define IMX7D_USDHC3_ROOT_CG 200 > +#define IMX7D_USDHC3_ROOT_DIV 201 > +#define IMX7D_CAN1_ROOT_CLK 202 > +#define IMX7D_CAN1_ROOT_SRC 203 > +#define IMX7D_CAN1_ROOT_CG 204 > +#define IMX7D_CAN1_ROOT_DIV 205 > +#define IMX7D_CAN2_ROOT_CLK 206 > +#define IMX7D_CAN2_ROOT_SRC 207 > +#define IMX7D_CAN2_ROOT_CG 208 > +#define IMX7D_CAN2_ROOT_DIV 209 > +#define IMX7D_I2C1_ROOT_CLK 210 > +#define IMX7D_I2C1_ROOT_SRC 211 > +#define IMX7D_I2C1_ROOT_CG 212 > +#define IMX7D_I2C1_ROOT_DIV 213 > +#define IMX7D_I2C2_ROOT_CLK 214 > +#define IMX7D_I2C2_ROOT_SRC 215 > +#define IMX7D_I2C2_ROOT_CG 216 > +#define IMX7D_I2C2_ROOT_DIV 217 > +#define IMX7D_I2C3_ROOT_CLK 218 > +#define IMX7D_I2C3_ROOT_SRC 219 > +#define IMX7D_I2C3_ROOT_CG 220 > +#define IMX7D_I2C3_ROOT_DIV 221 > +#define IMX7D_I2C4_ROOT_CLK 222 > +#define IMX7D_I2C4_ROOT_SRC 223 > +#define IMX7D_I2C4_ROOT_CG 224 > +#define IMX7D_I2C4_ROOT_DIV 225 > +#define IMX7D_UART1_ROOT_CLK 226 > +#define IMX7D_UART1_ROOT_SRC 227 > +#define IMX7D_UART1_ROOT_CG 228 > +#define IMX7D_UART1_ROOT_DIV 229 > +#define IMX7D_UART2_ROOT_CLK 230 > +#define IMX7D_UART2_ROOT_SRC 231 > +#define IMX7D_UART2_ROOT_CG 232 > +#define IMX7D_UART2_ROOT_DIV 233 > +#define IMX7D_UART3_ROOT_CLK 234 > +#define IMX7D_UART3_ROOT_SRC 235 > +#define IMX7D_UART3_ROOT_CG 236 > +#define IMX7D_UART3_ROOT_DIV 237 > +#define IMX7D_UART4_ROOT_CLK 238 > +#define IMX7D_UART4_ROOT_SRC 239 > +#define IMX7D_UART4_ROOT_CG 240 > +#define IMX7D_UART4_ROOT_DIV 241 > +#define IMX7D_UART5_ROOT_CLK 242 > +#define IMX7D_UART5_ROOT_SRC 243 > +#define IMX7D_UART5_ROOT_CG 244 > +#define IMX7D_UART5_ROOT_DIV 245 > +#define IMX7D_UART6_ROOT_CLK 246 > +#define IMX7D_UART6_ROOT_SRC 247 > +#define IMX7D_UART6_ROOT_CG 248 > +#define IMX7D_UART6_ROOT_DIV 249 > +#define IMX7D_UART7_ROOT_CLK 250 > +#define IMX7D_UART7_ROOT_SRC 251 > +#define IMX7D_UART7_ROOT_CG 252 > +#define IMX7D_UART7_ROOT_DIV 253 > +#define IMX7D_ECSPI1_ROOT_CLK 254 > +#define IMX7D_ECSPI1_ROOT_SRC 255 > +#define IMX7D_ECSPI1_ROOT_CG 256 > +#define IMX7D_ECSPI1_ROOT_DIV 257 > +#define IMX7D_ECSPI2_ROOT_CLK 258 > +#define IMX7D_ECSPI2_ROOT_SRC 259 > +#define IMX7D_ECSPI2_ROOT_CG 260 > +#define IMX7D_ECSPI2_ROOT_DIV 261 > +#define IMX7D_ECSPI3_ROOT_CLK 262 > +#define IMX7D_ECSPI3_ROOT_SRC 263 > +#define IMX7D_ECSPI3_ROOT_CG 264 > +#define IMX7D_ECSPI3_ROOT_DIV 265 > +#define IMX7D_ECSPI4_ROOT_CLK 266 > +#define IMX7D_ECSPI4_ROOT_SRC 267 > +#define IMX7D_ECSPI4_ROOT_CG 268 > +#define IMX7D_ECSPI4_ROOT_DIV 269 > +#define IMX7D_PWM1_ROOT_CLK 270 > +#define IMX7D_PWM1_ROOT_SRC 271 > +#define IMX7D_PWM1_ROOT_CG 272 > +#define IMX7D_PWM1_ROOT_DIV 273 > +#define IMX7D_PWM2_ROOT_CLK 274 > +#define IMX7D_PWM2_ROOT_SRC 275 > +#define IMX7D_PWM2_ROOT_CG 276 > +#define IMX7D_PWM2_ROOT_DIV 277 > +#define IMX7D_PWM3_ROOT_CLK 278 > +#define IMX7D_PWM3_ROOT_SRC 279 > +#define IMX7D_PWM3_ROOT_CG 280 > +#define IMX7D_PWM3_ROOT_DIV 281 > +#define IMX7D_PWM4_ROOT_CLK 282 > +#define IMX7D_PWM4_ROOT_SRC 283 > +#define IMX7D_PWM4_ROOT_CG 284 > +#define IMX7D_PWM4_ROOT_DIV 285 > +#define IMX7D_FLEXTIMER1_ROOT_CLK 286 > +#define IMX7D_FLEXTIMER1_ROOT_SRC 287 > +#define IMX7D_FLEXTIMER1_ROOT_CG 288 > +#define IMX7D_FLEXTIMER1_ROOT_DIV 289 > +#define IMX7D_FLEXTIMER2_ROOT_CLK 290 > +#define IMX7D_FLEXTIMER2_ROOT_SRC 291 > +#define IMX7D_FLEXTIMER2_ROOT_CG 292 > +#define IMX7D_FLEXTIMER2_ROOT_DIV 293 > +#define IMX7D_SIM1_ROOT_CLK 294 > +#define IMX7D_SIM1_ROOT_SRC 295 > +#define IMX7D_SIM1_ROOT_CG 296 > +#define IMX7D_SIM1_ROOT_DIV 297 > +#define IMX7D_SIM2_ROOT_CLK 298 > +#define IMX7D_SIM2_ROOT_SRC 299 > +#define IMX7D_SIM2_ROOT_CG 300 > +#define IMX7D_SIM2_ROOT_DIV 301 > +#define IMX7D_GPT1_ROOT_CLK 302 > +#define IMX7D_GPT1_ROOT_SRC 303 > +#define IMX7D_GPT1_ROOT_CG 304 > +#define IMX7D_GPT1_ROOT_DIV 305 > +#define IMX7D_GPT2_ROOT_CLK 306 > +#define IMX7D_GPT2_ROOT_SRC 307 > +#define IMX7D_GPT2_ROOT_CG 308 > +#define IMX7D_GPT2_ROOT_DIV 309 > +#define IMX7D_GPT3_ROOT_CLK 310 > +#define IMX7D_GPT3_ROOT_SRC 311 > +#define IMX7D_GPT3_ROOT_CG 312 > +#define IMX7D_GPT3_ROOT_DIV 313 > +#define IMX7D_GPT4_ROOT_CLK 314 > +#define IMX7D_GPT4_ROOT_SRC 315 > +#define IMX7D_GPT4_ROOT_CG 316 > +#define IMX7D_GPT4_ROOT_DIV 317 > +#define IMX7D_TRACE_ROOT_CLK 318 > +#define IMX7D_TRACE_ROOT_SRC 319 > +#define IMX7D_TRACE_ROOT_CG 320 > +#define IMX7D_TRACE_ROOT_DIV 321 > +#define IMX7D_WDOG1_ROOT_CLK 322 > +#define IMX7D_WDOG_ROOT_SRC 323 > +#define IMX7D_WDOG_ROOT_CG 324 > +#define IMX7D_WDOG_ROOT_DIV 325 > +#define IMX7D_CSI_MCLK_ROOT_CLK 326 > +#define IMX7D_CSI_MCLK_ROOT_SRC 327 > +#define IMX7D_CSI_MCLK_ROOT_CG 328 > +#define IMX7D_CSI_MCLK_ROOT_DIV 329 > +#define IMX7D_AUDIO_MCLK_ROOT_CLK 330 > +#define IMX7D_AUDIO_MCLK_ROOT_SRC 331 > +#define IMX7D_AUDIO_MCLK_ROOT_CG 332 > +#define IMX7D_AUDIO_MCLK_ROOT_DIV 333 > +#define IMX7D_WRCLK_ROOT_CLK 334 > +#define IMX7D_WRCLK_ROOT_SRC 335 > +#define IMX7D_WRCLK_ROOT_CG 336 > +#define IMX7D_WRCLK_ROOT_DIV 337 > +#define IMX7D_CLKO1_ROOT_SRC 338 > +#define IMX7D_CLKO1_ROOT_CG 339 > +#define IMX7D_CLKO1_ROOT_DIV 340 > +#define IMX7D_CLKO2_ROOT_SRC 341 > +#define IMX7D_CLKO2_ROOT_CG 342 > +#define IMX7D_CLKO2_ROOT_DIV 343 > +#define IMX7D_MAIN_AXI_ROOT_PRE_DIV 344 > +#define IMX7D_DISP_AXI_ROOT_PRE_DIV 345 > +#define IMX7D_ENET_AXI_ROOT_PRE_DIV 346 > +#define IMX7D_NAND_USDHC_BUS_ROOT_PRE_DIV 347 > +#define IMX7D_AHB_CHANNEL_ROOT_PRE_DIV 348 > +#define IMX7D_USB_HSIC_ROOT_PRE_DIV 349 > +#define IMX7D_PCIE_CTRL_ROOT_PRE_DIV 350 > +#define IMX7D_PCIE_PHY_ROOT_PRE_DIV 351 > +#define IMX7D_EPDC_PIXEL_ROOT_PRE_DIV 352 > +#define IMX7D_LCDIF_PIXEL_ROOT_PRE_DIV 353 > +#define IMX7D_MIPI_DSI_ROOT_PRE_DIV 354 > +#define IMX7D_MIPI_CSI_ROOT_PRE_DIV 355 > +#define IMX7D_MIPI_DPHY_ROOT_PRE_DIV 356 > +#define IMX7D_SAI1_ROOT_PRE_DIV 357 > +#define IMX7D_SAI2_ROOT_PRE_DIV 358 > +#define IMX7D_SAI3_ROOT_PRE_DIV 359 > +#define IMX7D_SPDIF_ROOT_PRE_DIV 360 > +#define IMX7D_ENET1_REF_ROOT_PRE_DIV 361 > +#define IMX7D_ENET1_TIME_ROOT_PRE_DIV 362 > +#define IMX7D_ENET2_REF_ROOT_PRE_DIV 363 > +#define IMX7D_ENET2_TIME_ROOT_PRE_DIV 364 > +#define IMX7D_ENET_PHY_REF_ROOT_PRE_DIV 365 > +#define IMX7D_EIM_ROOT_PRE_DIV 366 > +#define IMX7D_NAND_ROOT_PRE_DIV 367 > +#define IMX7D_QSPI_ROOT_PRE_DIV 368 > +#define IMX7D_USDHC1_ROOT_PRE_DIV 369 > +#define IMX7D_USDHC2_ROOT_PRE_DIV 370 > +#define IMX7D_USDHC3_ROOT_PRE_DIV 371 > +#define IMX7D_CAN1_ROOT_PRE_DIV 372 > +#define IMX7D_CAN2_ROOT_PRE_DIV 373 > +#define IMX7D_I2C1_ROOT_PRE_DIV 374 > +#define IMX7D_I2C2_ROOT_PRE_DIV 375 > +#define IMX7D_I2C3_ROOT_PRE_DIV 376 > +#define IMX7D_I2C4_ROOT_PRE_DIV 377 > +#define IMX7D_UART1_ROOT_PRE_DIV 378 > +#define IMX7D_UART2_ROOT_PRE_DIV 379 > +#define IMX7D_UART3_ROOT_PRE_DIV 380 > +#define IMX7D_UART4_ROOT_PRE_DIV 381 > +#define IMX7D_UART5_ROOT_PRE_DIV 382 > +#define IMX7D_UART6_ROOT_PRE_DIV 383 > +#define IMX7D_UART7_ROOT_PRE_DIV 384 > +#define IMX7D_ECSPI1_ROOT_PRE_DIV 385 > +#define IMX7D_ECSPI2_ROOT_PRE_DIV 386 > +#define IMX7D_ECSPI3_ROOT_PRE_DIV 387 > +#define IMX7D_ECSPI4_ROOT_PRE_DIV 388 > +#define IMX7D_PWM1_ROOT_PRE_DIV 389 > +#define IMX7D_PWM2_ROOT_PRE_DIV 390 > +#define IMX7D_PWM3_ROOT_PRE_DIV 391 > +#define IMX7D_PWM4_ROOT_PRE_DIV 392 > +#define IMX7D_FLEXTIMER1_ROOT_PRE_DIV 393 > +#define IMX7D_FLEXTIMER2_ROOT_PRE_DIV 394 > +#define IMX7D_SIM1_ROOT_PRE_DIV 395 > +#define IMX7D_SIM2_ROOT_PRE_DIV 396 > +#define IMX7D_GPT1_ROOT_PRE_DIV 397 > +#define IMX7D_GPT2_ROOT_PRE_DIV 398 > +#define IMX7D_GPT3_ROOT_PRE_DIV 399 > +#define IMX7D_GPT4_ROOT_PRE_DIV 400 > +#define IMX7D_TRACE_ROOT_PRE_DIV 401 > +#define IMX7D_WDOG_ROOT_PRE_DIV 402 > +#define IMX7D_CSI_MCLK_ROOT_PRE_DIV 403 > +#define IMX7D_AUDIO_MCLK_ROOT_PRE_DIV 404 > +#define IMX7D_WRCLK_ROOT_PRE_DIV 405 > +#define IMX7D_CLKO1_ROOT_PRE_DIV 406 > +#define IMX7D_CLKO2_ROOT_PRE_DIV 407 > +#define IMX7D_DRAM_PHYM_ALT_ROOT_PRE_DIV 408 > +#define IMX7D_DRAM_ALT_ROOT_PRE_DIV 409 > +#define IMX7D_LVDS1_IN_CLK 410 > +#define IMX7D_LVDS1_OUT_SEL 411 > +#define IMX7D_LVDS1_OUT_CLK 412 > +#define IMX7D_CLK_DUMMY 413 > +#define IMX7D_GPT_3M_CLK 414 > +#define IMX7D_OCRAM_CLK 415 > +#define IMX7D_OCRAM_S_CLK 416 > +#define IMX7D_WDOG2_ROOT_CLK 417 > +#define IMX7D_WDOG3_ROOT_CLK 418 > +#define IMX7D_WDOG4_ROOT_CLK 419 > +#define IMX7D_SDMA_CORE_CLK 420 > +#define IMX7D_USB1_MAIN_480M_CLK 421 > +#define IMX7D_USB_CTRL_CLK 422 > +#define IMX7D_USB_PHY1_CLK 423 > +#define IMX7D_USB_PHY2_CLK 424 > +#define IMX7D_IPG_ROOT_CLK 425 > +#define IMX7D_SAI1_IPG_CLK 426 > +#define IMX7D_SAI2_IPG_CLK 427 > +#define IMX7D_SAI3_IPG_CLK 428 > +#define IMX7D_PLL_AUDIO_TEST_DIV 429 > +#define IMX7D_PLL_AUDIO_POST_DIV 430 > +#define IMX7D_PLL_VIDEO_TEST_DIV 431 > +#define IMX7D_PLL_VIDEO_POST_DIV 432 > +#define IMX7D_MU_ROOT_CLK 433 > +#define IMX7D_SEMA4_HS_ROOT_CLK 434 > +#define IMX7D_PLL_DRAM_TEST_DIV 435 > +#define IMX7D_ADC_ROOT_CLK 436 > +#define IMX7D_CLK_ARM 437 > +#define IMX7D_CKIL 438 > +#define IMX7D_OCOTP_CLK 439 > +#define IMX7D_CLK_END 440 > +#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */ > -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 24+ messages in thread
end of thread, other threads:[~2017-05-18 9:00 UTC | newest] Thread overview: 24+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2017-04-13 6:09 [U-Boot] [PATCH V2 01/12] arm: dts: imx7: sync with Linux Peng Fan 2017-04-13 6:09 ` [U-Boot] [PATCH V2 02/12] arm: dts: imx7d-sdb add basic dts Peng Fan 2017-04-13 6:09 ` [U-Boot] [PATCH V2 03/12] arm: dts: imx7d-sdb: add spi gpio node Peng Fan 2017-04-13 6:09 ` [U-Boot] [PATCH V2 04/12] arm: dts: imx7d-sdb: add regulator node for usb and mmc Peng Fan 2017-04-13 6:09 ` [U-Boot] [PATCH V2 05/12] arm: dts: imx7d-sdb: add i2c support Peng Fan 2017-04-13 6:09 ` [U-Boot] [PATCH V2 06/12] arm: dts: imx7d-sdb: add usdhc support Peng Fan 2017-04-13 6:09 ` [U-Boot] [PATCH V2 07/12] spi: kconfig: add soft spi Kconfig entry Peng Fan 2017-05-03 6:06 ` Jagan Teki 2017-05-08 2:47 ` Peng Fan 2017-04-13 6:09 ` [U-Boot] [PATCH V2 08/12] gpio: 74x164: make oe-pins optional Peng Fan 2017-04-16 19:32 ` Simon Glass 2017-04-13 6:09 ` [U-Boot] [PATCH V2 09/12] imx: mx7dsabresd: enable more DM drivers Peng Fan 2017-05-18 8:46 ` Stefano Babic 2017-04-13 6:09 ` [U-Boot] [PATCH V2 10/12] imx: mx7dsabresd: reset ENET_RST_B Peng Fan 2017-04-13 6:09 ` [U-Boot] [PATCH V2 11/12] imx: mx7dsabresd: switch to DM USB Peng Fan 2017-04-13 6:10 ` [U-Boot] [PATCH V2 12/12] imx: mx7dsabresd: add board revision check Peng Fan 2017-04-17 15:00 ` Fabio Estevam 2017-04-18 0:54 ` Peng Fan 2017-05-11 11:33 ` Stefano Babic 2017-05-11 12:52 ` Peng Fan 2017-05-18 8:19 ` Stefano Babic 2017-05-18 8:51 ` Peng Fan 2017-05-18 9:00 ` Stefano Babic 2017-05-11 11:35 ` [U-Boot] [PATCH V2 01/12] arm: dts: imx7: sync with Linux Stefano Babic
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