From mboxrd@z Thu Jan  1 00:00:00 1970
From: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Date: Thu, 8 Jun 2017 22:03:46 +0300
Subject: [U-Boot] [linux-sunxi] [PATCH v2 00/12] Big work on sunxi DW
 DRAM controllers and some new DDR type support
In-Reply-To: <20170603091025.11723-1-icenowy@aosc.io>
References: <20170603091025.11723-1-icenowy@aosc.io>
Message-ID: <20170608220346.7c499ff0@i7>
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On Sat,  3 Jun 2017 17:10:13 +0800
Icenowy Zheng <icenowy@aosc.io> wrote:

> This patchset contains several works on the sunxi DesignWare DRAM
> controllers.
> 
> The 1st patch made an option for H3-like DRAM controllers
> (DesignWare ones), which can ease further import of alike controllers.
> 
> The 2nd and 3rd patches are for supporting 16-bit DW DRAM controllers,
> in order to add V3s DRAM support (The controller on V3s is 16-bit).
> 
> The 4th patch adds bank detection code, in order to support some DDR2
> chips.
> 
> The 5th patch adds a framework for select DRAM type and timing -- it's
> needed for boards that use DRAM chips rather than DDR3.
> 
> The 6th patch enables dual rank detection in the DW DRAM code on SoCs
> except R40. For R40 the dual rank facility is still not so clear, so it's
> temporarily disabled.
> 
> The 7th~9th patches enables support for DRAM initialization and SPL for
> the V3s SoC, which integrates a DDR2 chip.
> 
> The 10th and 11th patches adds support for LPDDR3, with the stock boot0
> timing. (Seen in A83T boot0 source and some leaked H5/R40 libdram source)
> 
> The 12th patches adds a defconfig for SoPine w/ official baseboard, which
> utilizes LPDDR3.
> 
> Icenowy Zheng (12):
>   sunxi: makes an invisible option for H3-like DRAM controllers
>   sunxi: Rename bus-width related macros in H3 DRAM code
>   sunxi: add option for 16-bit DW DRAM controller
>   sunxi: add bank detection code to H3 DRAM initialization code
>   sunxi: Add selective DRAM type and timing
>   sunxi: enable dual rank detection in DesignWare-like DRAM code
>   sunxi: add support for the DDR2 in V3s SoC
>   sunxi: add support for V3s DRAM controller
>   sunxi: enable DRAM initialization and SPL for V3s SoC
>   sunxi: add LPDDR3 DRAM type support for DesignWare-like DRAM
>     controller
>   sunxi: add LPDDR3 timing from stock boot0
>   sunxi: add a defconfig for SoPine w/ official baseboard
> 
>  arch/arm/include/asm/arch-sunxi/dram.h             |   6 +-
>  .../{dram_sun8i_h3.h => dram_sunxi_dw.h}           |  36 +++-
>  arch/arm/mach-sunxi/Kconfig                        |  75 ++++++++-
>  arch/arm/mach-sunxi/Makefile                       |   5 +-
>  .../{dram_sun8i_h3.c => dram_sunxi_dw.c}           | 187 +++++++--------------
>  arch/arm/mach-sunxi/dram_timings/Makefile          |   3 +
>  arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c        |  84 +++++++++
>  arch/arm/mach-sunxi/dram_timings/ddr3_1333.c       |  87 ++++++++++
>  arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c    |  83 +++++++++
>  configs/sopine_baseboard_defconfig                 |  22 +++
>  10 files changed, 453 insertions(+), 135 deletions(-)
>  rename arch/arm/include/asm/arch-sunxi/{dram_sun8i_h3.h => dram_sunxi_dw.h} (86%)
>  rename arch/arm/mach-sunxi/{dram_sun8i_h3.c => dram_sunxi_dw.c} (84%)
>  create mode 100644 arch/arm/mach-sunxi/dram_timings/Makefile
>  create mode 100644 arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c
>  create mode 100644 arch/arm/mach-sunxi/dram_timings/ddr3_1333.c
>  create mode 100644 arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c
>  create mode 100644 configs/sopine_baseboard_defconfig
> 

I'll have time to review your patchset on the coming weekend. Thanks!

-- 
Best regards,
Siarhei Siamashka