From mboxrd@z Thu Jan 1 00:00:00 1970 From: Gautam Bhat Date: Mon, 3 Jul 2017 00:50:32 +0530 Subject: [U-Boot] [PATCH v3 1/1] mx7dsabresd: Set VLD04 output to 2.8V in PMIC initialization. In-Reply-To: <20170702192032.14840-1-mindentropy@gmail.com> References: <20170702192032.14840-1-mindentropy@gmail.com> Message-ID: <20170702192032.14840-2-mindentropy@gmail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de This change sets the VLDO4 settings output to 2.8V in PMIC initialization so that the MIPI DSI/CSI input voltage is 2.8V as per the schematics. The original code provides an output of 3.3V which violates the voltage mentioned in the schematics. Signed-off-by: Gautam Bhat --- Changes in v3: - Used pmic_clrsetbits for consistency. board/freescale/mx7dsabresd/mx7dsabresd.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c index ecea5a529a..7d22501d26 100644 --- a/board/freescale/mx7dsabresd/mx7dsabresd.c +++ b/board/freescale/mx7dsabresd/mx7dsabresd.c @@ -354,6 +354,12 @@ int power_init_board(void) pmic_clrsetbits(dev, PFUZE3000_LDOGCTL, 0, 1); + /* + * Set the voltage of VLDO4 output to 2.8V which feeds + * the MIPI DSI and MIPI CSI inputs. + */ + pmic_clrsetbits(dev, PFUZE3000_VLD4CTL, 0xF, 0xA); + return 0; } #endif -- 2.11.0