* [U-Boot] [PATCH v3 01/66] spl: add a 'return to bootrom' boot method
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
@ 2017-07-28 19:21 ` Philipp Tomsich
2017-07-28 19:21 ` [U-Boot] [PATCH v3 02/66] spl: configure 'return to bootrom' separately for SPL and TPL Philipp Tomsich
` (64 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:21 UTC (permalink / raw)
To: u-boot
Some devices (e.g. the RK3368) have only limited SRAM, but provide
support for loading the next boot stage after our SPL performs basic
setup (e.g. DRAM).
For target systems like these, we add a boot device BOOTROM that will
invoke a board-specific hook to return to the bootrom (if supported).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
Changes in v3: None
Changes in v2: None
arch/arm/include/asm/spl.h | 1 +
common/spl/Kconfig | 11 +++++++++++
common/spl/Makefile | 1 +
common/spl/spl_bootrom.c | 27 +++++++++++++++++++++++++++
include/spl.h | 10 ++++++++++
5 files changed, 50 insertions(+)
create mode 100644 common/spl/spl_bootrom.c
diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h
index 0e67470..df45511 100644
--- a/arch/arm/include/asm/spl.h
+++ b/arch/arm/include/asm/spl.h
@@ -30,6 +30,7 @@ enum {
BOOT_DEVICE_BOARD,
BOOT_DEVICE_DFU,
BOOT_DEVICE_XIP,
+ BOOT_DEVICE_BOOTROM,
BOOT_DEVICE_NONE
};
#endif
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 4de8139..ee767b7 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -25,6 +25,17 @@ config SPL_BOARD_INIT
spl_board_init() from board_init_r(). This function should be
provided by the board.
+config SPL_BOOTROM_SUPPORT
+ bool "Support returning to the BOOTROM"
+ help
+ Some platforms (e.g. the Rockchip RK3368) provide support in their
+ ROM for loading the next boot-stage after performing basic setup
+ from the SPL stage.
+
+ Enable this option, to return to the BOOTROM through the
+ BOOT_DEVICE_BOOTROM (or fall-through to the next boot device in the
+ boot device list, if not implemented for a given board)
+
config SPL_RAW_IMAGE_SUPPORT
bool "Support SPL loading and booting of RAW images"
default n if (ARCH_MX6 && (SPL_MMC_SUPPORT || SPL_SATA_SUPPORT))
diff --git a/common/spl/Makefile b/common/spl/Makefile
index 47a64dd..189b272 100644
--- a/common/spl/Makefile
+++ b/common/spl/Makefile
@@ -10,6 +10,7 @@
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_FRAMEWORK) += spl.o
+obj-$(CONFIG_SPL_BOOTROM_SUPPORT) += spl_bootrom.o
obj-$(CONFIG_SPL_LOAD_FIT) += spl_fit.o
obj-$(CONFIG_SPL_NOR_SUPPORT) += spl_nor.o
obj-$(CONFIG_SPL_XIP_SUPPORT) += spl_xip.o
diff --git a/common/spl/spl_bootrom.c b/common/spl/spl_bootrom.c
new file mode 100644
index 0000000..6804246
--- /dev/null
+++ b/common/spl/spl_bootrom.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2017 Theobroma Systems Design und Consulting GmH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+
+__weak void board_return_to_bootrom(void)
+{
+}
+
+static int spl_return_to_bootrom(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev)
+{
+ /*
+ * If the board implements a way to return to its ROM (with
+ * the expectation that the next stage of will be booted by
+ * the ROM), it will implement board_return_to_bootrom() and
+ * should not return from it.
+ */
+ board_return_to_bootrom();
+ return false;
+}
+
+SPL_LOAD_IMAGE_METHOD("BOOTROM", 0, BOOT_DEVICE_BOOTROM, spl_return_to_bootrom);
diff --git a/include/spl.h b/include/spl.h
index ccb1404..b5c2994 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -278,4 +278,14 @@ int spl_mmc_load_image(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev);
void bl31_entry(void);
+
+/**
+ * board_return_to_bootrom - allow for boards to continue with the boot ROM
+ *
+ * If a board (e.g. the Rockchip RK3368 boards) provide some
+ * supporting functionality for SPL in their boot ROM and the SPL
+ * stage wants to return to the ROM code to continue booting, boards
+ * can implement 'board_return_to_bootrom'.
+ */
+void board_return_to_bootrom(void);
#endif
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 02/66] spl: configure 'return to bootrom' separately for SPL and TPL
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
2017-07-28 19:21 ` [U-Boot] [PATCH v3 01/66] spl: add a 'return to bootrom' boot method Philipp Tomsich
@ 2017-07-28 19:21 ` Philipp Tomsich
2017-07-28 19:21 ` [U-Boot] [PATCH v3 03/66] rockchip: back-to-bootrom: add 'back-to-bootrom' support for AArch64 Philipp Tomsich
` (63 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:21 UTC (permalink / raw)
To: u-boot
On the RK3368, we want our TPL to use the 'return to bootrom' boot
method (to have the bootrom load up the SPL stage) and then continue
with different boot methods (MMC, SPI, etc.) from SPL.
This adds the config option needed to control the availabily of the
'return to bootrom' boot-method separately for the TPL stage.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
---
Changes in v3: None
Changes in v2: None
common/spl/Kconfig | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index ee767b7..dd94801 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -698,6 +698,17 @@ config TPL
if TPL
+config TPL_BOOTROM_SUPPORT
+ bool "Support returning to the BOOTROM (from TPL)"
+ help
+ Some platforms (e.g. the Rockchip RK3368) provide support in their
+ ROM for loading the next boot-stage after performing basic setup
+ from the TPL stage.
+
+ Enable this option, to return to the BOOTROM through the
+ BOOT_DEVICE_BOOTROM (or fall-through to the next boot device in the
+ boot device list, if not implemented for a given board)
+
config TPL_ENV_SUPPORT
bool "Support an environment"
help
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 03/66] rockchip: back-to-bootrom: add 'back-to-bootrom' support for AArch64
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
2017-07-28 19:21 ` [U-Boot] [PATCH v3 01/66] spl: add a 'return to bootrom' boot method Philipp Tomsich
2017-07-28 19:21 ` [U-Boot] [PATCH v3 02/66] spl: configure 'return to bootrom' separately for SPL and TPL Philipp Tomsich
@ 2017-07-28 19:21 ` Philipp Tomsich
2017-07-28 19:21 ` [U-Boot] [PATCH v3 04/66] rockchip: back-to-bootrom: split BACK_TO_BOOTROM for TPL/SPL Philipp Tomsich
` (62 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:21 UTC (permalink / raw)
To: u-boot
The back-to-bootrom support for Rockchip is equivalent to an
(assembly) implementation of setjmp/longjmp (i.e. it saves the
stack-pointer, link-register and callee-saved registers). Up until
now, this had only been implemented for AArch32 (i.e. ARMv7 or older),
which puts the new ARMv8 devices (which boot in AArch64 mode) at a
slight disadvantage.
To allow use of the 'back-to-bootrom' feature on new devices (e.g. the
RK3368), this commit adds an implementation for AArch64.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
---
Changes in v3: None
Changes in v2: None
arch/arm/mach-rockchip/save_boot_param.S | 37 ++++++++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/arch/arm/mach-rockchip/save_boot_param.S b/arch/arm/mach-rockchip/save_boot_param.S
index 5e6c8db..945a9dd 100644
--- a/arch/arm/mach-rockchip/save_boot_param.S
+++ b/arch/arm/mach-rockchip/save_boot_param.S
@@ -1,11 +1,47 @@
/*
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/linkage.h>
+#if defined(CONFIG_ARM64)
+.globl SAVE_SP_ADDR
+SAVE_SP_ADDR:
+ .quad 0
+
+ENTRY(save_boot_params)
+ sub sp, sp, #0x100
+ stp x29, x30, [sp, #0x50]
+ stp x27, x28, [sp, #0x40]
+ stp x25, x26, [sp, #0x30]
+ stp x23, x24, [sp, #0x20]
+ stp x21, x22, [sp, #0x10]
+ stp x19, x20, [sp, #0]
+ ldr x8, =SAVE_SP_ADDR
+ mov x9, sp
+ str x9, [x8]
+ b save_boot_params_ret /* back to my caller */
+ENDPROC(save_boot_params)
+
+.globl _back_to_bootrom_s
+ENTRY(_back_to_bootrom_s)
+ ldr x0, =SAVE_SP_ADDR
+ ldr x0, [x0]
+ mov sp, x0
+ ldp x29, x30, [sp, #0x50]
+ ldp x27, x28, [sp, #0x40]
+ ldp x25, x26, [sp, #0x30]
+ ldp x23, x24, [sp, #0x20]
+ ldp x21, x22, [sp, #0x10]
+ ldp x19, x20, [sp]
+ add sp, sp, #0x100
+ mov x0, xzr
+ ret
+ENDPROC(_back_to_bootrom_s)
+#else
.globl SAVE_SP_ADDR
SAVE_SP_ADDR:
.word 0
@@ -30,3 +66,4 @@ ENTRY(_back_to_bootrom_s)
mov r0, #0
pop {r1-r12, pc}
ENDPROC(_back_to_bootrom_s)
+#endif
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 04/66] rockchip: back-to-bootrom: split BACK_TO_BOOTROM for TPL/SPL
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (2 preceding siblings ...)
2017-07-28 19:21 ` [U-Boot] [PATCH v3 03/66] rockchip: back-to-bootrom: add 'back-to-bootrom' support for AArch64 Philipp Tomsich
@ 2017-07-28 19:21 ` Philipp Tomsich
2017-07-28 19:21 ` [U-Boot] [PATCH v3 05/66] rockchip: back-to-bootrom: simplify the #ifdef-check for LIBGENERIC in TPL/SPL Philipp Tomsich
` (61 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:21 UTC (permalink / raw)
To: u-boot
The back-to-bootrom option is rather unfortunately named
CONFIG_ROCKCHIP_SPL_BACK_TO_BOOTROM
instead of
CONFIG_SPL_ROCKCHIP_BACK_TO_BOOTROM
To make is selectable through CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BOOTROM),
we need to rename it. At the same time, we introduce a TPL_ variant of
the option to give us finer-grained control over when it should be used.
This change is motivated by our RK3368 boot process, which returns to
the boot ROM only from the TPL stage, but not from the SPL stage.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
---
Changes in v3: None
Changes in v2: None
arch/arm/mach-rockchip/Kconfig | 15 +++++++++++++--
arch/arm/mach-rockchip/rk3188-board-spl.c | 5 ++---
arch/arm/mach-rockchip/rk3188-board.c | 2 +-
arch/arm/mach-rockchip/rk3288-board-spl.c | 4 ++--
arch/arm/mach-rockchip/rk3288-board.c | 4 ++--
arch/arm/mach-rockchip/rk3399-board-spl.c | 4 ++--
configs/evb-rk3288_defconfig | 2 +-
configs/fennec-rk3288_defconfig | 2 +-
configs/firefly-rk3288_defconfig | 2 +-
configs/miqi-rk3288_defconfig | 2 +-
configs/popmetal-rk3288_defconfig | 2 +-
configs/rock2_defconfig | 2 +-
configs/rock_defconfig | 2 +-
configs/tinker-rk3288_defconfig | 2 +-
doc/README.rockchip | 2 +-
include/configs/rk3188_common.h | 2 +-
include/configs/rk3288_common.h | 2 +-
include/configs/rock.h | 2 +-
include/configs/rockchip-common.h | 2 +-
19 files changed, 35 insertions(+), 25 deletions(-)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index c924613..37885b8 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -101,10 +101,21 @@ config ROCKCHIP_RV1108
The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
and a DSP.
-config ROCKCHIP_SPL_BACK_TO_BROM
+config SPL_ROCKCHIP_BACK_TO_BROM
bool "SPL returns to bootrom"
default y if ROCKCHIP_RK3036
select ROCKCHIP_BROM_HELPER
+ depends on SPL
+ help
+ Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
+ SPL will return to the boot rom, which will then load the U-Boot
+ binary to keep going on.
+
+config TPL_ROCKCHIP_BACK_TO_BROM
+ bool "TPL returns to bootrom"
+ default y if ROCKCHIP_RK3368
+ select ROCKCHIP_BROM_HELPER
+ depends on TPL
help
Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
SPL will return to the boot rom, which will then load the U-Boot
@@ -122,7 +133,7 @@ config ROCKCHIP_BROM_HELPER
bool
config SPL_MMC_SUPPORT
- default y if !ROCKCHIP_SPL_BACK_TO_BROM
+ default y if !SPL_ROCKCHIP_BACK_TO_BROM
source "arch/arm/mach-rockchip/rk3036/Kconfig"
source "arch/arm/mach-rockchip/rk3188/Kconfig"
diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c b/arch/arm/mach-rockchip/rk3188-board-spl.c
index c3e174d..d3866bf 100644
--- a/arch/arm/mach-rockchip/rk3188-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3188-board-spl.c
@@ -167,8 +167,7 @@ void board_init_f(ulong dummy)
}
setup_arm_clock();
-
-#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
+#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
back_to_bootrom();
#endif
}
@@ -229,7 +228,7 @@ void spl_board_init(void)
}
preloader_console_init();
-#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
back_to_bootrom();
#endif
return;
diff --git a/arch/arm/mach-rockchip/rk3188-board.c b/arch/arm/mach-rockchip/rk3188-board.c
index 3e76100..622e046 100644
--- a/arch/arm/mach-rockchip/rk3188-board.c
+++ b/arch/arm/mach-rockchip/rk3188-board.c
@@ -39,7 +39,7 @@ int board_late_init(void)
int board_init(void)
{
-#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM)
+#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
struct udevice *pinctrl;
int ret;
diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c
index 5668fd2..6b7bf85 100644
--- a/arch/arm/mach-rockchip/rk3288-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
@@ -249,7 +249,7 @@ void board_init_f(ulong dummy)
debug("DRAM init failed: %d\n", ret);
return;
}
-#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
+#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
back_to_bootrom();
#endif
}
@@ -316,7 +316,7 @@ void spl_board_init(void)
}
preloader_console_init();
-#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
back_to_bootrom();
#endif
return;
diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c
index 613967c..272f079 100644
--- a/arch/arm/mach-rockchip/rk3288-board.c
+++ b/arch/arm/mach-rockchip/rk3288-board.c
@@ -78,7 +78,7 @@ int board_late_init(void)
return rk_board_late_init();
}
-#ifndef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
static int veyron_init(void)
{
struct udevice *dev;
@@ -115,7 +115,7 @@ static int veyron_init(void)
int board_init(void)
{
-#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
struct udevice *pinctrl;
int ret;
diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c
index e050aff..710f7fe 100644
--- a/arch/arm/mach-rockchip/rk3399-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3399-board-spl.c
@@ -28,7 +28,7 @@
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OF_CONTROL)
+#if CONFIG_IS_ENABLED(OF_CONTROL)
static int spl_node_to_boot_device(int node)
{
struct udevice *parent;
@@ -263,7 +263,7 @@ void spl_board_init(void)
}
preloader_console_init();
-#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
back_to_bootrom();
#endif
diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig
index 98addee..75c0c8b 100644
--- a/configs/evb-rk3288_defconfig
+++ b/configs/evb-rk3288_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3288=y
-CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
CONFIG_TARGET_EVB_RK3288=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-evb"
diff --git a/configs/fennec-rk3288_defconfig b/configs/fennec-rk3288_defconfig
index 9d2b319..2d68242 100644
--- a/configs/fennec-rk3288_defconfig
+++ b/configs/fennec-rk3288_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3288=y
-CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
CONFIG_TARGET_FENNEC_RK3288=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-fennec"
diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
index 1438f75..f0569a6 100644
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3288=y
-CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
CONFIG_TARGET_FIREFLY_RK3288=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-firefly"
diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig
index a7c796d..3dd1872 100644
--- a/configs/miqi-rk3288_defconfig
+++ b/configs/miqi-rk3288_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3288=y
-CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
CONFIG_TARGET_MIQI_RK3288=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-miqi"
diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig
index cfa2205..f68f988 100644
--- a/configs/popmetal-rk3288_defconfig
+++ b/configs/popmetal-rk3288_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3288=y
-CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
CONFIG_TARGET_POPMETAL_RK3288=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-popmetal"
diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig
index cca855c..570ff31 100644
--- a/configs/rock2_defconfig
+++ b/configs/rock2_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3288=y
-CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
CONFIG_TARGET_ROCK2=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-rock2-square"
diff --git a/configs/rock_defconfig b/configs/rock_defconfig
index 2ad6a6c..101b159 100644
--- a/configs/rock_defconfig
+++ b/configs/rock_defconfig
@@ -4,7 +4,7 @@ CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3188=y
-CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
CONFIG_TARGET_ROCK=y
CONFIG_SPL_STACK_R_ADDR=0x60080000
CONFIG_DEFAULT_DEVICE_TREE="rk3188-radxarock"
diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig
index be93799..7dde8ab 100644
--- a/configs/tinker-rk3288_defconfig
+++ b/configs/tinker-rk3288_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3288=y
-CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
CONFIG_TARGET_TINKER_RK3288=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-tinker"
diff --git a/doc/README.rockchip b/doc/README.rockchip
index dbeb8be..12fec38 100644
--- a/doc/README.rockchip
+++ b/doc/README.rockchip
@@ -130,7 +130,7 @@ load a second-level bootloader(ie. U-BOOT) as soon as it returns to bootrom.
Therefore RK3288 has another loading sequence like RK3036. The option of
U-Boot is controlled with this setting in U-Boot:
- #define CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+ #define CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
You can create the image via the following operations:
diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h
index 3ee9abd..8a01936 100644
--- a/include/configs/rk3188_common.h
+++ b/include/configs/rk3188_common.h
@@ -26,7 +26,7 @@
#define CONFIG_SYS_NS16550_MEM32
-#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+#ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
/* Bootrom will load u-boot binary to 0x60000000 once return from SPL */
#define CONFIG_SYS_TEXT_BASE 0x60000000
#else
diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index 488d679..ade6caf 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -24,7 +24,7 @@
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SYS_NS16550_MEM32
-#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+#ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
/* Bootrom will load u-boot binary to 0x0 once return from SPL */
#define CONFIG_SYS_TEXT_BASE 0x00000000
#else
diff --git a/include/configs/rock.h b/include/configs/rock.h
index e998ec5..676c009 100644
--- a/include/configs/rock.h
+++ b/include/configs/rock.h
@@ -12,7 +12,7 @@
#define CONFIG_SYS_MMC_ENV_DEV 0
-#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+#ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
/* SPL @ 32k for 34k
* u-boot directly after @ 68k for 400k or so
* ENV @ 992k
diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h
index bb4214c..c5ea990 100644
--- a/include/configs/rockchip-common.h
+++ b/include/configs/rockchip-common.h
@@ -47,7 +47,7 @@
#endif
#if !defined(CONFIG_ENV_OFFSET)
-#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+#ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
/* SPL @ 32k for 34k
* u-boot directly after @ 68k for 400k or so
* ENV @ 992k
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 05/66] rockchip: back-to-bootrom: simplify the #ifdef-check for LIBGENERIC in TPL/SPL
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (3 preceding siblings ...)
2017-07-28 19:21 ` [U-Boot] [PATCH v3 04/66] rockchip: back-to-bootrom: split BACK_TO_BOOTROM for TPL/SPL Philipp Tomsich
@ 2017-07-28 19:21 ` Philipp Tomsich
2017-08-01 7:30 ` Andy Yan
2017-07-28 19:21 ` [U-Boot] [PATCH v3 06/66] spl: adapts SYS_MALLOC_F_LEN for TPL Philipp Tomsich
` (60 subsequent siblings)
65 siblings, 1 reply; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:21 UTC (permalink / raw)
To: u-boot
With the finer-grained control over LIBGENERIC_SUPPORT for TPL/SPL (i.e.
with the newly introduced distinction between TPL_LIBGENERIC_SUPPORT and
SPL_LIBGENERIC_SUPPORT), we can simplify the #ifdef-check to simply use
CONFIG_IS_ENABELD.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
---
Changes in v3: None
Changes in v2: None
arch/arm/mach-rockchip/bootrom.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-rockchip/bootrom.c b/arch/arm/mach-rockchip/bootrom.c
index 4ca9962..4d38ed6 100644
--- a/arch/arm/mach-rockchip/bootrom.c
+++ b/arch/arm/mach-rockchip/bootrom.c
@@ -9,8 +9,8 @@
void back_to_bootrom(void)
{
-#if defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && !defined(CONFIG_TPL_BUILD)
- puts("Returning to boot ROM...");
+#if CONFIG_IS_ENABLED(LIBGENERIC_SUPPORT)
+ printf("Returning to boot ROM...\n");
#endif
_back_to_bootrom_s();
}
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 05/66] rockchip: back-to-bootrom: simplify the #ifdef-check for LIBGENERIC in TPL/SPL
2017-07-28 19:21 ` [U-Boot] [PATCH v3 05/66] rockchip: back-to-bootrom: simplify the #ifdef-check for LIBGENERIC in TPL/SPL Philipp Tomsich
@ 2017-08-01 7:30 ` Andy Yan
0 siblings, 0 replies; 95+ messages in thread
From: Andy Yan @ 2017-08-01 7:30 UTC (permalink / raw)
To: u-boot
Hi Philipp:
2017-07-29 3:21 GMT+08:00 Philipp Tomsich <
philipp.tomsich@theobroma-systems.com>:
> With the finer-grained control over LIBGENERIC_SUPPORT for TPL/SPL (i.e.
> with the newly introduced distinction between TPL_LIBGENERIC_SUPPORT and
> SPL_LIBGENERIC_SUPPORT), we can simplify the #ifdef-check to simply use
> CONFIG_IS_ENABELD.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Tom Rini <trini@konsulko.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
> arch/arm/mach-rockchip/bootrom.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-rockchip/bootrom.c b/arch/arm/mach-rockchip/
> bootrom.c
> index 4ca9962..4d38ed6 100644
> --- a/arch/arm/mach-rockchip/bootrom.c
> +++ b/arch/arm/mach-rockchip/bootrom.c
> @@ -9,8 +9,8 @@
>
> void back_to_bootrom(void)
> {
> -#if defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && !defined(CONFIG_TPL_BUILD)
> - puts("Returning to boot ROM...");
> +#if CONFIG_IS_ENABLED(LIBGENERIC_SUPPORT)
> + printf("Returning to boot ROM...\n");
>
We need to use puts here, or the code size will increase too much for sram
limited platform, like RK3036
> #endif
> _back_to_bootrom_s();
> }
> --
> 2.1.4
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot
>
^ permalink raw reply [flat|nested] 95+ messages in thread
* [U-Boot] [PATCH v3 06/66] spl: adapts SYS_MALLOC_F_LEN for TPL
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (4 preceding siblings ...)
2017-07-28 19:21 ` [U-Boot] [PATCH v3 05/66] rockchip: back-to-bootrom: simplify the #ifdef-check for LIBGENERIC in TPL/SPL Philipp Tomsich
@ 2017-07-28 19:21 ` Philipp Tomsich
2017-08-01 9:48 ` Simon Glass
2017-07-28 19:21 ` [U-Boot] [PATCH v3 07/66] spl: dm: Kconfig: fix help text for SPL/TPL confusion Philipp Tomsich
` (59 subsequent siblings)
65 siblings, 1 reply; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:21 UTC (permalink / raw)
To: u-boot
The (upstream) changes to break up SYS_MALLOC_F_LEN for the full
U-Boot and the SPL stage, break TPL (if simple malloc is enabled in
TPL).
This adds support for a TPL-variant of SYS_MALLOC_F_LEN:
- adds TPL_SYS_MALLOC_F_LEN
- rewrites a test for CONFIG_SPL_SYS_MALLOC_F_LEN to access
CONFIG_VAL(SYS_MALLOC_F_LEN)
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Version-changes: 3
- (new patch) adds changes to SYS_MALLOC_F_LEN for TPL to fix breakage
from rebasing to u-boot-rockchip/master
---
Changes in v3: None
Changes in v2: None
Kconfig | 12 +++++++++++-
common/spl/spl.c | 2 +-
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/Kconfig b/Kconfig
index c1451bc..27c64fe 100644
--- a/Kconfig
+++ b/Kconfig
@@ -96,7 +96,17 @@ config SYS_MALLOC_F_LEN
initial serial device and any others that are needed.
config SPL_SYS_MALLOC_F_LEN
- hex "Size of malloc() pool in spl before relocation"
+ hex "Size of malloc() pool in SPL before relocation"
+ depends on SYS_MALLOC_F
+ default SYS_MALLOC_F_LEN
+ help
+ Before relocation, memory is very limited on many platforms. Still,
+ we can provide a small malloc() pool if needed. Driver model in
+ particular needs this to operate, so that it can allocate the
+ initial serial device and any others that are needed.
+
+config TPL_SYS_MALLOC_F_LEN
+ hex "Size of malloc() pool in TPL before relocation"
depends on SYS_MALLOC_F
default SYS_MALLOC_F_LEN
help
diff --git a/common/spl/spl.c b/common/spl/spl.c
index b61993f..c84ffd8 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -487,7 +487,7 @@ ulong spl_relocate_stack_gd(void)
gd_t *new_gd;
ulong ptr = CONFIG_SPL_STACK_R_ADDR;
-#if defined(CONFIG_SPL_SYS_MALLOC_SIMPLE) && CONFIG_SPL_SYS_MALLOC_F_LEN
+#if defined(CONFIG_SPL_SYS_MALLOC_SIMPLE) && CONFIG_VAL(SYS_MALLOC_F_LEN)
if (CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN) {
ptr -= CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN;
gd->malloc_base = ptr;
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 06/66] spl: adapts SYS_MALLOC_F_LEN for TPL
2017-07-28 19:21 ` [U-Boot] [PATCH v3 06/66] spl: adapts SYS_MALLOC_F_LEN for TPL Philipp Tomsich
@ 2017-08-01 9:48 ` Simon Glass
0 siblings, 0 replies; 95+ messages in thread
From: Simon Glass @ 2017-08-01 9:48 UTC (permalink / raw)
To: u-boot
On 28 July 2017 at 13:21, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> The (upstream) changes to break up SYS_MALLOC_F_LEN for the full
> U-Boot and the SPL stage, break TPL (if simple malloc is enabled in
> TPL).
>
> This adds support for a TPL-variant of SYS_MALLOC_F_LEN:
> - adds TPL_SYS_MALLOC_F_LEN
> - rewrites a test for CONFIG_SPL_SYS_MALLOC_F_LEN to access
> CONFIG_VAL(SYS_MALLOC_F_LEN)
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>
> Version-changes: 3
> - (new patch) adds changes to SYS_MALLOC_F_LEN for TPL to fix breakage
> from rebasing to u-boot-rockchip/master
>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
> Kconfig | 12 +++++++++++-
> common/spl/spl.c | 2 +-
> 2 files changed, 12 insertions(+), 2 deletions(-)
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 95+ messages in thread
* [U-Boot] [PATCH v3 07/66] spl: dm: Kconfig: fix help text for SPL/TPL confusion
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (5 preceding siblings ...)
2017-07-28 19:21 ` [U-Boot] [PATCH v3 06/66] spl: adapts SYS_MALLOC_F_LEN for TPL Philipp Tomsich
@ 2017-07-28 19:21 ` Philipp Tomsich
2017-08-01 9:48 ` Simon Glass
2017-07-28 19:21 ` [U-Boot] [PATCH v3 08/66] spl: dm: Kconfig: use more specific prereqs for SPL_REGMAP and SPL_SYSCON Philipp Tomsich
` (58 subsequent siblings)
65 siblings, 1 reply; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:21 UTC (permalink / raw)
To: u-boot
TPL_NAND_SUPPORT, TPL_SERIAL_SUPPORT, TPL_SPI_FLASH_SUPPORT and
TPL_SPI_SUPPORT refer to SPL in their help text. This fixes up
the description to correctly reference TPL.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---
Changes in v3:
- (new patch) added fix-up of SPL/TPL confusion in help text
Changes in v2: None
common/spl/Kconfig | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index dd94801..8ce9c39 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -717,7 +717,7 @@ config TPL_ENV_SUPPORT
config TPL_I2C_SUPPORT
bool "Support I2C"
help
- Enable support for the I2C bus in SPL. See SPL_I2C_SUPPORT for
+ Enable support for the I2C bus in TPL. See SPL_I2C_SUPPORT for
details.
config TPL_LIBCOMMON_SUPPORT
@@ -747,24 +747,24 @@ config TPL_MMC_SUPPORT
config TPL_NAND_SUPPORT
bool "Support NAND flash"
help
- Enable support for NAND in SPL. See SPL_NAND_SUPPORT for details.
+ Enable support for NAND in TPL. See SPL_NAND_SUPPORT for details.
config TPL_SERIAL_SUPPORT
bool "Support serial"
help
- Enable support for serial in SPL. See SPL_SERIAL_SUPPORT for
+ Enable support for serial in TPL. See SPL_SERIAL_SUPPORT for
details.
config TPL_SPI_FLASH_SUPPORT
bool "Support SPI flash drivers"
help
- Enable support for using SPI flash in SPL. See SPL_SPI_FLASH_SUPPORT
+ Enable support for using SPI flash in TPL. See SPL_SPI_FLASH_SUPPORT
for details.
config TPL_SPI_SUPPORT
bool "Support SPI drivers"
help
- Enable support for using SPI in SPL. See SPL_SPI_SUPPORT for
+ Enable support for using SPI in TPL. See SPL_SPI_SUPPORT for
details.
endif # TPL
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 07/66] spl: dm: Kconfig: fix help text for SPL/TPL confusion
2017-07-28 19:21 ` [U-Boot] [PATCH v3 07/66] spl: dm: Kconfig: fix help text for SPL/TPL confusion Philipp Tomsich
@ 2017-08-01 9:48 ` Simon Glass
0 siblings, 0 replies; 95+ messages in thread
From: Simon Glass @ 2017-08-01 9:48 UTC (permalink / raw)
To: u-boot
On 28 July 2017 at 13:21, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> TPL_NAND_SUPPORT, TPL_SERIAL_SUPPORT, TPL_SPI_FLASH_SUPPORT and
> TPL_SPI_SUPPORT refer to SPL in their help text. This fixes up
> the description to correctly reference TPL.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>
> ---
>
> Changes in v3:
> - (new patch) added fix-up of SPL/TPL confusion in help text
>
> Changes in v2: None
>
> common/spl/Kconfig | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 95+ messages in thread
* [U-Boot] [PATCH v3 08/66] spl: dm: Kconfig: use more specific prereqs for SPL_REGMAP and SPL_SYSCON
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (6 preceding siblings ...)
2017-07-28 19:21 ` [U-Boot] [PATCH v3 07/66] spl: dm: Kconfig: fix help text for SPL/TPL confusion Philipp Tomsich
@ 2017-07-28 19:21 ` Philipp Tomsich
2017-07-28 19:21 ` [U-Boot] [PATCH v3 09/66] spl: dm: Kconfig: split REGMAP/SYSCON support for TPL from SPL Philipp Tomsich
` (57 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:21 UTC (permalink / raw)
To: u-boot
SPL_REGMAP and SPL_SYSCON were marked as depending on DM, when a
stricter dependency of SPL_DM was possible. This commit makes the
prereq more specific.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
---
Changes in v3: None
Changes in v2: None
drivers/core/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig
index f8b19a4..79a25c6 100644
--- a/drivers/core/Kconfig
+++ b/drivers/core/Kconfig
@@ -97,7 +97,7 @@ config REGMAP
config SPL_REGMAP
bool "Support register maps in SPL"
- depends on DM
+ depends on SPL_DM
help
Hardware peripherals tend to have one or more sets of registers
which can be accessed to control the hardware. A register map
@@ -116,7 +116,7 @@ config SYSCON
config SPL_SYSCON
bool "Support system controllers in SPL"
- depends on REGMAP
+ depends on SPL_REGMAP
help
Many SoCs have a number of system controllers which are dealt with
as a group by a single driver. Some common functionality is provided
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 09/66] spl: dm: Kconfig: split REGMAP/SYSCON support for TPL from SPL
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (7 preceding siblings ...)
2017-07-28 19:21 ` [U-Boot] [PATCH v3 08/66] spl: dm: Kconfig: use more specific prereqs for SPL_REGMAP and SPL_SYSCON Philipp Tomsich
@ 2017-07-28 19:21 ` Philipp Tomsich
2017-07-28 19:21 ` [U-Boot] [PATCH v3 10/66] spl: dm: Kconfig: SPL_RAM depends on SPL_DM Philipp Tomsich
` (56 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:21 UTC (permalink / raw)
To: u-boot
This change introduces TPL variants of the REGMAP and SYSCON config
options (i.e. TPL_REGMAP and TPL_SYSCON in analogy to SPL_REGMAP and
SPL_SYSCON) in preparation of a finer-grained feature selection for
building feature-rich TPL variants.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
---
Changes in v3: None
Changes in v2: None
drivers/core/Kconfig | 19 +++++++++++++++++++
drivers/core/Makefile | 4 ++--
2 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig
index 79a25c6..7afef1f 100644
--- a/drivers/core/Kconfig
+++ b/drivers/core/Kconfig
@@ -105,6 +105,16 @@ config SPL_REGMAP
support any bus type (I2C, SPI) but so far this only supports
direct memory access.
+config TPL_REGMAP
+ bool "Support register maps in TPL"
+ depends on TPL_DM
+ help
+ Hardware peripherals tend to have one or more sets of registers
+ which can be accessed to control the hardware. A register map
+ models this with a simple read/write interface. It can in principle
+ support any bus type (I2C, SPI) but so far this only supports
+ direct memory access.
+
config SYSCON
bool "Support system controllers"
depends on REGMAP
@@ -123,6 +133,15 @@ config SPL_SYSCON
by this uclass, including accessing registers via regmap and
assigning a unique number to each.
+config TPL_SYSCON
+ bool "Support system controllers in TPL"
+ depends on TPL_REGMAP
+ help
+ Many SoCs have a number of system controllers which are dealt with
+ as a group by a single driver. Some common functionality is provided
+ by this uclass, including accessing registers via regmap and
+ assigning a unique number to each.
+
config DEVRES
bool "Managed device resources"
depends on DM
diff --git a/drivers/core/Makefile b/drivers/core/Makefile
index fd2d4de..3d68c70 100644
--- a/drivers/core/Makefile
+++ b/drivers/core/Makefile
@@ -9,8 +9,8 @@ obj-$(CONFIG_DEVRES) += devres.o
obj-$(CONFIG_$(SPL_)DM_DEVICE_REMOVE) += device-remove.o
obj-$(CONFIG_$(SPL_)SIMPLE_BUS) += simple-bus.o
obj-$(CONFIG_DM) += dump.o
-obj-$(CONFIG_$(SPL_)REGMAP) += regmap.o
-obj-$(CONFIG_$(SPL_)SYSCON) += syscon-uclass.o
+obj-$(CONFIG_$(SPL_TPL_)REGMAP) += regmap.o
+obj-$(CONFIG_$(SPL_TPL_)SYSCON) += syscon-uclass.o
obj-$(CONFIG_OF_LIVE) += of_access.o of_addr.o
ifndef CONFIG_DM_DEV_READ_INLINE
obj-$(CONFIG_OF_CONTROL) += read.o
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 10/66] spl: dm: Kconfig: SPL_RAM depends on SPL_DM
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (8 preceding siblings ...)
2017-07-28 19:21 ` [U-Boot] [PATCH v3 09/66] spl: dm: Kconfig: split REGMAP/SYSCON support for TPL from SPL Philipp Tomsich
@ 2017-07-28 19:21 ` Philipp Tomsich
2017-07-28 19:21 ` [U-Boot] [PATCH v3 11/66] spl: dm: Kconfig: introduce TPL_RAM (in analogy to SPL_RAM) Philipp Tomsich
` (55 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:21 UTC (permalink / raw)
To: u-boot
This commit models the dependency from SPL_RAM to SPL_DM in Kconfig.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
---
Changes in v3: None
Changes in v2: None
drivers/ram/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index 61afd7a..e75c23f 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -10,7 +10,7 @@ config RAM
config SPL_RAM
bool "Enable RAM support in SPL"
- depends on RAM
+ depends on RAM && SPL_DM
help
The RAM subsystem adds a small amount of overhead to the image.
If this is acceptable and you have a need to use RAM drivers in
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 11/66] spl: dm: Kconfig: introduce TPL_RAM (in analogy to SPL_RAM)
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (9 preceding siblings ...)
2017-07-28 19:21 ` [U-Boot] [PATCH v3 10/66] spl: dm: Kconfig: SPL_RAM depends on SPL_DM Philipp Tomsich
@ 2017-07-28 19:21 ` Philipp Tomsich
2017-07-28 19:21 ` [U-Boot] [PATCH v3 12/66] spl: dm: Kconfig: SPL_CLK depends on SPL_DM Philipp Tomsich
` (54 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:21 UTC (permalink / raw)
To: u-boot
To allow finer grained selection of features for TPL, we introduce
TPL_RAM (in analogy to SPL_RAM).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
---
Changes in v3: None
Changes in v2: None
drivers/ram/Kconfig | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index e75c23f..836be25 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -17,6 +17,15 @@ config SPL_RAM
SPL, enable this option. It might provide a cleaner interface to
setting up RAM (e.g. SDRAM / DDR) within SPL.
+config TPL_RAM
+ bool "Enable RAM support in SPL"
+ depends on RAM && TPL_DM
+ help
+ The RAM subsystem adds a small amount of overhead to the image.
+ If this is acceptable and you have a need to use RAM drivers in
+ TPL, enable this option. It might provide a cleaner interface to
+ setting up RAM (e.g. SDRAM / DDR) within TPL.
+
config STM32_SDRAM
bool "Enable STM32 SDRAM support"
depends on RAM
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 12/66] spl: dm: Kconfig: SPL_CLK depends on SPL_DM
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (10 preceding siblings ...)
2017-07-28 19:21 ` [U-Boot] [PATCH v3 11/66] spl: dm: Kconfig: introduce TPL_RAM (in analogy to SPL_RAM) Philipp Tomsich
@ 2017-07-28 19:21 ` Philipp Tomsich
2017-07-28 19:21 ` [U-Boot] [PATCH v3 13/66] spl: dm: Kconfig: split CLK support for SPL and TPL Philipp Tomsich
` (53 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:21 UTC (permalink / raw)
To: u-boot
SPL_CLK should also depend on SPL_DM (and not just on CLK).
Add the additional dependency.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
---
Changes in v3: None
Changes in v2: None
drivers/clk/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 44da716..9c13587 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -12,7 +12,7 @@ config CLK
config SPL_CLK
bool "Enable clock support in SPL"
- depends on CLK
+ depends on CLK && SPL_DM
help
The clock subsystem adds a small amount of overhead to the image.
If this is acceptable and you have a need to use clock drivers in
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 13/66] spl: dm: Kconfig: split CLK support for SPL and TPL
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (11 preceding siblings ...)
2017-07-28 19:21 ` [U-Boot] [PATCH v3 12/66] spl: dm: Kconfig: SPL_CLK depends on SPL_DM Philipp Tomsich
@ 2017-07-28 19:21 ` Philipp Tomsich
2017-07-28 19:21 ` [U-Boot] [PATCH v3 14/66] spl: dm: Kconfig: split OF_CONTROL and OF_PLATDATA between " Philipp Tomsich
` (52 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:21 UTC (permalink / raw)
To: u-boot
Introduce TPL_CLK to allow finer-grained selection of TPL features
for feature-rich (i.e. DM-based) TPL stages.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
---
Changes in v3: None
Changes in v2: None
drivers/clk/Kconfig | 10 ++++++++++
drivers/clk/Makefile | 2 +-
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 9c13587..b40bde2 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -20,6 +20,16 @@ config SPL_CLK
setting up clocks within SPL, and allows the same drivers to be
used as U-Boot proper.
+config TPL_CLK
+ bool "Enable clock support in TPL"
+ depends on CLK && TPL_DM
+ help
+ The clock subsystem adds a small amount of overhead to the image.
+ If this is acceptable and you have a need to use clock drivers in
+ SPL, enable this option. It might provide a cleaner interface to
+ setting up clocks within TPL, and allows the same drivers to be
+ used as U-Boot proper.
+
config CLK_BCM6345
bool "Clock controller driver for BCM6345"
depends on CLK && ARCH_BMIPS
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 2746a80..844bc4e 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -5,7 +5,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_CLK) += clk-uclass.o clk_fixed_rate.o
+obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o clk_fixed_rate.o
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_SANDBOX) += clk_sandbox.o
obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 14/66] spl: dm: Kconfig: split OF_CONTROL and OF_PLATDATA between SPL and TPL
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (12 preceding siblings ...)
2017-07-28 19:21 ` [U-Boot] [PATCH v3 13/66] spl: dm: Kconfig: split CLK support for SPL and TPL Philipp Tomsich
@ 2017-07-28 19:21 ` Philipp Tomsich
2017-07-28 19:21 ` [U-Boot] [PATCH v3 15/66] spl: dm: use CONFIG_IS_ENABLED to test for the DM option Philipp Tomsich
` (51 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:21 UTC (permalink / raw)
To: u-boot
For the RK3368, we want to use OF_PLATDATA in TPL, but full OF_CONTROL
in SPL: this requires the introduction of a new family of
configuration options to decouple SPL_OF_CONTROL and SPL_OF_PLATDATA
from TPL.
Consequently, Makefile.spl needs to be adjusted to test for these
configuration items through the $(SPL_TPL_) macro instead of
hard-coding the SPL variant.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
---
Changes in v3: None
Changes in v2: None
Makefile | 2 +-
dts/Kconfig | 29 +++++++++++++++++++++++++++++
scripts/Makefile.spl | 4 ++--
3 files changed, 32 insertions(+), 3 deletions(-)
diff --git a/Makefile b/Makefile
index 3d2b66a..8d19a03 100644
--- a/Makefile
+++ b/Makefile
@@ -1398,7 +1398,7 @@ u-boot.lds: $(LDSCRIPT) prepare FORCE
spl/u-boot-spl.bin: spl/u-boot-spl
@:
spl/u-boot-spl: tools prepare \
- $(if $(CONFIG_OF_SEPARATE)$(CONFIG_SPL_OF_PLATDATA),dts/dt.dtb)
+ $(if $(CONFIG_OF_SEPARATE)$(CONFIG_$(SPL_TPL_)OF_PLATDATA),dts/dt.dtb)
$(Q)$(MAKE) obj=spl -f $(srctree)/scripts/Makefile.spl all
spl/sunxi-spl.bin: spl/u-boot-spl
diff --git a/dts/Kconfig b/dts/Kconfig
index 1bc9656..b4b7ddc 100644
--- a/dts/Kconfig
+++ b/dts/Kconfig
@@ -32,6 +32,14 @@ config SPL_OF_CONTROL
which is not enough to support device tree. Enable this option to
allow such boards to be supported by U-Boot SPL.
+config TPL_OF_CONTROL
+ bool "Enable run-time configuration via Device Tree in TPL"
+ depends on TPL && OF_CONTROL
+ help
+ Some boards use device tree in U-Boot but only have 4KB of SRAM
+ which is not enough to support device tree. Enable this option to
+ allow such boards to be supported by U-Boot TPL.
+
config OF_LIVE
bool "Enable use of a live tree"
depends on OF_CONTROL
@@ -136,4 +144,25 @@ config SPL_OF_PLATDATA
declarations for each node. See README.platdata for more
information.
+config TPL_OF_PLATDATA
+ bool "Generate platform data for use in TPL"
+ depends on TPL_OF_CONTROL
+ help
+ For very constrained SPL environments the overhead of decoding
+ device tree nodes and converting their contents into platform data
+ is too large. This overhead includes libfdt code as well as the
+ device tree contents itself. The latter is fairly compact, but the
+ former can add 3KB or more to a Thumb 2 Image.
+
+ This option enables generation of platform data from the device
+ tree as C code. This code creates devices using U_BOOT_DEVICE()
+ declarations. The benefit is that it allows driver code to access
+ the platform data directly in C structures, avoidin the libfdt
+ overhead.
+
+ This option works by generating C structure declarations for each
+ compatible string, then adding platform data and U_BOOT_DEVICE
+ declarations for each node. See README.platdata for more
+ information.
+
endmenu
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index ac3c2c7..3e35cd6 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -98,7 +98,7 @@ endif
u-boot-spl-init := $(head-y)
u-boot-spl-main := $(libs-y)
-ifdef CONFIG_SPL_OF_PLATDATA
+ifdef CONFIG_$(SPL_TPL_)OF_PLATDATA
u-boot-spl-platdata := $(obj)/dts/dt-platdata.o
endif
@@ -202,7 +202,7 @@ cmd_cat = cat $(filter-out $(PHONY), $^) > $@
quiet_cmd_copy = COPY $@
cmd_copy = cp $< $@
-ifeq ($(CONFIG_SPL_OF_CONTROL)$(CONFIG_OF_SEPARATE)$(CONFIG_SPL_OF_PLATDATA),yy)
+ifeq ($(CONFIG_$(SPL_TPL_)OF_CONTROL)$(CONFIG_OF_SEPARATE)$(CONFIG_$(SPL_TPL_)OF_PLATDATA),yy)
$(obj)/$(SPL_BIN)-dtb.bin: $(obj)/$(SPL_BIN)-nodtb.bin \
$(if $(CONFIG_SPL_SEPARATE_BSS),,$(obj)/$(SPL_BIN)-pad.bin) \
$(obj)/$(SPL_BIN).dtb FORCE
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 15/66] spl: dm: use CONFIG_IS_ENABLED to test for the DM option
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (13 preceding siblings ...)
2017-07-28 19:21 ` [U-Boot] [PATCH v3 14/66] spl: dm: Kconfig: split OF_CONTROL and OF_PLATDATA between " Philipp Tomsich
@ 2017-07-28 19:21 ` Philipp Tomsich
2017-07-28 19:21 ` [U-Boot] [PATCH v3 16/66] armv8: move low-level assembly functions into function-sections Philipp Tomsich
` (50 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:21 UTC (permalink / raw)
To: u-boot
Even though there's now a TPL_DM configuration option, the spl logic
still checks for SPL_DM and thus does not pick up the proper config
option.
This introduces the use of CONFIG_IS_ENABLED(DM) in spl.c to always
pick up the desired configuration option instead of having a
hard-coded check for the SPL variant.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
---
Changes in v3: None
Changes in v2: None
common/spl/spl.c | 5 +++--
include/linux/kconfig.h | 13 +++++++++++++
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/common/spl/spl.c b/common/spl/spl.c
index c84ffd8..4c7dd9e 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -6,6 +6,7 @@
*
* SPDX-License-Identifier: GPL-2.0+
*/
+
#include <common.h>
#include <dm.h>
#include <spl.h>
@@ -243,7 +244,7 @@ static int spl_common_init(bool setup_malloc)
return ret;
}
}
- if (IS_ENABLED(CONFIG_SPL_DM)) {
+ if (CONFIG_IS_ENABLED(DM)) {
bootstage_start(BOOTSTATE_ID_ACCUM_DM_SPL, "dm_spl");
/* With CONFIG_SPL_OF_PLATDATA, bring in all devices */
ret = dm_init_and_scan(!CONFIG_IS_ENABLED(OF_PLATDATA));
@@ -425,7 +426,7 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
gd->malloc_ptr / 1024);
#endif
- if (IS_ENABLED(CONFIG_SPL_ATF_SUPPORT)) {
+ if (CONFIG_IS_ENABLED(ATF_SUPPORT)) {
debug("loaded - jumping to U-Boot via ATF BL31.\n");
bl31_entry();
}
diff --git a/include/linux/kconfig.h b/include/linux/kconfig.h
index 486fb94..fbfc718 100644
--- a/include/linux/kconfig.h
+++ b/include/linux/kconfig.h
@@ -51,12 +51,25 @@
#define _IS_SPL 1
#endif
+#ifdef CONFIG_TPL_BUILD
+#define _IS_TPL 1
+#endif
+
+#if defined(CONFIG_TPL_BUILD)
+#define config_val(cfg) _config_val(_IS_TPL, cfg)
+#define _config_val(x, cfg) __config_val(x, cfg)
+#define __config_val(x, cfg) ___config_val(__ARG_PLACEHOLDER_##x, cfg)
+#define ___config_val(arg1_or_junk, cfg) \
+ ____config_val(arg1_or_junk CONFIG_TPL_##cfg, CONFIG_##cfg)
+#define ____config_val(__ignored, val, ...) val
+#else
#define config_val(cfg) _config_val(_IS_SPL, cfg)
#define _config_val(x, cfg) __config_val(x, cfg)
#define __config_val(x, cfg) ___config_val(__ARG_PLACEHOLDER_##x, cfg)
#define ___config_val(arg1_or_junk, cfg) \
____config_val(arg1_or_junk CONFIG_SPL_##cfg, CONFIG_##cfg)
#define ____config_val(__ignored, val, ...) val
+#endif
/*
* CONFIG_VAL(FOO) evaluates to the value of
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 16/66] armv8: move low-level assembly functions into function-sections
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (14 preceding siblings ...)
2017-07-28 19:21 ` [U-Boot] [PATCH v3 15/66] spl: dm: use CONFIG_IS_ENABLED to test for the DM option Philipp Tomsich
@ 2017-07-28 19:21 ` Philipp Tomsich
2017-08-01 9:49 ` Simon Glass
2017-07-28 19:21 ` [U-Boot] [PATCH v3 17/66] armv8: spl: Support separate stack for TPL Philipp Tomsich
` (49 subsequent siblings)
65 siblings, 1 reply; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:21 UTC (permalink / raw)
To: u-boot
TPL builds today don't need to call into firmware or set up the MMU
(if this changes, it should be controlled through a config option
whether to include this or not), but include the needed support code
for this anyway. By moving these unused low-level functions into
seperate function-sections, the linker can garbage-collect the unused
sections.
Note that (if DM support is enabled), there will be a call to the
cache-flushing code from alloc_priv(...) in drivers/core/device.c.
This then add 52 bytes of binary size (an increase from 20589 to 20641
bytes) compared to completely removing this code.
Even for a feature-rich TPL (including DM support as for the RK3368),
this equates to a size difference of significantly more than 10% in
TPL binary size.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---
Changes in v3:
- change to use function-sections (instead of disabling at the
Makefile-level for TPL builds) per Tom's suggestion
Changes in v2: None
arch/arm/cpu/armv8/Makefile | 2 +-
arch/arm/cpu/armv8/cache.S | 22 ++++++++++++++++++++++
arch/arm/cpu/armv8/tlb.S | 4 +++-
arch/arm/cpu/armv8/transition.S | 6 ++++++
4 files changed, 32 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index c447085..64f35f1 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -10,11 +10,11 @@ extra-y := start.o
obj-y += cpu.o
obj-y += generic_timer.o
obj-y += cache_v8.o
-obj-y += exceptions.o
obj-y += cache.o
obj-y += tlb.o
obj-y += transition.o
obj-y += fwcall.o
+obj-y += exceptions.o
obj-y += cpu-dt.o
obj-$(CONFIG_ARM_SMCCC) += smccc-call.o
diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S
index 7cba308..ea845d1 100644
--- a/arch/arm/cpu/armv8/cache.S
+++ b/arch/arm/cpu/armv8/cache.S
@@ -22,6 +22,7 @@
* x1: 0 clean & invalidate, 1 invalidate only
* x2~x9: clobbered
*/
+.pushsection .text.__asm_dcache_level, "ax"
ENTRY(__asm_dcache_level)
lsl x12, x0, #1
msr csselr_el1, x12 /* select cache level */
@@ -58,6 +59,7 @@ loop_way:
ret
ENDPROC(__asm_dcache_level)
+.popsection
/*
* void __asm_flush_dcache_all(int invalidate_only)
@@ -66,6 +68,7 @@ ENDPROC(__asm_dcache_level)
*
* flush or invalidate all data cache by SET/WAY.
*/
+.pushsection .text.__asm_dcache_all, "ax"
ENTRY(__asm_dcache_all)
mov x1, x0
dsb sy
@@ -102,16 +105,21 @@ skip:
finished:
ret
ENDPROC(__asm_dcache_all)
+.popsection
+.pushsection .text.__asm_flush_dcache_all, "ax"
ENTRY(__asm_flush_dcache_all)
mov x0, #0
b __asm_dcache_all
ENDPROC(__asm_flush_dcache_all)
+.popsection
+.pushsection .text.__asm_invalidate_dcache_all, "ax"
ENTRY(__asm_invalidate_dcache_all)
mov x0, #0x1
b __asm_dcache_all
ENDPROC(__asm_invalidate_dcache_all)
+.popsection
/*
* void __asm_flush_dcache_range(start, end)
@@ -121,6 +129,7 @@ ENDPROC(__asm_invalidate_dcache_all)
* x0: start address
* x1: end address
*/
+.pushsection .text.__asm_flush_dcache_range, "ax"
ENTRY(__asm_flush_dcache_range)
mrs x3, ctr_el0
lsr x3, x3, #16
@@ -138,6 +147,7 @@ ENTRY(__asm_flush_dcache_range)
dsb sy
ret
ENDPROC(__asm_flush_dcache_range)
+.popsection
/*
* void __asm_invalidate_dcache_range(start, end)
*
@@ -146,6 +156,7 @@ ENDPROC(__asm_flush_dcache_range)
* x0: start address
* x1: end address
*/
+.pushsection .text.__asm_invalidate_dcache_range, "ax"
ENTRY(__asm_invalidate_dcache_range)
mrs x3, ctr_el0
ubfm x3, x3, #16, #19
@@ -162,41 +173,51 @@ ENTRY(__asm_invalidate_dcache_range)
dsb sy
ret
ENDPROC(__asm_invalidate_dcache_range)
+.popsection
/*
* void __asm_invalidate_icache_all(void)
*
* invalidate all tlb entries.
*/
+.pushsection .text.__asm_invalidate_icache_all, "ax"
ENTRY(__asm_invalidate_icache_all)
ic ialluis
isb sy
ret
ENDPROC(__asm_invalidate_icache_all)
+.popsection
+.pushsection .text.__asm_invalidate_l3_dcache, "ax"
ENTRY(__asm_invalidate_l3_dcache)
mov x0, #0 /* return status as success */
ret
ENDPROC(__asm_invalidate_l3_dcache)
.weak __asm_invalidate_l3_dcache
+.popsection
+.pushsection .text.__asm_flush_l3_dcache, "ax"
ENTRY(__asm_flush_l3_dcache)
mov x0, #0 /* return status as success */
ret
ENDPROC(__asm_flush_l3_dcache)
.weak __asm_flush_l3_dcache
+.popsection
+.pushsection .text.__asm_invalidate_l3_icache, "ax"
ENTRY(__asm_invalidate_l3_icache)
mov x0, #0 /* return status as success */
ret
ENDPROC(__asm_invalidate_l3_icache)
.weak __asm_invalidate_l3_icache
+.popsection
/*
* void __asm_switch_ttbr(ulong new_ttbr)
*
* Safely switches to a new page table.
*/
+.pushsection .text.__asm_switch_ttbr, "ax"
ENTRY(__asm_switch_ttbr)
/* x2 = SCTLR (alive throghout the function) */
switch_el x4, 3f, 2f, 1f
@@ -244,3 +265,4 @@ ENTRY(__asm_switch_ttbr)
ret x3
ENDPROC(__asm_switch_ttbr)
+.popsection
diff --git a/arch/arm/cpu/armv8/tlb.S b/arch/arm/cpu/armv8/tlb.S
index 945445b..6743111 100644
--- a/arch/arm/cpu/armv8/tlb.S
+++ b/arch/arm/cpu/armv8/tlb.S
@@ -14,7 +14,8 @@
* void __asm_invalidate_tlb_all(void)
*
* invalidate all tlb entries.
- */
+*/
+.pushsection .text.__asm_invalidate_tlb_all, "ax"
ENTRY(__asm_invalidate_tlb_all)
switch_el x9, 3f, 2f, 1f
3: tlbi alle3
@@ -31,3 +32,4 @@ ENTRY(__asm_invalidate_tlb_all)
0:
ret
ENDPROC(__asm_invalidate_tlb_all)
+.popsection
diff --git a/arch/arm/cpu/armv8/transition.S b/arch/arm/cpu/armv8/transition.S
index ca07465..7aa6935 100644
--- a/arch/arm/cpu/armv8/transition.S
+++ b/arch/arm/cpu/armv8/transition.S
@@ -10,6 +10,7 @@
#include <linux/linkage.h>
#include <asm/macro.h>
+.pushsection .text.armv8_switch_to_el2, "ax"
ENTRY(armv8_switch_to_el2)
switch_el x6, 1f, 0f, 0f
0:
@@ -30,7 +31,9 @@ ENTRY(armv8_switch_to_el2)
br x4
1: armv8_switch_to_el2_m x4, x5, x6
ENDPROC(armv8_switch_to_el2)
+.popsection
+.pushsection .text.armv8_switch_to_el1, "ax"
ENTRY(armv8_switch_to_el1)
switch_el x6, 0f, 1f, 0f
0:
@@ -40,7 +43,10 @@ ENTRY(armv8_switch_to_el1)
br x4
1: armv8_switch_to_el1_m x4, x5, x6
ENDPROC(armv8_switch_to_el1)
+.popsection
+.pushsection .text.armv8_el2_to_aarch32, "ax"
WEAK(armv8_el2_to_aarch32)
ret
ENDPROC(armv8_el2_to_aarch32)
+.popsection
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 16/66] armv8: move low-level assembly functions into function-sections
2017-07-28 19:21 ` [U-Boot] [PATCH v3 16/66] armv8: move low-level assembly functions into function-sections Philipp Tomsich
@ 2017-08-01 9:49 ` Simon Glass
0 siblings, 0 replies; 95+ messages in thread
From: Simon Glass @ 2017-08-01 9:49 UTC (permalink / raw)
To: u-boot
On 28 July 2017 at 13:21, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> TPL builds today don't need to call into firmware or set up the MMU
> (if this changes, it should be controlled through a config option
> whether to include this or not), but include the needed support code
> for this anyway. By moving these unused low-level functions into
> seperate function-sections, the linker can garbage-collect the unused
> sections.
>
> Note that (if DM support is enabled), there will be a call to the
> cache-flushing code from alloc_priv(...) in drivers/core/device.c.
> This then add 52 bytes of binary size (an increase from 20589 to 20641
> bytes) compared to completely removing this code.
>
> Even for a feature-rich TPL (including DM support as for the RK3368),
> this equates to a size difference of significantly more than 10% in
> TPL binary size.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>
> ---
>
> Changes in v3:
> - change to use function-sections (instead of disabling at the
> Makefile-level for TPL builds) per Tom's suggestion
>
> Changes in v2: None
>
> arch/arm/cpu/armv8/Makefile | 2 +-
> arch/arm/cpu/armv8/cache.S | 22 ++++++++++++++++++++++
> arch/arm/cpu/armv8/tlb.S | 4 +++-
> arch/arm/cpu/armv8/transition.S | 6 ++++++
> 4 files changed, 32 insertions(+), 2 deletions(-)
>
Reviewed-by: Simon Glass <sjg@chromium.org>
> diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
> index c447085..64f35f1 100644
> --- a/arch/arm/cpu/armv8/Makefile
> +++ b/arch/arm/cpu/armv8/Makefile
> @@ -10,11 +10,11 @@ extra-y := start.o
> obj-y += cpu.o
> obj-y += generic_timer.o
> obj-y += cache_v8.o
> -obj-y += exceptions.o
> obj-y += cache.o
> obj-y += tlb.o
> obj-y += transition.o
> obj-y += fwcall.o
> +obj-y += exceptions.o
But what is happened here?
> obj-y += cpu-dt.o
> obj-$(CONFIG_ARM_SMCCC) += smccc-call.o
^ permalink raw reply [flat|nested] 95+ messages in thread
* [U-Boot] [PATCH v3 17/66] armv8: spl: Support separate stack for TPL
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (15 preceding siblings ...)
2017-07-28 19:21 ` [U-Boot] [PATCH v3 16/66] armv8: move low-level assembly functions into function-sections Philipp Tomsich
@ 2017-07-28 19:21 ` Philipp Tomsich
2017-07-28 19:21 ` [U-Boot] [PATCH v3 18/66] spl: allow a separate TEXT_BASE, LDSCRIPT and MAX_SIZE " Philipp Tomsich
` (48 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:21 UTC (permalink / raw)
To: u-boot
To allow a TPL and SPL to run from different addresses/memories, we
need to split setup of the TPL and SPL stacks. To do so, we introduce
CONFIG_TPL_STACK (not listed in Kconfig) which can be used to override
the initial stack pointer for TPL.
To provide backward compatibility for existing boards, this is added
as an optional configuration item and the normal search order (i.e.
SPL_STACK, then SYS_STACK) apply if not defined.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
---
Changes in v3: None
Changes in v2: None
arch/arm/lib/crt0_64.S | 4 +++-
scripts/config_whitelist.txt | 1 +
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S
index 57e728f..177b5bf 100644
--- a/arch/arm/lib/crt0_64.S
+++ b/arch/arm/lib/crt0_64.S
@@ -69,7 +69,9 @@ ENTRY(_main)
/*
* Set up initial C runtime environment and call board_init_f(0).
*/
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
+#if defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_STACK)
+ ldr x0, =(CONFIG_TPL_STACK)
+#elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
ldr x0, =(CONFIG_SPL_STACK)
#else
ldr x0, =(CONFIG_SYS_INIT_SP_ADDR)
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 93f0bf4..0a06dff 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -4983,6 +4983,7 @@ CONFIG_TI_SPI_MMAP
CONFIG_TMU_TIMER
CONFIG_TPL_DRIVERS_MISC_SUPPORT
CONFIG_TPL_PAD_TO
+CONFIG_TPL_STACK
CONFIG_TPM_TIS_BASE_ADDRESS
CONFIG_TPS6586X_POWER
CONFIG_TQM834X
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 18/66] spl: allow a separate TEXT_BASE, LDSCRIPT and MAX_SIZE for TPL
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (16 preceding siblings ...)
2017-07-28 19:21 ` [U-Boot] [PATCH v3 17/66] armv8: spl: Support separate stack for TPL Philipp Tomsich
@ 2017-07-28 19:21 ` Philipp Tomsich
2017-08-01 9:48 ` Simon Glass
2017-07-28 19:21 ` [U-Boot] [PATCH v3 19/66] spl: Kconfig: split SYS_MALLOC_SIMPLE for TPL and SPL Philipp Tomsich
` (47 subsequent siblings)
65 siblings, 1 reply; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:21 UTC (permalink / raw)
To: u-boot
For the bringup of the RK3368, we need to support TPL and SPL running
from different addresses... which requires both stages to use a
distinct TEXT_BASE.
This commit adds support for having a separate LDSCRIPT for TPL (which
is expected to make use of the TPL_MAX_SIZE define) and for having a
the option of defining TPL_TEXT_BASE and having the TPL stage linked
against this address.
Note that the handling of the TEXT_BASE is designed to not interfere
with the previous assumption that SPL_TEXT_BASE should be used for TPL
as well, unless TPL_TEXT_BASE is defined. For this reason, the test
in Makefile.spl uses the following (seemingly redundant checks):
1. looks for $(SPL_TPL_)TEXT_BASE
2. looks for SPL_TEXT_BASE (even when building in TPL)
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---
Changes in v3: None
Changes in v2: None
scripts/Makefile.spl | 10 ++++++++--
scripts/config_whitelist.txt | 3 +++
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 3e35cd6..4a9a58f 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -103,9 +103,9 @@ u-boot-spl-platdata := $(obj)/dts/dt-platdata.o
endif
# Linker Script
-ifdef CONFIG_SPL_LDSCRIPT
+ifdef CONFIG_$(SPL_TPL_)LDSCRIPT
# need to strip off double quotes
-LDSCRIPT := $(addprefix $(srctree)/,$(CONFIG_SPL_LDSCRIPT:"%"=%))
+LDSCRIPT := $(addprefix $(srctree)/,$(CONFIG_$(SPL_TPL_)LDSCRIPT:"%"=%))
endif
ifeq ($(wildcard $(LDSCRIPT)),)
@@ -293,9 +293,15 @@ LDFLAGS_$(SPL_BIN) += -T u-boot-spl.lds $(LDFLAGS_FINAL)
# Avoid 'Not enough room for program headers' error on binutils 2.28 onwards.
LDFLAGS_$(SPL_BIN) += $(call ld-option, --no-dynamic-linker)
+# First try the best-match (i.e. SPL_TEXT_BASE for SPL, TPL_TEXT_BASE for TPL)
+ifneq ($(CONFIG_$(SPL_TPL_)TEXT_BASE),)
+LDFLAGS_$(SPL_BIN) += -Ttext $(CONFIG_$(SPL_TPL_)TEXT_BASE)
+else
+# And then fall back to just testing for SPL_TEXT_BASE, even if in TPL mode
ifneq ($(CONFIG_SPL_TEXT_BASE),)
LDFLAGS_$(SPL_BIN) += -Ttext $(CONFIG_SPL_TEXT_BASE)
endif
+endif
MKIMAGEFLAGS_$(SPL_BIN).sfp = -T socfpgaimage
$(obj)/$(SPL_BIN).sfp: $(obj)/$(SPL_BIN).bin FORCE
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 0a06dff..e2f1797 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -4982,8 +4982,11 @@ CONFIG_TI_KSNAV
CONFIG_TI_SPI_MMAP
CONFIG_TMU_TIMER
CONFIG_TPL_DRIVERS_MISC_SUPPORT
+CONFIG_TPL_LDSCRIPT
+CONFIG_TPL_MAX_SIZE
CONFIG_TPL_PAD_TO
CONFIG_TPL_STACK
+CONFIG_TPL_TEXT_BASE
CONFIG_TPM_TIS_BASE_ADDRESS
CONFIG_TPS6586X_POWER
CONFIG_TQM834X
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 18/66] spl: allow a separate TEXT_BASE, LDSCRIPT and MAX_SIZE for TPL
2017-07-28 19:21 ` [U-Boot] [PATCH v3 18/66] spl: allow a separate TEXT_BASE, LDSCRIPT and MAX_SIZE " Philipp Tomsich
@ 2017-08-01 9:48 ` Simon Glass
0 siblings, 0 replies; 95+ messages in thread
From: Simon Glass @ 2017-08-01 9:48 UTC (permalink / raw)
To: u-boot
On 28 July 2017 at 13:21, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> For the bringup of the RK3368, we need to support TPL and SPL running
> from different addresses... which requires both stages to use a
> distinct TEXT_BASE.
>
> This commit adds support for having a separate LDSCRIPT for TPL (which
> is expected to make use of the TPL_MAX_SIZE define) and for having a
> the option of defining TPL_TEXT_BASE and having the TPL stage linked
> against this address.
>
> Note that the handling of the TEXT_BASE is designed to not interfere
> with the previous assumption that SPL_TEXT_BASE should be used for TPL
> as well, unless TPL_TEXT_BASE is defined. For this reason, the test
> in Makefile.spl uses the following (seemingly redundant checks):
> 1. looks for $(SPL_TPL_)TEXT_BASE
> 2. looks for SPL_TEXT_BASE (even when building in TPL)
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
> scripts/Makefile.spl | 10 ++++++++--
> scripts/config_whitelist.txt | 3 +++
> 2 files changed, 11 insertions(+), 2 deletions(-)
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 95+ messages in thread
* [U-Boot] [PATCH v3 19/66] spl: Kconfig: split SYS_MALLOC_SIMPLE for TPL and SPL
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (17 preceding siblings ...)
2017-07-28 19:21 ` [U-Boot] [PATCH v3 18/66] spl: allow a separate TEXT_BASE, LDSCRIPT and MAX_SIZE " Philipp Tomsich
@ 2017-07-28 19:21 ` Philipp Tomsich
2017-07-28 19:21 ` [U-Boot] [PATCH v3 20/66] lib: spl: differentiate between TPL and SPL for libfdt/of_control/of_platdata Philipp Tomsich
` (46 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:21 UTC (permalink / raw)
To: u-boot
As include/malloc.h already checks for SYS_MALLOC_SIMPLE using the
CONFIG_IS_ENABLED macro, we need to move to having separate entries
as we switch to fully separate configuration for SPL and TPL.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
---
Changes in v3: None
Changes in v2: None
common/spl/Kconfig | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 8ce9c39..ad7747e 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -62,6 +62,15 @@ config SPL_SYS_MALLOC_SIMPLE
this will make the SPL binary smaller at the cost of more heap
usage as the *_simple malloc functions do not re-use free-ed mem.
+config TPL_SYS_MALLOC_SIMPLE
+ bool
+ prompt "Only use malloc_simple functions in the TPL"
+ help
+ Say Y here to only use the *_simple malloc functions from
+ malloc_simple.c, rather then using the versions from dlmalloc.c;
+ this will make the TPL binary smaller at the cost of more heap
+ usage as the *_simple malloc functions do not re-use free-ed mem.
+
config SPL_STACK_R
bool "Enable SDRAM location for SPL stack"
help
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 20/66] lib: spl: differentiate between TPL and SPL for libfdt/of_control/of_platdata
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (18 preceding siblings ...)
2017-07-28 19:21 ` [U-Boot] [PATCH v3 19/66] spl: Kconfig: split SYS_MALLOC_SIMPLE for TPL and SPL Philipp Tomsich
@ 2017-07-28 19:21 ` Philipp Tomsich
2017-07-28 19:21 ` [U-Boot] [PATCH v3 21/66] spl: consistently use $(SPL_TPL_) to select features for SPL and TPL builds Philipp Tomsich
` (45 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:21 UTC (permalink / raw)
To: u-boot
This splits the compilation of code modules for TPL and SPL for
OF_CONTROL (and related) features between TPL and SPL. The typical
use-case of this is a TPL stage that uses OF_PLATDATA at TPL and
provides full OF_CONTROL at SPL (e.g. on the RK3368).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
---
Changes in v3: None
Changes in v2: None
lib/Makefile | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/lib/Makefile b/lib/Makefile
index eacc7d6..2eef1eb 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -49,11 +49,11 @@ obj-$(CONFIG_RSA) += rsa/
obj-$(CONFIG_SHA1) += sha1.o
obj-$(CONFIG_SHA256) += sha256.o
-obj-$(CONFIG_SPL_SAVEENV) += qsort.o
-obj-$(CONFIG_$(SPL_)OF_LIBFDT) += libfdt/
-ifneq ($(CONFIG_SPL_BUILD)$(CONFIG_SPL_OF_PLATDATA),yy)
-obj-$(CONFIG_$(SPL_)OF_CONTROL) += fdtdec_common.o
-obj-$(CONFIG_$(SPL_)OF_CONTROL) += fdtdec.o
+obj-$(CONFIG_$(SPL_TPL_)SAVEENV) += qsort.o
+obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += libfdt/
+ifneq ($(CONFIG_$(SPL_TPL_)BUILD)$(CONFIG_$(SPL_TPL_)OF_PLATDATA),yy)
+obj-$(CONFIG_$(SPL_TPL_)OF_CONTROL) += fdtdec_common.o
+obj-$(CONFIG_$(SPL_TPL_)OF_CONTROL) += fdtdec.o
endif
ifdef CONFIG_SPL_BUILD
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 21/66] spl: consistently use $(SPL_TPL_) to select features for SPL and TPL builds
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (19 preceding siblings ...)
2017-07-28 19:21 ` [U-Boot] [PATCH v3 20/66] lib: spl: differentiate between TPL and SPL for libfdt/of_control/of_platdata Philipp Tomsich
@ 2017-07-28 19:21 ` Philipp Tomsich
2017-07-28 19:21 ` [U-Boot] [PATCH v3 22/66] spl: add TPL_DRIVER_MISC_SUPPORT option Philipp Tomsich
` (44 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:21 UTC (permalink / raw)
To: u-boot
To allow for a finer-grained control of features for TPL and SPL
builds all modules/boot-methods/etc. need to be consistently selected
based on the $(SPL_TPL_) macros.
This allows splitting the associated config-options in Kconfig: we
don't split the Kconfig options here and now, as this should happen on
an as-needed basis, whenever someone needs a feature/boot-method/etc.
in their TPL.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
---
Changes in v3: None
Changes in v2: None
common/Makefile | 8 ++++----
common/spl/Makefile | 36 ++++++++++++++++++------------------
2 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/common/Makefile b/common/Makefile
index 60681c8..b388106 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -53,7 +53,7 @@ obj-$(CONFIG_ENV_IS_IN_UBI) += env_ubi.o
obj-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o
obj-$(CONFIG_CMD_BEDBUG) += bedbug.o
-obj-$(CONFIG_$(SPL_)OF_LIBFDT) += fdt_support.o
+obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += fdt_support.o
obj-$(CONFIG_MII) += miiphyutil.o
obj-$(CONFIG_CMD_MII) += miiphyutil.o
@@ -146,10 +146,10 @@ endif
endif
obj-y += image.o
obj-$(CONFIG_ANDROID_BOOT_IMAGE) += image-android.o
-obj-$(CONFIG_$(SPL_)OF_LIBFDT) += image-fdt.o
-obj-$(CONFIG_$(SPL_)FIT) += image-fit.o
+obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += image-fdt.o
+obj-$(CONFIG_$(SPL_TPL_)FIT) += image-fit.o
obj-$(CONFIG_FIT_EMBED) += boot_fit.o common_fit.o
-obj-$(CONFIG_$(SPL_)FIT_SIGNATURE) += image-sig.o
+obj-$(CONFIG_$(SPL_TPL_)FIT_SIGNATURE) += image-sig.o
obj-$(CONFIG_IO_TRACE) += iotrace.o
obj-y += memsize.o
obj-y += stdio.o
diff --git a/common/spl/Makefile b/common/spl/Makefile
index 189b272..112b3e6 100644
--- a/common/spl/Makefile
+++ b/common/spl/Makefile
@@ -10,24 +10,24 @@
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_FRAMEWORK) += spl.o
-obj-$(CONFIG_SPL_BOOTROM_SUPPORT) += spl_bootrom.o
-obj-$(CONFIG_SPL_LOAD_FIT) += spl_fit.o
-obj-$(CONFIG_SPL_NOR_SUPPORT) += spl_nor.o
-obj-$(CONFIG_SPL_XIP_SUPPORT) += spl_xip.o
-obj-$(CONFIG_SPL_YMODEM_SUPPORT) += spl_ymodem.o
+obj-$(CONFIG_$(SPL_TPL_)BOOTROM_SUPPORT) += spl_bootrom.o
+obj-$(CONFIG_$(SPL_TPL_)LOAD_FIT) += spl_fit.o
+obj-$(CONFIG_$(SPL_TPL_)SPL_NOR_SUPPORT) += spl_nor.o
+obj-$(CONFIG_$(SPL_TPL_)SPL_XIP_SUPPORT) += spl_xip.o
+obj-$(CONFIG_$(SPL_TPL_)SPL_YMODEM_SUPPORT) += spl_ymodem.o
ifndef CONFIG_SPL_UBI
-obj-$(CONFIG_SPL_NAND_SUPPORT) += spl_nand.o
-obj-$(CONFIG_SPL_ONENAND_SUPPORT) += spl_onenand.o
+obj-$(CONFIG_$(SPL_TPL_)NAND_SUPPORT) += spl_nand.o
+obj-$(CONFIG_$(SPL_TPL_)ONENAND_SUPPORT) += spl_onenand.o
endif
-obj-$(CONFIG_SPL_UBI) += spl_ubi.o
-obj-$(CONFIG_SPL_NET_SUPPORT) += spl_net.o
-obj-$(CONFIG_SPL_MMC_SUPPORT) += spl_mmc.o
-obj-$(CONFIG_SPL_ATF_SUPPORT) += spl_atf.o
-obj-$(CONFIG_SPL_USB_SUPPORT) += spl_usb.o
-obj-$(CONFIG_SPL_FAT_SUPPORT) += spl_fat.o
-obj-$(CONFIG_SPL_EXT_SUPPORT) += spl_ext.o
-obj-$(CONFIG_SPL_SATA_SUPPORT) += spl_sata.o
-obj-$(CONFIG_SPL_DFU_SUPPORT) += spl_dfu.o
-obj-$(CONFIG_SPL_SPI_LOAD) += spl_spi.o
-obj-$(CONFIG_SPL_RAM_SUPPORT) += spl_ram.o
+obj-$(CONFIG_$(SPL_TPL_)UBI) += spl_ubi.o
+obj-$(CONFIG_$(SPL_TPL_)NET_SUPPORT) += spl_net.o
+obj-$(CONFIG_$(SPL_TPL_)MMC_SUPPORT) += spl_mmc.o
+obj-$(CONFIG_$(SPL_TPL_)ATF_SUPPORT) += spl_atf.o
+obj-$(CONFIG_$(SPL_TPL_)USB_SUPPORT) += spl_usb.o
+obj-$(CONFIG_$(SPL_TPL_)FAT_SUPPORT) += spl_fat.o
+obj-$(CONFIG_$(SPL_TPL_)EXT_SUPPORT) += spl_ext.o
+obj-$(CONFIG_$(SPL_TPL_)SATA_SUPPORT) += spl_sata.o
+obj-$(CONFIG_$(SPL_TPL_)DFU_SUPPORT) += spl_dfu.o
+obj-$(CONFIG_$(SPL_TPL_)SPI_LOAD) += spl_spi.o
+obj-$(CONFIG_$(SPL_TPL_)RAM_SUPPORT) += spl_ram.o
endif
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 22/66] spl: add TPL_DRIVER_MISC_SUPPORT option
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (20 preceding siblings ...)
2017-07-28 19:21 ` [U-Boot] [PATCH v3 21/66] spl: consistently use $(SPL_TPL_) to select features for SPL and TPL builds Philipp Tomsich
@ 2017-07-28 19:21 ` Philipp Tomsich
2017-07-28 19:21 ` [U-Boot] [PATCH v3 23/66] drivers: spl: consistently use the $(SPL_TPL_) macro Philipp Tomsich
` (43 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:21 UTC (permalink / raw)
To: u-boot
This adds the TPL_DRIVER_MISC_SUPPORT option to allow activation of
DRIVER_MISC_SUPPORT for devices that need it in the TPL stage.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Version-changes: 3
- removes TPL_MISC_DRIVERS_SUPPORT from the whitelist
---
Changes in v3: None
Changes in v2: None
common/spl/Kconfig | 8 ++++++++
scripts/config_whitelist.txt | 1 -
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index ad7747e..64f9e1f 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -718,6 +718,14 @@ config TPL_BOOTROM_SUPPORT
BOOT_DEVICE_BOOTROM (or fall-through to the next boot device in the
boot device list, if not implemented for a given board)
+config TPL_DRIVERS_MISC_SUPPORT
+ bool "Support misc drivers in TPL"
+ help
+ Enable miscellaneous drivers in TPL. These drivers perform various
+ tasks that don't fall nicely into other categories, Enable this
+ option to build the drivers in drivers/misc as part of an TPL
+ build, for those that support building in TPL (not all drivers do).
+
config TPL_ENV_SUPPORT
bool "Support an environment"
help
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index e2f1797..ee3fcd0 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -4981,7 +4981,6 @@ CONFIG_TI_KEYSTONE_SERDES
CONFIG_TI_KSNAV
CONFIG_TI_SPI_MMAP
CONFIG_TMU_TIMER
-CONFIG_TPL_DRIVERS_MISC_SUPPORT
CONFIG_TPL_LDSCRIPT
CONFIG_TPL_MAX_SIZE
CONFIG_TPL_PAD_TO
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 23/66] drivers: spl: consistently use the $(SPL_TPL_) macro
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (21 preceding siblings ...)
2017-07-28 19:21 ` [U-Boot] [PATCH v3 22/66] spl: add TPL_DRIVER_MISC_SUPPORT option Philipp Tomsich
@ 2017-07-28 19:21 ` Philipp Tomsich
2017-07-28 19:21 ` [U-Boot] [PATCH v3 24/66] rockchip: Makefile: allow selective inclusion of sdram_common.o from TPL/SPL/U-Boot Philipp Tomsich
` (42 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:21 UTC (permalink / raw)
To: u-boot
To simplify drivers/Makefile a bit when using TPL/SPL, we consistently
use the $(SPL_TPL_) macro to test for drivers that have separate
configuration symbols for the full U-boot, SPL and TPL stages.
Instead of explicitly repeating them in two separate if-guarded
sections of the Makefile, we can now simply list these options once.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
---
Changes in v3: None
Changes in v2: None
drivers/Makefile | 36 ++++++++++++++++--------------------
1 file changed, 16 insertions(+), 20 deletions(-)
diff --git a/drivers/Makefile b/drivers/Makefile
index 8624bd8..b98550e 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -2,33 +2,34 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_$(SPL_TPL_)DM) += core/
-obj-$(CONFIG_$(SPL_)CLK) += clk/
-obj-$(CONFIG_$(SPL_)LED) += led/
-obj-$(CONFIG_$(SPL_)PHY) += phy/
-obj-$(CONFIG_$(SPL_)PINCTRL) += pinctrl/
-obj-$(CONFIG_$(SPL_)RAM) += ram/
+obj-$(CONFIG_$(SPL_TPL_)CLK) += clk/
+obj-$(CONFIG_$(SPL_TPL_)DM) += core/
+obj-$(CONFIG_$(SPL_TPL_)DRIVERS_MISC_SUPPORT) += misc/ sysreset/ firmware/
+obj-$(CONFIG_$(SPL_TPL_)I2C_SUPPORT) += i2c/
+obj-$(CONFIG_$(SPL_TPL_)LED) += led/
+obj-$(CONFIG_$(SPL_TPL_)MMC_SUPPORT) += mmc/
+obj-$(CONFIG_$(SPL_TPL_)NAND_SUPPORT) += mtd/nand/
+obj-$(CONFIG_$(SPL_TPL_)PHY) += phy/
+obj-$(CONFIG_$(SPL_TPL_)PINCTRL) += pinctrl/
+obj-$(CONFIG_$(SPL_TPL_)RAM) += ram/
+obj-$(CONFIG_$(SPL_TPL_)SERIAL_SUPPORT) += serial/
+obj-$(CONFIG_$(SPL_TPL_)SPI_FLASH_SUPPORT) += mtd/spi/
+obj-$(CONFIG_$(SPL_TPL_)SPI_SUPPORT) += spi/
+ifndef CONFIG_TPL_BUILD
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_CPU_SUPPORT) += cpu/
obj-$(CONFIG_SPL_CRYPTO_SUPPORT) += crypto/
-obj-$(CONFIG_SPL_I2C_SUPPORT) += i2c/
obj-$(CONFIG_SPL_GPIO_SUPPORT) += gpio/
-obj-$(CONFIG_SPL_MMC_SUPPORT) += mmc/
obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/
obj-$(CONFIG_ARMADA_38X) += ddr/marvell/a38x/
obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/
obj-$(CONFIG_ALTERA_SDRAM) += ddr/altera/
-obj-$(CONFIG_SPL_SERIAL_SUPPORT) += serial/
-obj-$(CONFIG_SPL_SPI_SUPPORT) += spi/
obj-$(CONFIG_SPL_POWER_SUPPORT) += power/ power/pmic/
obj-$(CONFIG_SPL_POWER_SUPPORT) += power/regulator/
-obj-$(CONFIG_SPL_DRIVERS_MISC_SUPPORT) += misc/ sysreset/ firmware/
obj-$(CONFIG_SPL_MTD_SUPPORT) += mtd/
-obj-$(CONFIG_SPL_NAND_SUPPORT) += mtd/nand/
obj-$(CONFIG_SPL_ONENAND_SUPPORT) += mtd/onenand/
-obj-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += mtd/spi/
obj-$(CONFIG_SPL_UBI) += mtd/ubispl/
obj-$(CONFIG_SPL_DMA_SUPPORT) += dma/
obj-$(CONFIG_SPL_ETH_SUPPORT) += net/
@@ -48,18 +49,13 @@ obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/
obj-$(CONFIG_SPL_SATA_SUPPORT) += ata/ scsi/
obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += block/
obj-$(CONFIG_SPL_MMC_SUPPORT) += block/
+
+endif
endif
ifdef CONFIG_TPL_BUILD
-obj-$(CONFIG_TPL_I2C_SUPPORT) += i2c/
-obj-$(CONFIG_TPL_DRIVERS_MISC_SUPPORT) += misc/ sysreset/ firmware/
-obj-$(CONFIG_TPL_MMC_SUPPORT) += mmc/
obj-$(CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/
-obj-$(CONFIG_TPL_NAND_SUPPORT) += mtd/nand/
-obj-$(CONFIG_TPL_SERIAL_SUPPORT) += serial/
-obj-$(CONFIG_TPL_SPI_FLASH_SUPPORT) += mtd/spi/
-obj-$(CONFIG_TPL_SPI_SUPPORT) += spi/
endif
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 24/66] rockchip: Makefile: allow selective inclusion of sdram_common.o from TPL/SPL/U-Boot
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (22 preceding siblings ...)
2017-07-28 19:21 ` [U-Boot] [PATCH v3 23/66] drivers: spl: consistently use the $(SPL_TPL_) macro Philipp Tomsich
@ 2017-07-28 19:21 ` Philipp Tomsich
2017-07-28 19:21 ` [U-Boot] [PATCH v3 25/66] rockchip: rk3368: improve Kconfig text for the RK3368 Philipp Tomsich
` (41 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:21 UTC (permalink / raw)
To: u-boot
The utility functions in sdram_common.c will be useful both for some
SPL implementations (and if unused, the linked will discard these
anyway) and for the full U-Boot stage.
This changes selects sdram_common.o through the $(SPL_TPL_) macro to
allow better control of its inclusion through the CONFIG_ROM,
CONFIG_SPL_RAM or CONFIG_TPL_RAM options.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
Changes in v3: None
Changes in v2: None
arch/arm/mach-rockchip/Makefile | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index cb8d3ef..8a3cb9f 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -5,6 +5,7 @@
#
obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
+obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o
ifdef CONFIG_TPL_BUILD
obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-tpl.o
@@ -21,9 +22,6 @@ obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o
obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board.o
obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o
obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o
-ifdef CONFIG_RAM
-obj-y += sdram_common.o
-endif
endif
ifndef CONFIG_ARM64
obj-y += rk_timer.o
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 25/66] rockchip: rk3368: improve Kconfig text for the RK3368
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (23 preceding siblings ...)
2017-07-28 19:21 ` [U-Boot] [PATCH v3 24/66] rockchip: Makefile: allow selective inclusion of sdram_common.o from TPL/SPL/U-Boot Philipp Tomsich
@ 2017-07-28 19:21 ` Philipp Tomsich
2017-07-28 19:21 ` [U-Boot] [PATCH v3 26/66] rockchip: rk3368: mkimage: add support " Philipp Tomsich
` (40 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:21 UTC (permalink / raw)
To: u-boot
The RK3368 option in Kconfig referred to the RK3328 (copy-and-paste)
and had a few typos and unnecessarily used UTF-8 characters. While
fixing this, I also reformatted and further clarified the text
(e.g. made the grouping into a a big and little cluster of 4 cores
each explicit).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
Changes in v3: None
Changes in v2: None
arch/arm/mach-rockchip/Kconfig | 15 +++++++++------
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 37885b8..8a89b51 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -69,12 +69,15 @@ config ROCKCHIP_RK3368
select ARM64
select SYS_NS16550
help
- The Rockchip RK3328 is a ARM-based SoC with a octa-core Cortex-A53.
- including NEON and GPU, 512KB L2 cache for big cluster and 256 KB
- L2 cache for little cluser, PowerVR G6110 based graphics, one video
- output processor supporting LVDS、HDMI、eDP, several DDR3 options
- and video codec support. Peripherals include Gigabit Ethernet,
- USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
+ The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
+ into a big and little cluster with 4 cores each) Cortex-A53 including
+ AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache
+ (for the little cluster), PowerVR G6110 based graphics, one video
+ output processor supporting LVDS/HDMI/eDP, several DDR3 options and
+ video codec support.
+
+ On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO,
+ I2S, UARTs, SPI, I2C and PWMs.
config ROCKCHIP_RK3399
bool "Support Rockchip RK3399"
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 26/66] rockchip: rk3368: mkimage: add support for the RK3368
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (24 preceding siblings ...)
2017-07-28 19:21 ` [U-Boot] [PATCH v3 25/66] rockchip: rk3368: improve Kconfig text for the RK3368 Philipp Tomsich
@ 2017-07-28 19:21 ` Philipp Tomsich
2017-07-28 19:21 ` [U-Boot] [PATCH v3 27/66] rockchip: rk3368: pmugrf: add definitions for os_reg[0..3] Philipp Tomsich
` (39 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:21 UTC (permalink / raw)
To: u-boot
This commit adds support for RK3368 SoC in mkimage.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
Changes in v3: None
Changes in v2: None
tools/rkcommon.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index 25b0340..04e8272 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -77,6 +77,7 @@ static struct spl_info spl_infos[] = {
{ "rk322x", "RK32", 0x8000 - 0x1000, false, false },
{ "rk3288", "RK32", 0x8000, false, false },
{ "rk3328", "RK32", 0x8000 - 0x1000, false, false },
+ { "rk3368", "RK33", 0x8000 - 0x1000, false, true },
{ "rk3399", "RK33", 0x30000 - 0x2000, false, true },
{ "rv1108", "RK11", 0x1800, false, false},
};
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 27/66] rockchip: rk3368: pmugrf: add definitions for os_reg[0..3]
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (25 preceding siblings ...)
2017-07-28 19:21 ` [U-Boot] [PATCH v3 26/66] rockchip: rk3368: mkimage: add support " Philipp Tomsich
@ 2017-07-28 19:21 ` Philipp Tomsich
2017-07-28 19:22 ` [U-Boot] [PATCH v3 28/66] rockchip: rk3368: spl: define COUNTER_FREQUENCY to 24MHz Philipp Tomsich
` (38 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:21 UTC (permalink / raw)
To: u-boot
On the RK3368 we use a TPL-stage similar to Rockchip's DDR init
(i.e. it initialises DRAM, leaves some info for the next stage and
returns to the BootROM). To allow compatibility with Rockchip's DDR
init code, we use the same register os_reg2 in pmugrf for passing
this info (i.e. DRAM size and configuration) between stages.
This change adds the definitions for os_reg[0] through os_reg[3] to
the pmugrf structure for the RK3368.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
Changes in v3: None
Changes in v2: None
arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
index 93c4e7d..a438f5d 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
@@ -92,10 +92,11 @@ struct rk3368_pmu_grf {
u32 gpio0d_drv;
u32 gpio0l_sr;
u32 gpio0h_sr;
- u32 reserved[(0x200 - 0x34) / 4 - 1];
+ u32 reserved[0x72];
u32 os_reg[4];
};
-check_member(rk3368_pmu_grf, os_reg[3], 0x20c);
+check_member(rk3368_pmu_grf, gpio0h_sr, 0x34);
+check_member(rk3368_pmu_grf, os_reg[0], 0x200);
/*GRF_GPIO0C_IOMUX*/
enum {
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 28/66] rockchip: rk3368: spl: define COUNTER_FREQUENCY to 24MHz
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (26 preceding siblings ...)
2017-07-28 19:21 ` [U-Boot] [PATCH v3 27/66] rockchip: rk3368: pmugrf: add definitions for os_reg[0..3] Philipp Tomsich
@ 2017-07-28 19:22 ` Philipp Tomsich
2017-07-28 19:22 ` [U-Boot] [PATCH v3 29/66] rockchip: rk3368: spl: add memory layout for TPL and SPL Philipp Tomsich
` (37 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:22 UTC (permalink / raw)
To: u-boot
The BootROM of the RK3368 Boot ROM does not initialise cntfrq_el0.
This change defines COUNTER_FREQUENCY, which is used by the AArch64 init
code in arch/arm/cpu/armv8/start.S to set up cntfrq_el0.
If the counter-frequency is not correctly set up, the calculation of
delays using the ARMv8 generic timer can not work correctly.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
Changes in v3: None
Changes in v2: None
include/configs/rk3368_common.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h
index b0c858c..ddb7df0 100644
--- a/include/configs/rk3368_common.h
+++ b/include/configs/rk3368_common.h
@@ -21,6 +21,8 @@
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SKIP_LOWLEVEL_INIT
+#define COUNTER_FREQUENCY 24000000
+
#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_SYS_TEXT_BASE 0x00200000
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 29/66] rockchip: rk3368: spl: add memory layout for TPL and SPL
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (27 preceding siblings ...)
2017-07-28 19:22 ` [U-Boot] [PATCH v3 28/66] rockchip: rk3368: spl: define COUNTER_FREQUENCY to 24MHz Philipp Tomsich
@ 2017-07-28 19:22 ` Philipp Tomsich
2017-07-28 19:22 ` [U-Boot] [PATCH v3 30/66] rockchip: rk3368: syscon: MSCH/PMUGRF/GRF support for OF_PLATDATA Philipp Tomsich
` (36 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:22 UTC (permalink / raw)
To: u-boot
For the RK3368, we use a multi-stage boot-process consisting of the
following:
1. TPL: initalises DRAM, returns to boot-ROM (which then loads
the next stage and transfers control to it)
2. SPL: a full-features SPL stage including OF_CONTROL and FIT
image loading, which fetches the ATF, DTB and full U-Boot
and then transfers control to the ATF (using the BL31
parameter block to indicate the location of BL33/U-Boot)
3. ATF: sets up the secure world and exits to BL33 (i.e. a full
U-Boot) in the normal world
4. full U-Boot
TPL/SPL and the full U-Boot are built from this tree and need to
run from distinct text addresses and with distinct initial stack
pointer addresses.
This commit sets up the configuration to run:
- TPL from the SRAM at 0xff8c0000 (note that the first 0x1000
are reserved for use by the boot-ROM and contain the SP
when the TPL is entered)
- SPL from DRAM at 0x0
- U-Boot from DRAM at 0x200000
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
Changes in v3: None
Changes in v2: None
include/configs/rk3368_common.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h
index ddb7df0..e35f4c0 100644
--- a/include/configs/rk3368_common.h
+++ b/include/configs/rk3368_common.h
@@ -29,6 +29,17 @@
#define CONFIG_SYS_INIT_SP_ADDR 0x00300000
#define CONFIG_SYS_LOAD_ADDR 0x00280000
+#define CONFIG_SPL_TEXT_BASE 0x00000000
+#define CONFIG_SPL_MAX_SIZE 0x40000
+#define CONFIG_SPL_BSS_START_ADDR 0x400000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x20000
+
+#define CONFIG_TPL_LDSCRIPT \
+ "arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds"
+#define CONFIG_TPL_TEXT_BASE 0xff8c1000
+#define CONFIG_TPL_MAX_SIZE 0x7000
+#define CONFIG_TPL_STACK 0xff8cffff
+
#define CONFIG_BOUNCE_BUFFER
#ifndef CONFIG_SPL_BUILD
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 30/66] rockchip: rk3368: syscon: MSCH/PMUGRF/GRF support for OF_PLATDATA
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (28 preceding siblings ...)
2017-07-28 19:22 ` [U-Boot] [PATCH v3 29/66] rockchip: rk3368: spl: add memory layout for TPL and SPL Philipp Tomsich
@ 2017-07-28 19:22 ` Philipp Tomsich
2017-07-28 19:22 ` [U-Boot] [PATCH v3 31/66] rockchip: rk3368: syscon: SGRF " Philipp Tomsich
` (35 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:22 UTC (permalink / raw)
To: u-boot
The RK3368 has both a limited TPL size (just 0x7000 bytes) and the
added challenge of booting in AArch64, which increases the code size
for TPL (particularily when using the LP64 programming model). For
this reason we expect the RK3368 to always use OF_PLATDATA for its
TPL stage.
This change adds support for the MSCH, PMUGRF and GRF register regions
in syscon, which are necessary for initialising the RK3368's DRAM
controller.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
Changes in v3:
- commit message now correctly refers to TPL
Changes in v2: None
arch/arm/mach-rockchip/rk3368/syscon_rk3368.c | 35 +++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c
index 03e97eb..90a993e 100644
--- a/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c
+++ b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c
@@ -1,6 +1,8 @@
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
* Author: Andy Yan <andy.yan@rock-chips.com>
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -14,6 +16,8 @@ static const struct udevice_id rk3368_syscon_ids[] = {
.data = ROCKCHIP_SYSCON_GRF },
{ .compatible = "rockchip,rk3368-pmugrf",
.data = ROCKCHIP_SYSCON_PMUGRF },
+ { .compatible = "rockchip,rk3368-msch",
+ .data = ROCKCHIP_SYSCON_MSCH },
{ }
};
@@ -22,3 +26,34 @@ U_BOOT_DRIVER(syscon_rk3368) = {
.id = UCLASS_SYSCON,
.of_match = rk3368_syscon_ids,
};
+
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+static int rk3368_syscon_bind_of_platdata(struct udevice *dev)
+{
+ dev->driver_data = dev->driver->of_match->data;
+ debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
+
+ return 0;
+}
+
+U_BOOT_DRIVER(rockchip_rk3368_grf) = {
+ .name = "rockchip_rk3368_grf",
+ .id = UCLASS_SYSCON,
+ .of_match = rk3368_syscon_ids,
+ .bind = rk3368_syscon_bind_of_platdata,
+};
+
+U_BOOT_DRIVER(rockchip_rk3368_pmugrf) = {
+ .name = "rockchip_rk3368_pmugrf",
+ .id = UCLASS_SYSCON,
+ .of_match = rk3368_syscon_ids + 1,
+ .bind = rk3368_syscon_bind_of_platdata,
+};
+
+U_BOOT_DRIVER(rockchip_rk3368_msch) = {
+ .name = "rockchip_rk3368_msch",
+ .id = UCLASS_SYSCON,
+ .of_match = rk3368_syscon_ids + 2,
+ .bind = rk3368_syscon_bind_of_platdata,
+};
+#endif
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 31/66] rockchip: rk3368: syscon: SGRF support for OF_PLATDATA
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (29 preceding siblings ...)
2017-07-28 19:22 ` [U-Boot] [PATCH v3 30/66] rockchip: rk3368: syscon: MSCH/PMUGRF/GRF support for OF_PLATDATA Philipp Tomsich
@ 2017-07-28 19:22 ` Philipp Tomsich
2017-08-01 9:48 ` Simon Glass
2017-07-28 19:22 ` [U-Boot] [PATCH v3 32/66] rockchip: rk3368: grf: use shifted-constants Philipp Tomsich
` (34 subsequent siblings)
65 siblings, 1 reply; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:22 UTC (permalink / raw)
To: u-boot
In TPL we will need to configure security in the SGRF of the RK3368.
This change adds support for the SGRF as a syscon device, so we can
retrieve its address range through the syscon API in TPL (and can
avoid having to hard-code the address).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---
Changes in v3:
- adds SGRF syscon support with OF_PLATDATA (to allow access to the
SGRF address range from TPL)
Changes in v2: None
arch/arm/mach-rockchip/rk3368/syscon_rk3368.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c
index 90a993e..99d51f0 100644
--- a/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c
+++ b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c
@@ -18,6 +18,8 @@ static const struct udevice_id rk3368_syscon_ids[] = {
.data = ROCKCHIP_SYSCON_PMUGRF },
{ .compatible = "rockchip,rk3368-msch",
.data = ROCKCHIP_SYSCON_MSCH },
+ { .compatible = "rockchip,rk3368-sgrf",
+ .data = ROCKCHIP_SYSCON_SGRF },
{ }
};
@@ -56,4 +58,11 @@ U_BOOT_DRIVER(rockchip_rk3368_msch) = {
.of_match = rk3368_syscon_ids + 2,
.bind = rk3368_syscon_bind_of_platdata,
};
+
+U_BOOT_DRIVER(rockchip_rk3368_sgrf) = {
+ .name = "rockchip_rk3368_sgrf",
+ .id = UCLASS_SYSCON,
+ .of_match = rk3368_syscon_ids + 3,
+ .bind = rk3368_syscon_bind_of_platdata,
+};
#endif
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 31/66] rockchip: rk3368: syscon: SGRF support for OF_PLATDATA
2017-07-28 19:22 ` [U-Boot] [PATCH v3 31/66] rockchip: rk3368: syscon: SGRF " Philipp Tomsich
@ 2017-08-01 9:48 ` Simon Glass
0 siblings, 0 replies; 95+ messages in thread
From: Simon Glass @ 2017-08-01 9:48 UTC (permalink / raw)
To: u-boot
On 28 July 2017 at 13:22, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> In TPL we will need to configure security in the SGRF of the RK3368.
> This change adds support for the SGRF as a syscon device, so we can
> retrieve its address range through the syscon API in TPL (and can
> avoid having to hard-code the address).
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>
> ---
>
> Changes in v3:
> - adds SGRF syscon support with OF_PLATDATA (to allow access to the
> SGRF address range from TPL)
>
> Changes in v2: None
>
> arch/arm/mach-rockchip/rk3368/syscon_rk3368.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 95+ messages in thread
* [U-Boot] [PATCH v3 32/66] rockchip: rk3368: grf: use shifted-constants
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (30 preceding siblings ...)
2017-07-28 19:22 ` [U-Boot] [PATCH v3 31/66] rockchip: rk3368: syscon: SGRF " Philipp Tomsich
@ 2017-07-28 19:22 ` Philipp Tomsich
2017-07-28 19:22 ` [U-Boot] [PATCH v3 33/66] rockchip: rk3368: dts: add sgrf node Philipp Tomsich
` (33 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:22 UTC (permalink / raw)
To: u-boot
The RK3368 GRF header was still defines with a shifted-mask but with
non-shifted function selectors for the IOMUX defines. As the RK3368
support is still fresh enough to allow a quick change, we do this now
before having more code use this.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---
Changes in v3: None
Changes in v2:
- dropped the RK3368_ prefix for the GRF constants
arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 441 ++++++++++++------------
drivers/pinctrl/rockchip/pinctrl_rk3368.c | 9 +-
2 files changed, 226 insertions(+), 224 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
index a438f5d..1966960 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
@@ -1,4 +1,6 @@
-/* (C) Copyright 2016 Rockchip Electronics Co., Ltd
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -100,315 +102,318 @@ check_member(rk3368_pmu_grf, os_reg[0], 0x200);
/*GRF_GPIO0C_IOMUX*/
enum {
- GPIO0C7_SHIFT = 14,
- GPIO0C7_MASK = 3 << GPIO0C7_SHIFT,
- GPIO0C7_GPIO = 0,
- GPIO0C7_LCDC_D19,
- GPIO0C7_TRACE_D9,
- GPIO0C7_UART1_RTSN,
-
- GPIO0C6_SHIFT = 12,
- GPIO0C6_MASK = 3 << GPIO0C6_SHIFT,
+ GPIO0C7_MASK = GENMASK(15, 14),
+ GPIO0C7_GPIO = 0,
+ GPIO0C7_LCDC_D19 = (1 << 14),
+ GPIO0C7_TRACE_D9 = (2 << 14),
+ GPIO0C7_UART1_RTSN = (3 << 14),
+
+ GPIO0C6_MASK = GENMASK(13, 12),
GPIO0C6_GPIO = 0,
- GPIO0C6_LCDC_D18,
- GPIO0C6_TRACE_D8,
- GPIO0C6_UART1_CTSN,
+ GPIO0C6_LCDC_D18 = (1 << 12),
+ GPIO0C6_TRACE_D8 = (2 << 12),
+ GPIO0C6_UART1_CTSN = (3 << 12),
- GPIO0C5_SHIFT = 10,
- GPIO0C5_MASK = 3 << GPIO0C5_SHIFT,
+ GPIO0C5_MASK = GENMASK(11, 10),
GPIO0C5_GPIO = 0,
- GPIO0C5_LCDC_D17,
- GPIO0C5_TRACE_D7,
- GPIO0C5_UART1_SOUT,
+ GPIO0C5_LCDC_D17 = (1 << 10),
+ GPIO0C5_TRACE_D7 = (2 << 10),
+ GPIO0C5_UART1_SOUT = (3 << 10),
- GPIO0C4_SHIFT = 8,
- GPIO0C4_MASK = 3 << GPIO0C4_SHIFT,
+ GPIO0C4_MASK = GENMASK(9, 8),
GPIO0C4_GPIO = 0,
- GPIO0C4_LCDC_D16,
- GPIO0C4_TRACE_D6,
- GPIO0C4_UART1_SIN,
+ GPIO0C4_LCDC_D16 = (1 << 8),
+ GPIO0C4_TRACE_D6 = (2 << 8),
+ GPIO0C4_UART1_SIN = (3 << 8),
- GPIO0C3_SHIFT = 6,
- GPIO0C3_MASK = 3 << GPIO0C3_SHIFT,
+ GPIO0C3_MASK = GENMASK(7, 6),
GPIO0C3_GPIO = 0,
- GPIO0C3_LCDC_D15,
- GPIO0C3_TRACE_D5,
- GPIO0C3_MCU_JTAG_TDO,
+ GPIO0C3_LCDC_D15 = (1 << 6),
+ GPIO0C3_TRACE_D5 = (2 << 6),
+ GPIO0C3_MCU_JTAG_TDO = (3 << 6),
- GPIO0C2_SHIFT = 4,
- GPIO0C2_MASK = 3 << GPIO0C2_SHIFT,
+ GPIO0C2_MASK = GENMASK(5, 4),
GPIO0C2_GPIO = 0,
- GPIO0C2_LCDC_D14,
- GPIO0C2_TRACE_D4,
- GPIO0C2_MCU_JTAG_TDI,
+ GPIO0C2_LCDC_D14 = (1 << 4),
+ GPIO0C2_TRACE_D4 = (2 << 4),
+ GPIO0C2_MCU_JTAG_TDI = (3 << 4),
- GPIO0C1_SHIFT = 2,
- GPIO0C1_MASK = 3 << GPIO0C1_SHIFT,
+ GPIO0C1_MASK = GENMASK(3, 2),
GPIO0C1_GPIO = 0,
- GPIO0C1_LCDC_D13,
- GPIO0C1_TRACE_D3,
- GPIO0C1_MCU_JTAG_TRTSN,
+ GPIO0C1_LCDC_D13 = (1 << 2),
+ GPIO0C1_TRACE_D3 = (2 << 2),
+ GPIO0C1_MCU_JTAG_TRTSN = (3 << 2),
- GPIO0C0_SHIFT = 0,
- GPIO0C0_MASK = 3 << GPIO0C0_SHIFT,
+ GPIO0C0_MASK = GENMASK(1, 0),
GPIO0C0_GPIO = 0,
- GPIO0C0_LCDC_D12,
- GPIO0C0_TRACE_D2,
- GPIO0C0_MCU_JTAG_TDO,
+ GPIO0C0_LCDC_D12 = (1 << 0),
+ GPIO0C0_TRACE_D2 = (2 << 0),
+ GPIO0C0_MCU_JTAG_TDO = (3 << 0),
};
/*GRF_GPIO0D_IOMUX*/
enum {
- GPIO0D7_SHIFT = 14,
- GPIO0D7_MASK = 3 << GPIO0D7_SHIFT,
+ GPIO0D7_MASK = GENMASK(15, 14),
GPIO0D7_GPIO = 0,
- GPIO0D7_LCDC_DCLK,
- GPIO0D7_TRACE_CTL,
- GPIO0D7_PMU_DEBUG5,
+ GPIO0D7_LCDC_DCLK = (1 << 14),
+ GPIO0D7_TRACE_CTL = (2 << 14),
+ GPIO0D7_PMU_DEBUG5 = (3 << 14),
- GPIO0D6_SHIFT = 12,
- GPIO0D6_MASK = 3 << GPIO0D6_SHIFT,
+ GPIO0D6_MASK = GENMASK(13, 12),
GPIO0D6_GPIO = 0,
- GPIO0D6_LCDC_DEN,
- GPIO0D6_TRACE_CLK,
- GPIO0D6_PMU_DEBUG4,
+ GPIO0D6_LCDC_DEN = (1 << 12),
+ GPIO0D6_TRACE_CLK = (2 << 12),
+ GPIO0D6_PMU_DEBUG4 = (3 << 12),
- GPIO0D5_SHIFT = 10,
- GPIO0D5_MASK = 3 << GPIO0D5_SHIFT,
+ GPIO0D5_MASK = GENMASK(11, 10),
GPIO0D5_GPIO = 0,
- GPIO0D5_LCDC_VSYNC,
- GPIO0D5_TRACE_D15,
- GPIO0D5_PMU_DEBUG3,
+ GPIO0D5_LCDC_VSYNC = (1 << 10),
+ GPIO0D5_TRACE_D15 = (2 << 10),
+ GPIO0D5_PMU_DEBUG3 = (3 << 10),
- GPIO0D4_SHIFT = 8,
- GPIO0D4_MASK = 3 << GPIO0D4_SHIFT,
+ GPIO0D4_MASK = GENMASK(9, 8),
GPIO0D4_GPIO = 0,
- GPIO0D4_LCDC_HSYNC,
- GPIO0D4_TRACE_D14,
- GPIO0D4_PMU_DEBUG2,
+ GPIO0D4_LCDC_HSYNC = (1 << 8),
+ GPIO0D4_TRACE_D14 = (2 << 8),
+ GPIO0D4_PMU_DEBUG2 = (3 << 8),
- GPIO0D3_SHIFT = 6,
- GPIO0D3_MASK = 3 << GPIO0D3_SHIFT,
+ GPIO0D3_MASK = GENMASK(7, 6),
GPIO0D3_GPIO = 0,
- GPIO0D3_LCDC_D23,
- GPIO0D3_TRACE_D13,
- GPIO0D3_UART4_SIN,
+ GPIO0D3_LCDC_D23 = (1 << 6),
+ GPIO0D3_TRACE_D13 = (2 << 6),
+ GPIO0D3_UART4_SIN = (3 << 6),
- GPIO0D2_SHIFT = 4,
- GPIO0D2_MASK = 3 << GPIO0D2_SHIFT,
+ GPIO0D2_MASK = GENMASK(5, 4),
GPIO0D2_GPIO = 0,
- GPIO0D2_LCDC_D22,
- GPIO0D2_TRACE_D12,
- GPIO0D2_UART4_SOUT,
+ GPIO0D2_LCDC_D22 = (1 << 4),
+ GPIO0D2_TRACE_D12 = (2 << 4),
+ GPIO0D2_UART4_SOUT = (3 << 4),
- GPIO0D1_SHIFT = 2,
- GPIO0D1_MASK = 3 << GPIO0D1_SHIFT,
+ GPIO0D1_MASK = GENMASK(3, 2),
GPIO0D1_GPIO = 0,
- GPIO0D1_LCDC_D21,
- GPIO0D1_TRACE_D11,
- GPIO0D1_UART4_RTSN,
+ GPIO0D1_LCDC_D21 = (1 << 2),
+ GPIO0D1_TRACE_D11 = (2 << 2),
+ GPIO0D1_UART4_RTSN = (3 << 2),
- GPIO0D0_SHIFT = 0,
- GPIO0D0_MASK = 3 << GPIO0D0_SHIFT,
+ GPIO0D0_MASK = GENMASK(1, 0),
GPIO0D0_GPIO = 0,
- GPIO0D0_LCDC_D20,
- GPIO0D0_TRACE_D10,
- GPIO0D0_UART4_CTSN,
+ GPIO0D0_LCDC_D20 = (1 << 0),
+ GPIO0D0_TRACE_D10 = (2 << 0),
+ GPIO0D0_UART4_CTSN = (3 << 0),
};
/*GRF_GPIO2A_IOMUX*/
enum {
- GPIO2A7_SHIFT = 14,
- GPIO2A7_MASK = 3 << GPIO2A7_SHIFT,
+ GPIO2A7_MASK = GENMASK(15, 14),
GPIO2A7_GPIO = 0,
- GPIO2A7_SDMMC0_D2,
- GPIO2A7_JTAG_TCK,
+ GPIO2A7_SDMMC0_D2 = (1 << 14),
+ GPIO2A7_JTAG_TCK = (2 << 14),
- GPIO2A6_SHIFT = 12,
- GPIO2A6_MASK = 3 << GPIO2A6_SHIFT,
+ GPIO2A6_MASK = GENMASK(13, 12),
GPIO2A6_GPIO = 0,
- GPIO2A6_SDMMC0_D1,
- GPIO2A6_UART2_SIN,
+ GPIO2A6_SDMMC0_D1 = (1 << 12),
+ GPIO2A6_UART2_SIN = (2 << 12),
- GPIO2A5_SHIFT = 10,
- GPIO2A5_MASK = 3 << GPIO2A5_SHIFT,
+ GPIO2A5_MASK = GENMASK(11, 10),
GPIO2A5_GPIO = 0,
- GPIO2A5_SDMMC0_D0,
- GPIO2A5_UART2_SOUT,
+ GPIO2A5_SDMMC0_D0 = (1 << 10),
+ GPIO2A5_UART2_SOUT = (2 << 10),
- GPIO2A4_SHIFT = 8,
- GPIO2A4_MASK = 3 << GPIO2A4_SHIFT,
- GPIO2A4_GPIO = 0,
- GPIO2A4_FLASH_DQS,
- GPIO2A4_EMMC_CLKO,
+ GPIO2A4_MASK = GENMASK(9, 8),
+ GPIO2A4_GPIO = 0,
+ GPIO2A4_FLASH_DQS = (1 << 8),
+ GPIO2A4_EMMC_CLKOUT = (2 << 8),
- GPIO2A3_SHIFT = 6,
- GPIO2A3_MASK = 3 << GPIO2A3_SHIFT,
+ GPIO2A3_MASK = GENMASK(7, 6),
GPIO2A3_GPIO = 0,
- GPIO2A3_FLASH_CSN3,
- GPIO2A3_EMMC_RSTNO,
+ GPIO2A3_FLASH_CSN3 = (1 << 6),
+ GPIO2A3_EMMC_RSTNOUT = (2 << 6),
- GPIO2A2_SHIFT = 4,
- GPIO2A2_MASK = 3 << GPIO2A2_SHIFT,
- GPIO2A2_GPIO = 0,
- GPIO2A2_FLASH_CSN2,
+ GPIO2A2_MASK = GENMASK(5, 4),
+ GPIO2A2_GPIO = 0,
+ GPIO2A2_FLASH_CSN2 = (1 << 4),
- GPIO2A1_SHIFT = 2,
- GPIO2A1_MASK = 3 << GPIO2A1_SHIFT,
+ GPIO2A1_MASK = GENMASK(3, 2),
GPIO2A1_GPIO = 0,
- GPIO2A1_FLASH_CSN1,
+ GPIO2A1_FLASH_CSN1 = (1 << 2),
- GPIO2A0_SHIFT = 0,
- GPIO2A0_MASK = 3 << GPIO2A0_SHIFT,
+ GPIO2A0_MASK = GENMASK(1, 0),
GPIO2A0_GPIO = 0,
- GPIO2A0_FLASH_CSN0,
+ GPIO2A0_FLASH_CSN0 = (1 << 0),
};
/*GRF_GPIO2D_IOMUX*/
enum {
- GPIO2D7_SHIFT = 14,
- GPIO2D7_MASK = 3 << GPIO2D7_SHIFT,
+ GPIO2D7_MASK = GENMASK(15, 14),
GPIO2D7_GPIO = 0,
- GPIO2D7_SDIO0_D3,
+ GPIO2D7_SDIO0_D3 = (1 << 14),
- GPIO2D6_SHIFT = 12,
- GPIO2D6_MASK = 3 << GPIO2D6_SHIFT,
+ GPIO2D6_MASK = GENMASK(13, 12),
GPIO2D6_GPIO = 0,
- GPIO2D6_SDIO0_D2,
+ GPIO2D6_SDIO0_D2 = (1 << 12),
- GPIO2D5_SHIFT = 10,
- GPIO2D5_MASK = 3 << GPIO2D5_SHIFT,
+ GPIO2D5_MASK = GENMASK(11, 10),
GPIO2D5_GPIO = 0,
- GPIO2D5_SDIO0_D1,
+ GPIO2D5_SDIO0_D1 = (1 << 10),
- GPIO2D4_SHIFT = 8,
- GPIO2D4_MASK = 3 << GPIO2D4_SHIFT,
+ GPIO2D4_MASK = GENMASK(9, 8),
GPIO2D4_GPIO = 0,
- GPIO2D4_SDIO0_D0,
+ GPIO2D4_SDIO0_D0 = (1 << 8),
- GPIO2D3_SHIFT = 6,
- GPIO2D3_MASK = 3 << GPIO2D3_SHIFT,
+ GPIO2D3_MASK = GENMASK(7, 6),
GPIO2D3_GPIO = 0,
- GPIO2D3_UART0_RTS0,
+ GPIO2D3_UART0_RTS0 = (1 << 6),
- GPIO2D2_SHIFT = 4,
- GPIO2D2_MASK = 3 << GPIO2D2_SHIFT,
+ GPIO2D2_MASK = GENMASK(5, 4),
GPIO2D2_GPIO = 0,
- GPIO2D2_UART0_CTS0,
+ GPIO2D2_UART0_CTS0 = (1 << 4),
- GPIO2D1_SHIFT = 2,
- GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
+ GPIO2D1_MASK = GENMASK(3, 2),
GPIO2D1_GPIO = 0,
- GPIO2D1_UART0_SOUT,
+ GPIO2D1_UART0_SOUT = (1 << 2),
- GPIO2D0_SHIFT = 0,
- GPIO2D0_MASK = 3 << GPIO2D0_SHIFT,
+ GPIO2D0_MASK = GENMASK(1, 0),
GPIO2D0_GPIO = 0,
- GPIO2D0_UART0_SIN,
+ GPIO2D0_UART0_SIN = (1 << 0),
+};
+
+/* GRF_GPIO1C_IOMUX */
+enum {
+ GPIO1C7_MASK = GENMASK(15, 14),
+ GPIO1C7_GPIO = 0,
+ GPIO1C7_EMMC_DATA5 = (2 << 14),
+
+ GPIO1C6_MASK = GENMASK(13, 12),
+ GPIO1C6_GPIO = 0,
+ GPIO1C6_EMMC_DATA4 = (2 << 12),
+
+ GPIO1C5_MASK = GENMASK(11, 10),
+ GPIO1C5_GPIO = 0,
+ GPIO1C5_EMMC_DATA3 = (2 << 10),
+
+ GPIO1C4_MASK = GENMASK(9, 8),
+ GPIO1C4_GPIO = 0,
+ GPIO1C4_EMMC_DATA2 = (2 << 8),
+
+ GPIO1C3_MASK = GENMASK(7, 6),
+ GPIO1C3_GPIO = 0,
+ GPIO1C3_EMMC_DATA1 = (2 << 6),
+
+ GPIO1C2_MASK = GENMASK(5, 4),
+ GPIO1C2_GPIO = 0,
+ GPIO1C2_EMMC_DATA0 = (2 << 4),
+};
+
+/* GRF_GPIO1D_IOMUX*/
+enum {
+ GPIO1D3_MASK = GENMASK(7, 6),
+ GPIO1D3_GPIO = 0,
+ GPIO1D3_EMMC_PWREN = (2 << 6),
+
+ GPIO1D2_MASK = GENMASK(5, 4),
+ GPIO1D2_GPIO = 0,
+ GPIO1D2_EMMC_CMD = (2 << 4),
+
+ GPIO1D1_MASK = GENMASK(3, 2),
+ GPIO1D1_GPIO = 0,
+ GPIO1D1_EMMC_DATA7 = (2 << 2),
+
+ GPIO1D0_MASK = GENMASK(1, 0),
+ GPIO1D0_GPIO = 0,
+ GPIO1D0_EMMC_DATA6 = (2 << 0),
+};
+
+
+/*GRF_GPIO3B_IOMUX*/
+enum {
+ GPIO3B7_MASK = GENMASK(15, 14),
+ GPIO3B7_GPIO = 0,
+ GPIO3B7_MAC_RXD0 = (1 << 14),
+
+ GPIO3B6_MASK = GENMASK(13, 12),
+ GPIO3B6_GPIO = 0,
+ GPIO3B6_MAC_TXD3 = (1 << 12),
+
+ GPIO3B5_MASK = GENMASK(11, 10),
+ GPIO3B5_GPIO = 0,
+ GPIO3B5_MAC_TXEN = (1 << 10),
+
+ GPIO3B4_MASK = GENMASK(9, 8),
+ GPIO3B4_GPIO = 0,
+ GPIO3B4_MAC_COL = (1 << 8),
+
+ GPIO3B3_MASK = GENMASK(7, 6),
+ GPIO3B3_GPIO = 0,
+ GPIO3B3_MAC_CRS = (1 << 6),
+
+ GPIO3B2_MASK = GENMASK(5, 4),
+ GPIO3B2_GPIO = 0,
+ GPIO3B2_MAC_TXD2 = (1 << 4),
+
+ GPIO3B1_MASK = GENMASK(3, 2),
+ GPIO3B1_GPIO = 0,
+ GPIO3B1_MAC_TXD1 = (1 << 2),
+
+ GPIO3B0_MASK = GENMASK(1, 0),
+ GPIO3B0_GPIO = 0,
+ GPIO3B0_MAC_TXD0 = (1 << 0),
+ GPIO3B0_PWM0 = (2 << 0),
};
/*GRF_GPIO3C_IOMUX*/
enum {
- GPIO3C7_SHIFT = 14,
- GPIO3C7_MASK = 3 << GPIO3C7_SHIFT,
- GPIO3C7_GPIO = 0,
- GPIO3C7_EDPHDMI_CECINOUT,
- GPIO3C7_ISP_FLASHTRIGIN,
-
- GPIO3C6_SHIFT = 12,
- GPIO3C6_MASK = 3 << GPIO3C6_SHIFT,
+ GPIO3C6_MASK = GENMASK(13, 12),
GPIO3C6_GPIO = 0,
- GPIO3C6_MAC_CLK,
- GPIO3C6_ISP_SHUTTERTRIG,
+ GPIO3C6_MAC_CLK = (1 << 12),
- GPIO3C5_SHIFT = 10,
- GPIO3C5_MASK = 3 << GPIO3C5_SHIFT,
+ GPIO3C5_MASK = GENMASK(11, 10),
GPIO3C5_GPIO = 0,
- GPIO3C5_MAC_RXER,
- GPIO3C5_ISP_PRELIGHTTRIG,
+ GPIO3C5_MAC_RXEN = (1 << 10),
- GPIO3C4_SHIFT = 8,
- GPIO3C4_MASK = 3 << GPIO3C4_SHIFT,
+ GPIO3C4_MASK = GENMASK(9, 8),
GPIO3C4_GPIO = 0,
- GPIO3C4_MAC_RXDV,
- GPIO3C4_ISP_FLASHTRIGOUT,
+ GPIO3C4_MAC_RXDV = (1 << 8),
- GPIO3C3_SHIFT = 6,
- GPIO3C3_MASK = 3 << GPIO3C3_SHIFT,
+ GPIO3C3_MASK = GENMASK(7, 6),
GPIO3C3_GPIO = 0,
- GPIO3C3_MAC_RXDV,
- GPIO3C3_EMMC_RSTNO,
+ GPIO3C3_MAC_MDC = (1 << 6),
- GPIO3C2_SHIFT = 4,
- GPIO3C2_MASK = 3 << GPIO3C2_SHIFT,
- GPIO3C2_MAC_MDC = 0,
- GPIO3C2_ISP_SHUTTEREN,
+ GPIO3C2_MASK = GENMASK(5, 4),
+ GPIO3C2_GPIO = 0,
+ GPIO3C2_MAC_RXD3 = (1 << 4),
- GPIO3C1_SHIFT = 2,
- GPIO3C1_MASK = 3 << GPIO3C1_SHIFT,
+ GPIO3C1_MASK = GENMASK(3, 2),
GPIO3C1_GPIO = 0,
- GPIO3C1_MAC_RXD2,
- GPIO3C1_UART3_RTSN,
+ GPIO3C1_MAC_RXD2 = (1 << 2),
- GPIO3C0_SHIFT = 0,
- GPIO3C0_MASK = 3 << GPIO3C0_SHIFT,
+ GPIO3C0_MASK = GENMASK(1, 0),
GPIO3C0_GPIO = 0,
- GPIO3C0_MAC_RXD1,
- GPIO3C0_UART3_CTSN,
- GPIO3C0_GPS_RFCLK,
+ GPIO3C0_MAC_RXD1 = (1 << 0),
};
/*GRF_GPIO3D_IOMUX*/
enum {
- GPIO3D7_SHIFT = 14,
- GPIO3D7_MASK = 3 << GPIO3D7_SHIFT,
- GPIO3D7_GPIO = 0,
- GPIO3D7_SC_VCC18V,
- GPIO3D7_I2C2_SDA,
- GPIO3D7_GPUJTAG_TCK,
-
- GPIO3D6_SHIFT = 12,
- GPIO3D6_MASK = 3 << GPIO3D6_SHIFT,
- GPIO3D6_GPIO = 0,
- GPIO3D6_IR_TX,
- GPIO3D6_UART3_SOUT,
- GPIO3D6_PWM3,
-
- GPIO3D5_SHIFT = 10,
- GPIO3D5_MASK = 3 << GPIO3D5_SHIFT,
- GPIO3D5_GPIO = 0,
- GPIO3D5_IR_RX,
- GPIO3D5_UART3_SIN,
-
- GPIO3D4_SHIFT = 8,
- GPIO3D4_MASK = 3 << GPIO3D4_SHIFT,
+ GPIO3D4_MASK = GENMASK(9, 8),
GPIO3D4_GPIO = 0,
- GPIO3D4_MAC_TXCLKOUT,
- GPIO3D4_SPI1_CSN1,
-
- GPIO3D3_SHIFT = 6,
- GPIO3D3_MASK = 3 << GPIO3D3_SHIFT,
- GPIO3D3_GPIO = 0,
- GPIO3D3_HDMII2C_SCL,
- GPIO3D3_I2C5_SCL,
-
- GPIO3D2_SHIFT = 4,
- GPIO3D2_MASK = 3 << GPIO3D2_SHIFT,
- GPIO3D2_GPIO = 0,
- GPIO3D2_HDMII2C_SDA,
- GPIO3D2_I2C5_SDA,
-
- GPIO3D1_SHIFT = 2,
- GPIO3D1_MASK = 3 << GPIO3D1_SHIFT,
+ GPIO3D4_MAC_TXCLK = (1 << 8),
+
+ GPIO3D1_MASK = GENMASK(3, 2),
GPIO3D1_GPIO = 0,
- GPIO3D1_MAC_RXCLKIN,
- GPIO3D1_I2C4_SCL,
+ GPIO3D1_MAC_RXCLK = (1 << 2),
- GPIO3D0_SHIFT = 0,
- GPIO3D0_MASK = 3 << GPIO3D0_SHIFT,
+ GPIO3D0_MASK = GENMASK(1, 0),
GPIO3D0_GPIO = 0,
- GPIO3D0_MAC_MDIO,
- GPIO3D0_I2C4_SDA,
+ GPIO3D0_MAC_MDIO = (1 << 0),
+};
+
+/* GRF_SOC_CON0 */
+enum {
+ NOC_RSP_ERR_STALL = BIT(9),
+ MOBILE_DDR_SEL = BIT(4),
+ DDR0_16BIT_EN = BIT(3),
+ MSCH0_MAINDDR3_DDR3 = BIT(2),
+ MSCH0_MAINPARTIALPOP = BIT(1),
+ UPCTL_C_ACTIVE = BIT(0),
};
/*GRF_SOC_CON11/12/13*/
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3368.c b/drivers/pinctrl/rockchip/pinctrl_rk3368.c
index bdf0758..c96459f 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3368.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3368.c
@@ -31,8 +31,7 @@ static void pinctrl_rk3368_uart_config(struct rk3368_pinctrl_priv *priv,
case PERIPH_ID_UART2:
rk_clrsetreg(&grf->gpio2a_iomux,
GPIO2A6_MASK | GPIO2A5_MASK,
- GPIO2A6_UART2_SIN << GPIO2A6_SHIFT |
- GPIO2A5_UART2_SOUT << GPIO2A5_SHIFT);
+ GPIO2A6_UART2_SIN | GPIO2A5_UART2_SOUT);
break;
case PERIPH_ID_UART0:
break;
@@ -44,10 +43,8 @@ static void pinctrl_rk3368_uart_config(struct rk3368_pinctrl_priv *priv,
rk_clrsetreg(&pmugrf->gpio0d_iomux,
GPIO0D0_MASK | GPIO0D1_MASK |
GPIO0D2_MASK | GPIO0D3_MASK,
- GPIO0D0_GPIO << GPIO0D0_SHIFT |
- GPIO0D1_GPIO << GPIO0D1_SHIFT |
- GPIO0D2_UART4_SOUT << GPIO0D2_SHIFT |
- GPIO0D3_UART4_SIN << GPIO0D3_SHIFT);
+ GPIO0D0_GPIO | GPIO0D1_GPIO |
+ GPIO0D2_UART4_SOUT | GPIO0D3_UART4_SIN);
break;
default:
debug("uart id = %d iomux error!\n", uart_id);
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 33/66] rockchip: rk3368: dts: add sgrf node
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (31 preceding siblings ...)
2017-07-28 19:22 ` [U-Boot] [PATCH v3 32/66] rockchip: rk3368: grf: use shifted-constants Philipp Tomsich
@ 2017-07-28 19:22 ` Philipp Tomsich
2017-08-01 9:48 ` Simon Glass
2017-07-28 19:22 ` [U-Boot] [PATCH v3 34/66] rockchip: pinctrl: rk3368: add GMAC (RGMII only) support Philipp Tomsich
` (32 subsequent siblings)
65 siblings, 1 reply; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:22 UTC (permalink / raw)
To: u-boot
We will to drop device security temporarily (until the ATF initialises
it fully) from the TPL/SPL stage: this requires access to some
registers in the SGRF.
This adds the sgrf node to the rk3368.dtsi, so we can then bind a
syscon device onto it and access its memory ranges.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---
Changes in v3: None
Changes in v2: None
arch/arm/dts/rk3368.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/dts/rk3368.dtsi b/arch/arm/dts/rk3368.dtsi
index 9daf765..59c20da 100644
--- a/arch/arm/dts/rk3368.dtsi
+++ b/arch/arm/dts/rk3368.dtsi
@@ -652,6 +652,11 @@
reg = <0x0 0xff738000 0x0 0x1000>;
};
+ sgrf: syscon at ff740000 {
+ compatible = "rockchip,rk3368-sgrf", "syscon";
+ reg = <0x0 0xff740000 0x0 0x1000>;
+ };
+
cru: clock-controller at ff760000 {
compatible = "rockchip,rk3368-cru";
reg = <0x0 0xff760000 0x0 0x1000>;
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 33/66] rockchip: rk3368: dts: add sgrf node
2017-07-28 19:22 ` [U-Boot] [PATCH v3 33/66] rockchip: rk3368: dts: add sgrf node Philipp Tomsich
@ 2017-08-01 9:48 ` Simon Glass
0 siblings, 0 replies; 95+ messages in thread
From: Simon Glass @ 2017-08-01 9:48 UTC (permalink / raw)
To: u-boot
On 28 July 2017 at 13:22, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> We will to drop device security temporarily (until the ATF initialises
> it fully) from the TPL/SPL stage: this requires access to some
> registers in the SGRF.
>
> This adds the sgrf node to the rk3368.dtsi, so we can then bind a
> syscon device onto it and access its memory ranges.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
> arch/arm/dts/rk3368.dtsi | 5 +++++
> 1 file changed, 5 insertions(+)
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 95+ messages in thread
* [U-Boot] [PATCH v3 34/66] rockchip: pinctrl: rk3368: add GMAC (RGMII only) support
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (32 preceding siblings ...)
2017-07-28 19:22 ` [U-Boot] [PATCH v3 33/66] rockchip: rk3368: dts: add sgrf node Philipp Tomsich
@ 2017-07-28 19:22 ` Philipp Tomsich
2017-07-28 19:22 ` [U-Boot] [PATCH v3 35/66] rockchip: pinctrl: rk3368: add support for configuring the MMC pins Philipp Tomsich
` (31 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:22 UTC (permalink / raw)
To: u-boot
To add GMAC (Gigabit Ethernet) support (limited to RGMII only at this
point), we need support for additional pin-configuration. This commit
adds the pinctrl support for GMAC in RGMII mode:
* adds a PERIPH_ID_GMAC and the mapping from IRQ number to PERIPH_ID
* configures the RGMII pins
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
Changes in v3: None
Changes in v2:
- removed the RK3368-prefix on bit-definitions for GMAC pinctrl
drivers/pinctrl/rockchip/pinctrl_rk3368.c | 36 +++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3368.c b/drivers/pinctrl/rockchip/pinctrl_rk3368.c
index c96459f..22cd593 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3368.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3368.c
@@ -52,6 +52,33 @@ static void pinctrl_rk3368_uart_config(struct rk3368_pinctrl_priv *priv,
}
}
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
+static void pinctrl_rk3368_gmac_config(struct rk3368_grf *grf, int gmac_id)
+{
+ rk_clrsetreg(&grf->gpio3b_iomux,
+ GPIO3B0_MASK | GPIO3B1_MASK |
+ GPIO3B2_MASK | GPIO3B5_MASK |
+ GPIO3B6_MASK | GPIO3B7_MASK,
+ GPIO3B0_MAC_TXD0 | GPIO3B1_MAC_TXD1 |
+ GPIO3B2_MAC_TXD2 | GPIO3B5_MAC_TXEN |
+ GPIO3B6_MAC_TXD3 | GPIO3B7_MAC_RXD0);
+ rk_clrsetreg(&grf->gpio3c_iomux,
+ GPIO3C0_MASK | GPIO3C1_MASK |
+ GPIO3C2_MASK | GPIO3C3_MASK |
+ GPIO3C4_MASK | GPIO3C5_MASK |
+ GPIO3C6_MASK,
+ GPIO3C0_MAC_RXD1 | GPIO3C1_MAC_RXD2 |
+ GPIO3C2_MAC_RXD3 | GPIO3C3_MAC_MDC |
+ GPIO3C4_MAC_RXDV | GPIO3C5_MAC_RXEN |
+ GPIO3C6_MAC_CLK);
+ rk_clrsetreg(&grf->gpio3d_iomux,
+ GPIO3D0_MASK | GPIO3D1_MASK |
+ GPIO3D4_MASK,
+ GPIO3D0_MAC_MDIO | GPIO3D1_MAC_RXCLK |
+ GPIO3D4_MAC_TXCLK);
+}
+#endif
+
static int rk3368_pinctrl_request(struct udevice *dev, int func, int flags)
{
struct rk3368_pinctrl_priv *priv = dev_get_priv(dev);
@@ -65,6 +92,11 @@ static int rk3368_pinctrl_request(struct udevice *dev, int func, int flags)
case PERIPH_ID_UART4:
pinctrl_rk3368_uart_config(priv, func);
break;
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
+ case PERIPH_ID_GMAC:
+ pinctrl_rk3368_gmac_config(priv->grf, func);
+ break;
+#endif
default:
return -EINVAL;
}
@@ -94,6 +126,10 @@ static int rk3368_pinctrl_get_periph_id(struct udevice *dev,
return PERIPH_ID_UART1;
case 55:
return PERIPH_ID_UART0;
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
+ case 27:
+ return PERIPH_ID_GMAC;
+#endif
}
return -ENOENT;
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 35/66] rockchip: pinctrl: rk3368: add support for configuring the MMC pins
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (33 preceding siblings ...)
2017-07-28 19:22 ` [U-Boot] [PATCH v3 34/66] rockchip: pinctrl: rk3368: add GMAC (RGMII only) support Philipp Tomsich
@ 2017-07-28 19:22 ` Philipp Tomsich
2017-07-28 19:22 ` [U-Boot] [PATCH v3 36/66] rockchip: pinctrl: rk3368: move IOMUX bit-definitions to pinctrl driver Philipp Tomsich
` (30 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:22 UTC (permalink / raw)
To: u-boot
The RK3368 has two SD/MMC controllers that can be used from U-Boot
both during SPL and for booting an OS from the full bootloader stage.
While both are configured to (mostly) sensible settings from the BROM,
additional configuration for the MMC controller is needed to configure
it to 8bit mode.
This adds pinctrl support for the MMC controller.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
Changes in v3: None
Changes in v2:
- removed the RK3368 prefix on the SD/MMC pin definitions
drivers/pinctrl/rockchip/pinctrl_rk3368.c | 48 +++++++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3368.c b/drivers/pinctrl/rockchip/pinctrl_rk3368.c
index 22cd593..cf2f834 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3368.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3368.c
@@ -79,6 +79,46 @@ static void pinctrl_rk3368_gmac_config(struct rk3368_grf *grf, int gmac_id)
}
#endif
+static void pinctrl_rk3368_sdmmc_config(struct rk3368_grf *grf, int mmc_id)
+{
+ switch (mmc_id) {
+ case PERIPH_ID_EMMC:
+ debug("mmc id = %d setting registers!\n", mmc_id);
+ rk_clrsetreg(&grf->gpio1c_iomux,
+ GPIO1C2_MASK | GPIO1C3_MASK |
+ GPIO1C4_MASK | GPIO1C5_MASK |
+ GPIO1C6_MASK | GPIO1C7_MASK,
+ GPIO1C2_EMMC_DATA0 |
+ GPIO1C3_EMMC_DATA1 |
+ GPIO1C4_EMMC_DATA2 |
+ GPIO1C5_EMMC_DATA3 |
+ GPIO1C6_EMMC_DATA4 |
+ GPIO1C7_EMMC_DATA5);
+ rk_clrsetreg(&grf->gpio1d_iomux,
+ GPIO1D0_MASK | GPIO1D1_MASK |
+ GPIO1D2_MASK | GPIO1D3_MASK,
+ GPIO1D0_EMMC_DATA6 |
+ GPIO1D1_EMMC_DATA7 |
+ GPIO1D2_EMMC_CMD |
+ GPIO1D3_EMMC_PWREN);
+ rk_clrsetreg(&grf->gpio2a_iomux,
+ GPIO2A3_MASK | GPIO2A4_MASK,
+ GPIO2A3_EMMC_RSTNOUT |
+ GPIO2A4_EMMC_CLKOUT);
+ break;
+ case PERIPH_ID_SDCARD:
+ /*
+ * We assume that the BROM has already set this up
+ * correctly for us and that there's nothing to do
+ * here.
+ */
+ break;
+ default:
+ debug("mmc id = %d iomux error!\n", mmc_id);
+ break;
+ }
+}
+
static int rk3368_pinctrl_request(struct udevice *dev, int func, int flags)
{
struct rk3368_pinctrl_priv *priv = dev_get_priv(dev);
@@ -92,6 +132,10 @@ static int rk3368_pinctrl_request(struct udevice *dev, int func, int flags)
case PERIPH_ID_UART4:
pinctrl_rk3368_uart_config(priv, func);
break;
+ case PERIPH_ID_EMMC:
+ case PERIPH_ID_SDCARD:
+ pinctrl_rk3368_sdmmc_config(priv->grf, func);
+ break;
#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
case PERIPH_ID_GMAC:
pinctrl_rk3368_gmac_config(priv->grf, func);
@@ -126,6 +170,10 @@ static int rk3368_pinctrl_get_periph_id(struct udevice *dev,
return PERIPH_ID_UART1;
case 55:
return PERIPH_ID_UART0;
+ case 35:
+ return PERIPH_ID_EMMC;
+ case 32:
+ return PERIPH_ID_SDCARD;
#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
case 27:
return PERIPH_ID_GMAC;
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 36/66] rockchip: pinctrl: rk3368: move IOMUX bit-definitions to pinctrl driver
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (34 preceding siblings ...)
2017-07-28 19:22 ` [U-Boot] [PATCH v3 35/66] rockchip: pinctrl: rk3368: add support for configuring the MMC pins Philipp Tomsich
@ 2017-07-28 19:22 ` Philipp Tomsich
2017-07-28 19:22 ` [U-Boot] [PATCH v3 37/66] rockchip: pinctrl: rk3368: add SPI support Philipp Tomsich
` (29 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:22 UTC (permalink / raw)
To: u-boot
There is no real reason to keep the bit-definitions for the IOMUX in
the grf header file (which defines the register layout of the GRF block):
these should only be used by our pinctrl driver (with the possible
exception of early debug-init code in TPL/SPL).
This moves the relevant definitions from the grf_rk3368.h header
into the pinctrl driver pinctrl_rk3368.c.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
Changes in v3: None
Changes in v2:
- moved bit-definitions pertinent to pinctrl (i.e. the various IOMUX
definitions) to the rk3368 pinctrl driver implementation
arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 316 -----------------------
drivers/pinctrl/rockchip/pinctrl_rk3368.c | 325 ++++++++++++++++++++++++
2 files changed, 325 insertions(+), 316 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
index 1966960..ec42d7a 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
@@ -100,322 +100,6 @@ struct rk3368_pmu_grf {
check_member(rk3368_pmu_grf, gpio0h_sr, 0x34);
check_member(rk3368_pmu_grf, os_reg[0], 0x200);
-/*GRF_GPIO0C_IOMUX*/
-enum {
- GPIO0C7_MASK = GENMASK(15, 14),
- GPIO0C7_GPIO = 0,
- GPIO0C7_LCDC_D19 = (1 << 14),
- GPIO0C7_TRACE_D9 = (2 << 14),
- GPIO0C7_UART1_RTSN = (3 << 14),
-
- GPIO0C6_MASK = GENMASK(13, 12),
- GPIO0C6_GPIO = 0,
- GPIO0C6_LCDC_D18 = (1 << 12),
- GPIO0C6_TRACE_D8 = (2 << 12),
- GPIO0C6_UART1_CTSN = (3 << 12),
-
- GPIO0C5_MASK = GENMASK(11, 10),
- GPIO0C5_GPIO = 0,
- GPIO0C5_LCDC_D17 = (1 << 10),
- GPIO0C5_TRACE_D7 = (2 << 10),
- GPIO0C5_UART1_SOUT = (3 << 10),
-
- GPIO0C4_MASK = GENMASK(9, 8),
- GPIO0C4_GPIO = 0,
- GPIO0C4_LCDC_D16 = (1 << 8),
- GPIO0C4_TRACE_D6 = (2 << 8),
- GPIO0C4_UART1_SIN = (3 << 8),
-
- GPIO0C3_MASK = GENMASK(7, 6),
- GPIO0C3_GPIO = 0,
- GPIO0C3_LCDC_D15 = (1 << 6),
- GPIO0C3_TRACE_D5 = (2 << 6),
- GPIO0C3_MCU_JTAG_TDO = (3 << 6),
-
- GPIO0C2_MASK = GENMASK(5, 4),
- GPIO0C2_GPIO = 0,
- GPIO0C2_LCDC_D14 = (1 << 4),
- GPIO0C2_TRACE_D4 = (2 << 4),
- GPIO0C2_MCU_JTAG_TDI = (3 << 4),
-
- GPIO0C1_MASK = GENMASK(3, 2),
- GPIO0C1_GPIO = 0,
- GPIO0C1_LCDC_D13 = (1 << 2),
- GPIO0C1_TRACE_D3 = (2 << 2),
- GPIO0C1_MCU_JTAG_TRTSN = (3 << 2),
-
- GPIO0C0_MASK = GENMASK(1, 0),
- GPIO0C0_GPIO = 0,
- GPIO0C0_LCDC_D12 = (1 << 0),
- GPIO0C0_TRACE_D2 = (2 << 0),
- GPIO0C0_MCU_JTAG_TDO = (3 << 0),
-};
-
-/*GRF_GPIO0D_IOMUX*/
-enum {
- GPIO0D7_MASK = GENMASK(15, 14),
- GPIO0D7_GPIO = 0,
- GPIO0D7_LCDC_DCLK = (1 << 14),
- GPIO0D7_TRACE_CTL = (2 << 14),
- GPIO0D7_PMU_DEBUG5 = (3 << 14),
-
- GPIO0D6_MASK = GENMASK(13, 12),
- GPIO0D6_GPIO = 0,
- GPIO0D6_LCDC_DEN = (1 << 12),
- GPIO0D6_TRACE_CLK = (2 << 12),
- GPIO0D6_PMU_DEBUG4 = (3 << 12),
-
- GPIO0D5_MASK = GENMASK(11, 10),
- GPIO0D5_GPIO = 0,
- GPIO0D5_LCDC_VSYNC = (1 << 10),
- GPIO0D5_TRACE_D15 = (2 << 10),
- GPIO0D5_PMU_DEBUG3 = (3 << 10),
-
- GPIO0D4_MASK = GENMASK(9, 8),
- GPIO0D4_GPIO = 0,
- GPIO0D4_LCDC_HSYNC = (1 << 8),
- GPIO0D4_TRACE_D14 = (2 << 8),
- GPIO0D4_PMU_DEBUG2 = (3 << 8),
-
- GPIO0D3_MASK = GENMASK(7, 6),
- GPIO0D3_GPIO = 0,
- GPIO0D3_LCDC_D23 = (1 << 6),
- GPIO0D3_TRACE_D13 = (2 << 6),
- GPIO0D3_UART4_SIN = (3 << 6),
-
- GPIO0D2_MASK = GENMASK(5, 4),
- GPIO0D2_GPIO = 0,
- GPIO0D2_LCDC_D22 = (1 << 4),
- GPIO0D2_TRACE_D12 = (2 << 4),
- GPIO0D2_UART4_SOUT = (3 << 4),
-
- GPIO0D1_MASK = GENMASK(3, 2),
- GPIO0D1_GPIO = 0,
- GPIO0D1_LCDC_D21 = (1 << 2),
- GPIO0D1_TRACE_D11 = (2 << 2),
- GPIO0D1_UART4_RTSN = (3 << 2),
-
- GPIO0D0_MASK = GENMASK(1, 0),
- GPIO0D0_GPIO = 0,
- GPIO0D0_LCDC_D20 = (1 << 0),
- GPIO0D0_TRACE_D10 = (2 << 0),
- GPIO0D0_UART4_CTSN = (3 << 0),
-};
-
-/*GRF_GPIO2A_IOMUX*/
-enum {
- GPIO2A7_MASK = GENMASK(15, 14),
- GPIO2A7_GPIO = 0,
- GPIO2A7_SDMMC0_D2 = (1 << 14),
- GPIO2A7_JTAG_TCK = (2 << 14),
-
- GPIO2A6_MASK = GENMASK(13, 12),
- GPIO2A6_GPIO = 0,
- GPIO2A6_SDMMC0_D1 = (1 << 12),
- GPIO2A6_UART2_SIN = (2 << 12),
-
- GPIO2A5_MASK = GENMASK(11, 10),
- GPIO2A5_GPIO = 0,
- GPIO2A5_SDMMC0_D0 = (1 << 10),
- GPIO2A5_UART2_SOUT = (2 << 10),
-
- GPIO2A4_MASK = GENMASK(9, 8),
- GPIO2A4_GPIO = 0,
- GPIO2A4_FLASH_DQS = (1 << 8),
- GPIO2A4_EMMC_CLKOUT = (2 << 8),
-
- GPIO2A3_MASK = GENMASK(7, 6),
- GPIO2A3_GPIO = 0,
- GPIO2A3_FLASH_CSN3 = (1 << 6),
- GPIO2A3_EMMC_RSTNOUT = (2 << 6),
-
- GPIO2A2_MASK = GENMASK(5, 4),
- GPIO2A2_GPIO = 0,
- GPIO2A2_FLASH_CSN2 = (1 << 4),
-
- GPIO2A1_MASK = GENMASK(3, 2),
- GPIO2A1_GPIO = 0,
- GPIO2A1_FLASH_CSN1 = (1 << 2),
-
- GPIO2A0_MASK = GENMASK(1, 0),
- GPIO2A0_GPIO = 0,
- GPIO2A0_FLASH_CSN0 = (1 << 0),
-};
-
-/*GRF_GPIO2D_IOMUX*/
-enum {
- GPIO2D7_MASK = GENMASK(15, 14),
- GPIO2D7_GPIO = 0,
- GPIO2D7_SDIO0_D3 = (1 << 14),
-
- GPIO2D6_MASK = GENMASK(13, 12),
- GPIO2D6_GPIO = 0,
- GPIO2D6_SDIO0_D2 = (1 << 12),
-
- GPIO2D5_MASK = GENMASK(11, 10),
- GPIO2D5_GPIO = 0,
- GPIO2D5_SDIO0_D1 = (1 << 10),
-
- GPIO2D4_MASK = GENMASK(9, 8),
- GPIO2D4_GPIO = 0,
- GPIO2D4_SDIO0_D0 = (1 << 8),
-
- GPIO2D3_MASK = GENMASK(7, 6),
- GPIO2D3_GPIO = 0,
- GPIO2D3_UART0_RTS0 = (1 << 6),
-
- GPIO2D2_MASK = GENMASK(5, 4),
- GPIO2D2_GPIO = 0,
- GPIO2D2_UART0_CTS0 = (1 << 4),
-
- GPIO2D1_MASK = GENMASK(3, 2),
- GPIO2D1_GPIO = 0,
- GPIO2D1_UART0_SOUT = (1 << 2),
-
- GPIO2D0_MASK = GENMASK(1, 0),
- GPIO2D0_GPIO = 0,
- GPIO2D0_UART0_SIN = (1 << 0),
-};
-
-/* GRF_GPIO1C_IOMUX */
-enum {
- GPIO1C7_MASK = GENMASK(15, 14),
- GPIO1C7_GPIO = 0,
- GPIO1C7_EMMC_DATA5 = (2 << 14),
-
- GPIO1C6_MASK = GENMASK(13, 12),
- GPIO1C6_GPIO = 0,
- GPIO1C6_EMMC_DATA4 = (2 << 12),
-
- GPIO1C5_MASK = GENMASK(11, 10),
- GPIO1C5_GPIO = 0,
- GPIO1C5_EMMC_DATA3 = (2 << 10),
-
- GPIO1C4_MASK = GENMASK(9, 8),
- GPIO1C4_GPIO = 0,
- GPIO1C4_EMMC_DATA2 = (2 << 8),
-
- GPIO1C3_MASK = GENMASK(7, 6),
- GPIO1C3_GPIO = 0,
- GPIO1C3_EMMC_DATA1 = (2 << 6),
-
- GPIO1C2_MASK = GENMASK(5, 4),
- GPIO1C2_GPIO = 0,
- GPIO1C2_EMMC_DATA0 = (2 << 4),
-};
-
-/* GRF_GPIO1D_IOMUX*/
-enum {
- GPIO1D3_MASK = GENMASK(7, 6),
- GPIO1D3_GPIO = 0,
- GPIO1D3_EMMC_PWREN = (2 << 6),
-
- GPIO1D2_MASK = GENMASK(5, 4),
- GPIO1D2_GPIO = 0,
- GPIO1D2_EMMC_CMD = (2 << 4),
-
- GPIO1D1_MASK = GENMASK(3, 2),
- GPIO1D1_GPIO = 0,
- GPIO1D1_EMMC_DATA7 = (2 << 2),
-
- GPIO1D0_MASK = GENMASK(1, 0),
- GPIO1D0_GPIO = 0,
- GPIO1D0_EMMC_DATA6 = (2 << 0),
-};
-
-
-/*GRF_GPIO3B_IOMUX*/
-enum {
- GPIO3B7_MASK = GENMASK(15, 14),
- GPIO3B7_GPIO = 0,
- GPIO3B7_MAC_RXD0 = (1 << 14),
-
- GPIO3B6_MASK = GENMASK(13, 12),
- GPIO3B6_GPIO = 0,
- GPIO3B6_MAC_TXD3 = (1 << 12),
-
- GPIO3B5_MASK = GENMASK(11, 10),
- GPIO3B5_GPIO = 0,
- GPIO3B5_MAC_TXEN = (1 << 10),
-
- GPIO3B4_MASK = GENMASK(9, 8),
- GPIO3B4_GPIO = 0,
- GPIO3B4_MAC_COL = (1 << 8),
-
- GPIO3B3_MASK = GENMASK(7, 6),
- GPIO3B3_GPIO = 0,
- GPIO3B3_MAC_CRS = (1 << 6),
-
- GPIO3B2_MASK = GENMASK(5, 4),
- GPIO3B2_GPIO = 0,
- GPIO3B2_MAC_TXD2 = (1 << 4),
-
- GPIO3B1_MASK = GENMASK(3, 2),
- GPIO3B1_GPIO = 0,
- GPIO3B1_MAC_TXD1 = (1 << 2),
-
- GPIO3B0_MASK = GENMASK(1, 0),
- GPIO3B0_GPIO = 0,
- GPIO3B0_MAC_TXD0 = (1 << 0),
- GPIO3B0_PWM0 = (2 << 0),
-};
-
-/*GRF_GPIO3C_IOMUX*/
-enum {
- GPIO3C6_MASK = GENMASK(13, 12),
- GPIO3C6_GPIO = 0,
- GPIO3C6_MAC_CLK = (1 << 12),
-
- GPIO3C5_MASK = GENMASK(11, 10),
- GPIO3C5_GPIO = 0,
- GPIO3C5_MAC_RXEN = (1 << 10),
-
- GPIO3C4_MASK = GENMASK(9, 8),
- GPIO3C4_GPIO = 0,
- GPIO3C4_MAC_RXDV = (1 << 8),
-
- GPIO3C3_MASK = GENMASK(7, 6),
- GPIO3C3_GPIO = 0,
- GPIO3C3_MAC_MDC = (1 << 6),
-
- GPIO3C2_MASK = GENMASK(5, 4),
- GPIO3C2_GPIO = 0,
- GPIO3C2_MAC_RXD3 = (1 << 4),
-
- GPIO3C1_MASK = GENMASK(3, 2),
- GPIO3C1_GPIO = 0,
- GPIO3C1_MAC_RXD2 = (1 << 2),
-
- GPIO3C0_MASK = GENMASK(1, 0),
- GPIO3C0_GPIO = 0,
- GPIO3C0_MAC_RXD1 = (1 << 0),
-};
-
-/*GRF_GPIO3D_IOMUX*/
-enum {
- GPIO3D4_MASK = GENMASK(9, 8),
- GPIO3D4_GPIO = 0,
- GPIO3D4_MAC_TXCLK = (1 << 8),
-
- GPIO3D1_MASK = GENMASK(3, 2),
- GPIO3D1_GPIO = 0,
- GPIO3D1_MAC_RXCLK = (1 << 2),
-
- GPIO3D0_MASK = GENMASK(1, 0),
- GPIO3D0_GPIO = 0,
- GPIO3D0_MAC_MDIO = (1 << 0),
-};
-
-/* GRF_SOC_CON0 */
-enum {
- NOC_RSP_ERR_STALL = BIT(9),
- MOBILE_DDR_SEL = BIT(4),
- DDR0_16BIT_EN = BIT(3),
- MSCH0_MAINDDR3_DDR3 = BIT(2),
- MSCH0_MAINPARTIALPOP = BIT(1),
- UPCTL_C_ACTIVE = BIT(0),
-};
-
/*GRF_SOC_CON11/12/13*/
enum {
MCU_SRAM_BASE_BIT27_BIT12_SHIFT = 0,
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3368.c b/drivers/pinctrl/rockchip/pinctrl_rk3368.c
index cf2f834..67695ab 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3368.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3368.c
@@ -16,6 +16,331 @@
DECLARE_GLOBAL_DATA_PTR;
+/*GRF_GPIO0C_IOMUX*/
+enum {
+ GPIO0C7_MASK = GENMASK(15, 14),
+ GPIO0C7_GPIO = 0,
+ GPIO0C7_LCDC_D19 = (1 << 14),
+ GPIO0C7_TRACE_D9 = (2 << 14),
+ GPIO0C7_UART1_RTSN = (3 << 14),
+
+ GPIO0C6_MASK = GENMASK(13, 12),
+ GPIO0C6_GPIO = 0,
+ GPIO0C6_LCDC_D18 = (1 << 12),
+ GPIO0C6_TRACE_D8 = (2 << 12),
+ GPIO0C6_UART1_CTSN = (3 << 12),
+
+ GPIO0C5_MASK = GENMASK(11, 10),
+ GPIO0C5_GPIO = 0,
+ GPIO0C5_LCDC_D17 = (1 << 10),
+ GPIO0C5_TRACE_D7 = (2 << 10),
+ GPIO0C5_UART1_SOUT = (3 << 10),
+
+ GPIO0C4_MASK = GENMASK(9, 8),
+ GPIO0C4_GPIO = 0,
+ GPIO0C4_LCDC_D16 = (1 << 8),
+ GPIO0C4_TRACE_D6 = (2 << 8),
+ GPIO0C4_UART1_SIN = (3 << 8),
+
+ GPIO0C3_MASK = GENMASK(7, 6),
+ GPIO0C3_GPIO = 0,
+ GPIO0C3_LCDC_D15 = (1 << 6),
+ GPIO0C3_TRACE_D5 = (2 << 6),
+ GPIO0C3_MCU_JTAG_TDO = (3 << 6),
+
+ GPIO0C2_MASK = GENMASK(5, 4),
+ GPIO0C2_GPIO = 0,
+ GPIO0C2_LCDC_D14 = (1 << 4),
+ GPIO0C2_TRACE_D4 = (2 << 4),
+ GPIO0C2_MCU_JTAG_TDI = (3 << 4),
+
+ GPIO0C1_MASK = GENMASK(3, 2),
+ GPIO0C1_GPIO = 0,
+ GPIO0C1_LCDC_D13 = (1 << 2),
+ GPIO0C1_TRACE_D3 = (2 << 2),
+ GPIO0C1_MCU_JTAG_TRTSN = (3 << 2),
+
+ GPIO0C0_MASK = GENMASK(1, 0),
+ GPIO0C0_GPIO = 0,
+ GPIO0C0_LCDC_D12 = (1 << 0),
+ GPIO0C0_TRACE_D2 = (2 << 0),
+ GPIO0C0_MCU_JTAG_TDO = (3 << 0),
+};
+
+/*GRF_GPIO0D_IOMUX*/
+enum {
+ GPIO0D7_MASK = GENMASK(15, 14),
+ GPIO0D7_GPIO = 0,
+ GPIO0D7_LCDC_DCLK = (1 << 14),
+ GPIO0D7_TRACE_CTL = (2 << 14),
+ GPIO0D7_PMU_DEBUG5 = (3 << 14),
+
+ GPIO0D6_MASK = GENMASK(13, 12),
+ GPIO0D6_GPIO = 0,
+ GPIO0D6_LCDC_DEN = (1 << 12),
+ GPIO0D6_TRACE_CLK = (2 << 12),
+ GPIO0D6_PMU_DEBUG4 = (3 << 12),
+
+ GPIO0D5_MASK = GENMASK(11, 10),
+ GPIO0D5_GPIO = 0,
+ GPIO0D5_LCDC_VSYNC = (1 << 10),
+ GPIO0D5_TRACE_D15 = (2 << 10),
+ GPIO0D5_PMU_DEBUG3 = (3 << 10),
+
+ GPIO0D4_MASK = GENMASK(9, 8),
+ GPIO0D4_GPIO = 0,
+ GPIO0D4_LCDC_HSYNC = (1 << 8),
+ GPIO0D4_TRACE_D14 = (2 << 8),
+ GPIO0D4_PMU_DEBUG2 = (3 << 8),
+
+ GPIO0D3_MASK = GENMASK(7, 6),
+ GPIO0D3_GPIO = 0,
+ GPIO0D3_LCDC_D23 = (1 << 6),
+ GPIO0D3_TRACE_D13 = (2 << 6),
+ GPIO0D3_UART4_SIN = (3 << 6),
+
+ GPIO0D2_MASK = GENMASK(5, 4),
+ GPIO0D2_GPIO = 0,
+ GPIO0D2_LCDC_D22 = (1 << 4),
+ GPIO0D2_TRACE_D12 = (2 << 4),
+ GPIO0D2_UART4_SOUT = (3 << 4),
+
+ GPIO0D1_MASK = GENMASK(3, 2),
+ GPIO0D1_GPIO = 0,
+ GPIO0D1_LCDC_D21 = (1 << 2),
+ GPIO0D1_TRACE_D11 = (2 << 2),
+ GPIO0D1_UART4_RTSN = (3 << 2),
+
+ GPIO0D0_MASK = GENMASK(1, 0),
+ GPIO0D0_GPIO = 0,
+ GPIO0D0_LCDC_D20 = (1 << 0),
+ GPIO0D0_TRACE_D10 = (2 << 0),
+ GPIO0D0_UART4_CTSN = (3 << 0),
+};
+
+/*GRF_GPIO2A_IOMUX*/
+enum {
+ GPIO2A7_MASK = GENMASK(15, 14),
+ GPIO2A7_GPIO = 0,
+ GPIO2A7_SDMMC0_D2 = (1 << 14),
+ GPIO2A7_JTAG_TCK = (2 << 14),
+
+ GPIO2A6_MASK = GENMASK(13, 12),
+ GPIO2A6_GPIO = 0,
+ GPIO2A6_SDMMC0_D1 = (1 << 12),
+ GPIO2A6_UART2_SIN = (2 << 12),
+
+ GPIO2A5_MASK = GENMASK(11, 10),
+ GPIO2A5_GPIO = 0,
+ GPIO2A5_SDMMC0_D0 = (1 << 10),
+ GPIO2A5_UART2_SOUT = (2 << 10),
+
+ GPIO2A4_MASK = GENMASK(9, 8),
+ GPIO2A4_GPIO = 0,
+ GPIO2A4_FLASH_DQS = (1 << 8),
+ GPIO2A4_EMMC_CLKOUT = (2 << 8),
+
+ GPIO2A3_MASK = GENMASK(7, 6),
+ GPIO2A3_GPIO = 0,
+ GPIO2A3_FLASH_CSN3 = (1 << 6),
+ GPIO2A3_EMMC_RSTNOUT = (2 << 6),
+
+ GPIO2A2_MASK = GENMASK(5, 4),
+ GPIO2A2_GPIO = 0,
+ GPIO2A2_FLASH_CSN2 = (1 << 4),
+
+ GPIO2A1_MASK = GENMASK(3, 2),
+ GPIO2A1_GPIO = 0,
+ GPIO2A1_FLASH_CSN1 = (1 << 2),
+
+ GPIO2A0_MASK = GENMASK(1, 0),
+ GPIO2A0_GPIO = 0,
+ GPIO2A0_FLASH_CSN0 = (1 << 0),
+};
+
+/* GRF_GPIO2D_IOMUX */
+enum {
+ GPIO2D7_MASK = GENMASK(15, 14),
+ GPIO2D7_GPIO = 0,
+ GPIO2D7_SDIO0_D3 = (1 << 14),
+
+ GPIO2D6_MASK = GENMASK(13, 12),
+ GPIO2D6_GPIO = 0,
+ GPIO2D6_SDIO0_D2 = (1 << 12),
+
+ GPIO2D5_MASK = GENMASK(11, 10),
+ GPIO2D5_GPIO = 0,
+ GPIO2D5_SDIO0_D1 = (1 << 10),
+
+ GPIO2D4_MASK = GENMASK(9, 8),
+ GPIO2D4_GPIO = 0,
+ GPIO2D4_SDIO0_D0 = (1 << 8),
+
+ GPIO2D3_MASK = GENMASK(7, 6),
+ GPIO2D3_GPIO = 0,
+ GPIO2D3_UART0_RTS0 = (1 << 6),
+
+ GPIO2D2_MASK = GENMASK(5, 4),
+ GPIO2D2_GPIO = 0,
+ GPIO2D2_UART0_CTS0 = (1 << 4),
+
+ GPIO2D1_MASK = GENMASK(3, 2),
+ GPIO2D1_GPIO = 0,
+ GPIO2D1_UART0_SOUT = (1 << 2),
+
+ GPIO2D0_MASK = GENMASK(1, 0),
+ GPIO2D0_GPIO = 0,
+ GPIO2D0_UART0_SIN = (1 << 0),
+};
+
+/* GRF_GPIO1B_IOMUX */
+enum {
+ GPIO1B7_MASK = GENMASK(15, 14),
+ GPIO1B7_GPIO = 0,
+ GPIO1B7_SPI1_CSN0 = (2 << 14),
+
+ GPIO1B6_MASK = GENMASK(13, 12),
+ GPIO1B6_GPIO = 0,
+ GPIO1B6_SPI1_CLK = (2 << 12),
+};
+
+/* GRF_GPIO1C_IOMUX */
+enum {
+ GPIO1C7_MASK = GENMASK(15, 14),
+ GPIO1C7_GPIO = 0,
+ GPIO1C7_EMMC_DATA5 = (2 << 14),
+
+ GPIO1C6_MASK = GENMASK(13, 12),
+ GPIO1C6_GPIO = 0,
+ GPIO1C6_EMMC_DATA4 = (2 << 12),
+
+ GPIO1C5_MASK = GENMASK(11, 10),
+ GPIO1C5_GPIO = 0,
+ GPIO1C5_EMMC_DATA3 = (2 << 10),
+
+ GPIO1C4_MASK = GENMASK(9, 8),
+ GPIO1C4_GPIO = 0,
+ GPIO1C4_EMMC_DATA2 = (2 << 8),
+
+ GPIO1C3_MASK = GENMASK(7, 6),
+ GPIO1C3_GPIO = 0,
+ GPIO1C3_EMMC_DATA1 = (2 << 6),
+
+ GPIO1C2_MASK = GENMASK(5, 4),
+ GPIO1C2_GPIO = 0,
+ GPIO1C2_EMMC_DATA0 = (2 << 4),
+
+ GPIO1C1_MASK = GENMASK(3, 2),
+ GPIO1C1_GPIO = 0,
+ GPIO1C1_SPI1_RXD = (2 << 2),
+
+ GPIO1C0_MASK = GENMASK(1, 0),
+ GPIO1C0_GPIO = 0,
+ GPIO1C0_SPI1_TXD = (2 << 0),
+};
+
+/* GRF_GPIO1D_IOMUX*/
+enum {
+ GPIO1D3_MASK = GENMASK(7, 6),
+ GPIO1D3_GPIO = 0,
+ GPIO1D3_EMMC_PWREN = (2 << 6),
+
+ GPIO1D2_MASK = GENMASK(5, 4),
+ GPIO1D2_GPIO = 0,
+ GPIO1D2_EMMC_CMD = (2 << 4),
+
+ GPIO1D1_MASK = GENMASK(3, 2),
+ GPIO1D1_GPIO = 0,
+ GPIO1D1_EMMC_DATA7 = (2 << 2),
+
+ GPIO1D0_MASK = GENMASK(1, 0),
+ GPIO1D0_GPIO = 0,
+ GPIO1D0_EMMC_DATA6 = (2 << 0),
+};
+
+
+/*GRF_GPIO3B_IOMUX*/
+enum {
+ GPIO3B7_MASK = GENMASK(15, 14),
+ GPIO3B7_GPIO = 0,
+ GPIO3B7_MAC_RXD0 = (1 << 14),
+
+ GPIO3B6_MASK = GENMASK(13, 12),
+ GPIO3B6_GPIO = 0,
+ GPIO3B6_MAC_TXD3 = (1 << 12),
+
+ GPIO3B5_MASK = GENMASK(11, 10),
+ GPIO3B5_GPIO = 0,
+ GPIO3B5_MAC_TXEN = (1 << 10),
+
+ GPIO3B4_MASK = GENMASK(9, 8),
+ GPIO3B4_GPIO = 0,
+ GPIO3B4_MAC_COL = (1 << 8),
+
+ GPIO3B3_MASK = GENMASK(7, 6),
+ GPIO3B3_GPIO = 0,
+ GPIO3B3_MAC_CRS = (1 << 6),
+
+ GPIO3B2_MASK = GENMASK(5, 4),
+ GPIO3B2_GPIO = 0,
+ GPIO3B2_MAC_TXD2 = (1 << 4),
+
+ GPIO3B1_MASK = GENMASK(3, 2),
+ GPIO3B1_GPIO = 0,
+ GPIO3B1_MAC_TXD1 = (1 << 2),
+
+ GPIO3B0_MASK = GENMASK(1, 0),
+ GPIO3B0_GPIO = 0,
+ GPIO3B0_MAC_TXD0 = (1 << 0),
+ GPIO3B0_PWM0 = (2 << 0),
+};
+
+/* GRF_GPIO3C_IOMUX */
+enum {
+ GPIO3C6_MASK = GENMASK(13, 12),
+ GPIO3C6_GPIO = 0,
+ GPIO3C6_MAC_CLK = (1 << 12),
+
+ GPIO3C5_MASK = GENMASK(11, 10),
+ GPIO3C5_GPIO = 0,
+ GPIO3C5_MAC_RXEN = (1 << 10),
+
+ GPIO3C4_MASK = GENMASK(9, 8),
+ GPIO3C4_GPIO = 0,
+ GPIO3C4_MAC_RXDV = (1 << 8),
+
+ GPIO3C3_MASK = GENMASK(7, 6),
+ GPIO3C3_GPIO = 0,
+ GPIO3C3_MAC_MDC = (1 << 6),
+
+ GPIO3C2_MASK = GENMASK(5, 4),
+ GPIO3C2_GPIO = 0,
+ GPIO3C2_MAC_RXD3 = (1 << 4),
+
+ GPIO3C1_MASK = GENMASK(3, 2),
+ GPIO3C1_GPIO = 0,
+ GPIO3C1_MAC_RXD2 = (1 << 2),
+
+ GPIO3C0_MASK = GENMASK(1, 0),
+ GPIO3C0_GPIO = 0,
+ GPIO3C0_MAC_RXD1 = (1 << 0),
+};
+
+/* GRF_GPIO3D_IOMUX */
+enum {
+ GPIO3D4_MASK = GENMASK(9, 8),
+ GPIO3D4_GPIO = 0,
+ GPIO3D4_MAC_TXCLK = (1 << 8),
+
+ GPIO3D1_MASK = GENMASK(3, 2),
+ GPIO3D1_GPIO = 0,
+ GPIO3D1_MAC_RXCLK = (1 << 2),
+
+ GPIO3D0_MASK = GENMASK(1, 0),
+ GPIO3D0_GPIO = 0,
+ GPIO3D0_MAC_MDIO = (1 << 0),
+};
+
struct rk3368_pinctrl_priv {
struct rk3368_grf *grf;
struct rk3368_pmu_grf *pmugrf;
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 37/66] rockchip: pinctrl: rk3368: add SPI support
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (35 preceding siblings ...)
2017-07-28 19:22 ` [U-Boot] [PATCH v3 36/66] rockchip: pinctrl: rk3368: move IOMUX bit-definitions to pinctrl driver Philipp Tomsich
@ 2017-07-28 19:22 ` Philipp Tomsich
2017-07-28 19:22 ` [U-Boot] [PATCH v3 38/66] rockchip: clk: rk3368: implement bandwidth adjust for PLLs Philipp Tomsich
` (28 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:22 UTC (permalink / raw)
To: u-boot
To implement pinctrl support for the RK3368, we need to add the
bit-definitions to configure the IOMUX and tie these into the
pinctrl framework. This also adds the mapping from the IRQ# back
onto the periheral id for the SPI devices.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
Changes in v3: None
Changes in v2: None
drivers/pinctrl/rockchip/pinctrl_rk3368.c | 90 +++++++++++++++++++++++++++++++
1 file changed, 90 insertions(+)
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3368.c b/drivers/pinctrl/rockchip/pinctrl_rk3368.c
index 67695ab..7a3b7c16 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3368.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3368.c
@@ -1,8 +1,11 @@
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
* Author: Andy Yan <andy.yan@rock-chips.com>
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
* SPDX-License-Identifier: GPL-2.0+
*/
+
#include <common.h>
#include <dm.h>
#include <errno.h>
@@ -16,6 +19,25 @@
DECLARE_GLOBAL_DATA_PTR;
+/* PMUGRF_GPIO0B_IOMUX */
+enum {
+ GPIO0B5_MASK = GENMASK(11, 10),
+ GPIO0B5_GPIO = 0,
+ GPIO0B5_SPI2_CSN0 = (2 << 10),
+
+ GPIO0B4_MASK = GENMASK(9, 8),
+ GPIO0B4_GPIO = 0,
+ GPIO0B4_SPI2_CLK = (2 << 8),
+
+ GPIO0B3_MASK = GENMASK(7, 6),
+ GPIO0B3_GPIO = 0,
+ GPIO0B3_SPI2_TXD = (2 << 6),
+
+ GPIO0B2_MASK = GENMASK(5, 4),
+ GPIO0B2_GPIO = 0,
+ GPIO0B2_SPI2_RXD = (2 << 4),
+};
+
/*GRF_GPIO0C_IOMUX*/
enum {
GPIO0C7_MASK = GENMASK(15, 14),
@@ -209,10 +231,12 @@ enum {
GPIO1C7_MASK = GENMASK(15, 14),
GPIO1C7_GPIO = 0,
GPIO1C7_EMMC_DATA5 = (2 << 14),
+ GPIO1C7_SPI0_TXD = (3 << 14),
GPIO1C6_MASK = GENMASK(13, 12),
GPIO1C6_GPIO = 0,
GPIO1C6_EMMC_DATA4 = (2 << 12),
+ GPIO1C6_SPI0_RXD = (3 << 12),
GPIO1C5_MASK = GENMASK(11, 10),
GPIO1C5_GPIO = 0,
@@ -241,6 +265,10 @@ enum {
/* GRF_GPIO1D_IOMUX*/
enum {
+ GPIO1D5_MASK = GENMASK(11, 10),
+ GPIO1D5_GPIO = 0,
+ GPIO1D5_SPI0_CLK = (2 << 10),
+
GPIO1D3_MASK = GENMASK(7, 6),
GPIO1D3_GPIO = 0,
GPIO1D3_EMMC_PWREN = (2 << 6),
@@ -252,10 +280,12 @@ enum {
GPIO1D1_MASK = GENMASK(3, 2),
GPIO1D1_GPIO = 0,
GPIO1D1_EMMC_DATA7 = (2 << 2),
+ GPIO1D1_SPI0_CSN1 = (3 << 2),
GPIO1D0_MASK = GENMASK(1, 0),
GPIO1D0_GPIO = 0,
GPIO1D0_EMMC_DATA6 = (2 << 0),
+ GPIO1D0_SPI0_CSN0 = (3 << 0),
};
@@ -331,6 +361,7 @@ enum {
GPIO3D4_MASK = GENMASK(9, 8),
GPIO3D4_GPIO = 0,
GPIO3D4_MAC_TXCLK = (1 << 8),
+ GPIO3D4_SPI1_CNS1 = (2 << 8),
GPIO3D1_MASK = GENMASK(3, 2),
GPIO3D1_GPIO = 0,
@@ -377,6 +408,54 @@ static void pinctrl_rk3368_uart_config(struct rk3368_pinctrl_priv *priv,
}
}
+static void pinctrl_rk3368_spi_config(struct rk3368_pinctrl_priv *priv,
+ int spi_id)
+{
+ struct rk3368_grf *grf = priv->grf;
+ struct rk3368_pmu_grf *pmugrf = priv->pmugrf;
+
+ switch (spi_id) {
+ case PERIPH_ID_SPI0:
+ /*
+ * eMMC can only be connected with 4 bits, when SPI0 is used.
+ * This is all-or-nothing, so we assume that if someone asks us
+ * to configure SPI0, that their eMMC interface is unused or
+ * configured appropriately.
+ */
+ rk_clrsetreg(&grf->gpio1d_iomux,
+ GPIO1D0_MASK | GPIO1D1_MASK |
+ GPIO1D5_MASK,
+ GPIO1D0_SPI0_CSN0 | GPIO1D1_SPI0_CSN1 |
+ GPIO1D5_SPI0_CLK);
+ rk_clrsetreg(&grf->gpio1c_iomux,
+ GPIO1C6_MASK | GPIO1C7_MASK,
+ GPIO1C6_SPI0_RXD | GPIO1C7_SPI0_TXD);
+ break;
+ case PERIPH_ID_SPI1:
+ /*
+ * We don't implement support for configuring SPI1_CSN#1, as it
+ * will conflicts with the GMAC (MAC TX clk-out).
+ */
+ rk_clrsetreg(&grf->gpio1b_iomux,
+ GPIO1B6_MASK | GPIO1B7_MASK,
+ GPIO1B6_SPI1_CLK | GPIO1B7_SPI1_CSN0);
+ rk_clrsetreg(&grf->gpio1c_iomux,
+ GPIO1C0_MASK | GPIO1C1_MASK,
+ GPIO1C0_SPI1_TXD | GPIO1C1_SPI1_RXD);
+ break;
+ case PERIPH_ID_SPI2:
+ rk_clrsetreg(&pmugrf->gpio0b_iomux,
+ GPIO0B2_MASK | GPIO0B3_MASK |
+ GPIO0B4_MASK | GPIO0B5_MASK,
+ GPIO0B2_SPI2_RXD | GPIO0B3_SPI2_TXD |
+ GPIO0B4_SPI2_CLK | GPIO0B5_SPI2_CSN0);
+ break;
+ default:
+ debug("%s: spi id = %d iomux error!\n", __func__, spi_id);
+ break;
+ }
+}
+
#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
static void pinctrl_rk3368_gmac_config(struct rk3368_grf *grf, int gmac_id)
{
@@ -457,6 +536,11 @@ static int rk3368_pinctrl_request(struct udevice *dev, int func, int flags)
case PERIPH_ID_UART4:
pinctrl_rk3368_uart_config(priv, func);
break;
+ case PERIPH_ID_SPI0:
+ case PERIPH_ID_SPI1:
+ case PERIPH_ID_SPI2:
+ pinctrl_rk3368_spi_config(priv, func);
+ break;
case PERIPH_ID_EMMC:
case PERIPH_ID_SDCARD:
pinctrl_rk3368_sdmmc_config(priv->grf, func);
@@ -495,6 +579,12 @@ static int rk3368_pinctrl_get_periph_id(struct udevice *dev,
return PERIPH_ID_UART1;
case 55:
return PERIPH_ID_UART0;
+ case 44:
+ return PERIPH_ID_SPI0;
+ case 45:
+ return PERIPH_ID_SPI1;
+ case 41:
+ return PERIPH_ID_SPI2;
case 35:
return PERIPH_ID_EMMC;
case 32:
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 38/66] rockchip: clk: rk3368: implement bandwidth adjust for PLLs
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (36 preceding siblings ...)
2017-07-28 19:22 ` [U-Boot] [PATCH v3 37/66] rockchip: pinctrl: rk3368: add SPI support Philipp Tomsich
@ 2017-07-28 19:22 ` Philipp Tomsich
2017-07-28 19:22 ` [U-Boot] [PATCH v3 39/66] rockchip: clk: rk3368: support OF_PLATDATA for the RK3368 clk driver Philipp Tomsich
` (27 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:22 UTC (permalink / raw)
To: u-boot
The RK3368 TRM recommends to configure the bandwith adjustment (CON2)
for PLLs to NF/2. This implements this for all reconfigurations of
PLLs and removes the 'has_bwadj' flag (as the RK3368 always has the
bandwidth-adjustment feature according to its manual).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
Changes in v3: None
Changes in v2: None
drivers/clk/rockchip/clk_rk3368.c | 17 ++++++++++++-----
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c
index e1d9aeb..d8f06d5 100644
--- a/drivers/clk/rockchip/clk_rk3368.c
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -1,6 +1,7 @@
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
* Author: Andy Yan <andy.yan@rock-chips.com>
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
* SPDX-License-Identifier: GPL-2.0
*/
@@ -74,7 +75,7 @@ static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru,
}
static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id,
- const struct pll_div *div, bool has_bwadj)
+ const struct pll_div *div)
{
struct rk3368_pll *pll = &cru->pll[pll_id];
/* All PLLs have same VCO and output frequency range restrictions*/
@@ -92,6 +93,12 @@ static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id,
((div->nr - 1) << PLL_NR_SHIFT) |
((div->no - 1) << PLL_OD_SHIFT));
writel((div->nf - 1) << PLL_NF_SHIFT, &pll->con1);
+ /*
+ * BWADJ should be set to NF / 2 to ensure the nominal bandwidth.
+ * Compare the RK3368 TRM, section "3.6.4 PLL Bandwidth Adjustment".
+ */
+ clrsetbits_le32(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
+
udelay(10);
/* return from reset */
@@ -111,10 +118,10 @@ static void rkclk_init(struct rk3368_cru *cru)
{
u32 apllb, aplll, dpll, cpll, gpll;
- rkclk_set_pll(cru, APLLB, &apll_b_init_cfg, false);
- rkclk_set_pll(cru, APLLL, &apll_l_init_cfg, false);
- rkclk_set_pll(cru, GPLL, &gpll_init_cfg, false);
- rkclk_set_pll(cru, CPLL, &cpll_init_cfg, false);
+ rkclk_set_pll(cru, APLLB, &apll_b_init_cfg);
+ rkclk_set_pll(cru, APLLL, &apll_l_init_cfg);
+ rkclk_set_pll(cru, GPLL, &gpll_init_cfg);
+ rkclk_set_pll(cru, CPLL, &cpll_init_cfg);
apllb = rkclk_pll_get_rate(cru, APLLB);
aplll = rkclk_pll_get_rate(cru, APLLL);
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 39/66] rockchip: clk: rk3368: support OF_PLATDATA for the RK3368 clk driver
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (37 preceding siblings ...)
2017-07-28 19:22 ` [U-Boot] [PATCH v3 38/66] rockchip: clk: rk3368: implement bandwidth adjust for PLLs Philipp Tomsich
@ 2017-07-28 19:22 ` Philipp Tomsich
2017-07-28 19:22 ` [U-Boot] [PATCH v3 40/66] rockchip: clk: rk3368: do not change CPLL/GPLL before returning to BROM Philipp Tomsich
` (26 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:22 UTC (permalink / raw)
To: u-boot
With the RK3368's limited TPL size, we'll want to use OF_PLATFDATA for
the SPL stage. This implements support for OF_PLATDATA in the clock
driver for the RK3368.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
Changes in v3: None
Changes in v2: None
drivers/clk/rockchip/clk_rk3368.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c
index d8f06d5..809ad19 100644
--- a/drivers/clk/rockchip/clk_rk3368.c
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -8,7 +8,9 @@
#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
+#include <dt-structs.h>
#include <errno.h>
+#include <mapmem.h>
#include <syscon.h>
#include <asm/arch/clock.h>
#include <asm/arch/cru_rk3368.h>
@@ -19,6 +21,12 @@
DECLARE_GLOBAL_DATA_PTR;
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+struct rk3368_clk_plat {
+ struct dtd_rockchip_rk3368_cru dtd;
+};
+#endif
+
struct pll_div {
u32 nr;
u32 nf;
@@ -254,7 +262,11 @@ static struct clk_ops rk3368_clk_ops = {
static int rk3368_clk_probe(struct udevice *dev)
{
struct rk3368_clk_priv *priv = dev_get_priv(dev);
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct rk3368_clk_plat *plat = dev_get_platdata(dev);
+ priv->cru = map_sysmem(plat->dtd.reg[1], plat->dtd.reg[3]);
+#endif
rkclk_init(priv->cru);
return 0;
@@ -262,9 +274,11 @@ static int rk3368_clk_probe(struct udevice *dev)
static int rk3368_clk_ofdata_to_platdata(struct udevice *dev)
{
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3368_clk_priv *priv = dev_get_priv(dev);
priv->cru = (struct rk3368_cru *)devfdt_get_addr(dev);
+#endif
return 0;
}
@@ -291,6 +305,9 @@ U_BOOT_DRIVER(rockchip_rk3368_cru) = {
.id = UCLASS_CLK,
.of_match = rk3368_clk_ids,
.priv_auto_alloc_size = sizeof(struct rk3368_clk_priv),
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ .platdata_auto_alloc_size = sizeof(struct rk3368_clk_plat),
+#endif
.ofdata_to_platdata = rk3368_clk_ofdata_to_platdata,
.ops = &rk3368_clk_ops,
.bind = rk3368_clk_bind,
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 40/66] rockchip: clk: rk3368: do not change CPLL/GPLL before returning to BROM
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (38 preceding siblings ...)
2017-07-28 19:22 ` [U-Boot] [PATCH v3 39/66] rockchip: clk: rk3368: support OF_PLATDATA for the RK3368 clk driver Philipp Tomsich
@ 2017-07-28 19:22 ` Philipp Tomsich
2017-07-28 19:22 ` [U-Boot] [PATCH v3 41/66] rockchip: clk: rk3368: implement DPLL (DRAM PLL) support Philipp Tomsich
` (25 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:22 UTC (permalink / raw)
To: u-boot
The RK3368 has a somewhat temperamental BootROM (which I learned the
hard way) when it comes to reconfiguring the CPLL and GPLL (in fact,
experiments show that changing the GPLL broke things for me, while
changing the CPLL seems to be more benign). These should not be
modified by the SPL stage, if we intend to return to the BootROM for
chain booting the next stage.
This commit changes the clock initialisation to not change CPLL/GPLL
before returning to the BootROM (i.e. in TPL). As it's safe to change
these settings if we no longer intend to return to U-Boot, we'll run
the full PLL setup a little later (i.e. in SPL).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
Changes in v3: None
Changes in v2: None
drivers/clk/rockchip/clk_rk3368.c | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c
index 809ad19..d05be72 100644
--- a/drivers/clk/rockchip/clk_rk3368.c
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -50,10 +50,14 @@ struct pll_div {
(_nr * _no) == hz, #hz "Hz cannot be hit with PLL " \
"divisors on line " __stringify(__LINE__));
+#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2);
static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2);
+#if !defined(CONFIG_TPL_BUILD)
static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2);
static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6);
+#endif
+#endif
/* Get pll rate by id */
static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru,
@@ -82,6 +86,7 @@ static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru,
}
}
+#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id,
const struct pll_div *div)
{
@@ -121,15 +126,23 @@ static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id,
return 0;
}
+#endif
+#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
static void rkclk_init(struct rk3368_cru *cru)
{
u32 apllb, aplll, dpll, cpll, gpll;
rkclk_set_pll(cru, APLLB, &apll_b_init_cfg);
rkclk_set_pll(cru, APLLL, &apll_l_init_cfg);
+#if !defined(CONFIG_TPL_BUILD)
+ /*
+ * If we plan to return to the boot ROM, we can't increase the
+ * GPLL rate from the SPL stage.
+ */
rkclk_set_pll(cru, GPLL, &gpll_init_cfg);
rkclk_set_pll(cru, CPLL, &cpll_init_cfg);
+#endif
apllb = rkclk_pll_get_rate(cru, APLLB);
aplll = rkclk_pll_get_rate(cru, APLLL);
@@ -140,6 +153,7 @@ static void rkclk_init(struct rk3368_cru *cru)
debug("%s apllb(%d) apll(%d) dpll(%d) cpll(%d) gpll(%d)\n",
__func__, apllb, aplll, dpll, cpll, gpll);
}
+#endif
static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id)
{
@@ -261,13 +275,15 @@ static struct clk_ops rk3368_clk_ops = {
static int rk3368_clk_probe(struct udevice *dev)
{
- struct rk3368_clk_priv *priv = dev_get_priv(dev);
+ struct rk3368_clk_priv __maybe_unused *priv = dev_get_priv(dev);
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3368_clk_plat *plat = dev_get_platdata(dev);
priv->cru = map_sysmem(plat->dtd.reg[1], plat->dtd.reg[3]);
#endif
+#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
rkclk_init(priv->cru);
+#endif
return 0;
}
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 41/66] rockchip: clk: rk3368: implement DPLL (DRAM PLL) support
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (39 preceding siblings ...)
2017-07-28 19:22 ` [U-Boot] [PATCH v3 40/66] rockchip: clk: rk3368: do not change CPLL/GPLL before returning to BROM Philipp Tomsich
@ 2017-07-28 19:22 ` Philipp Tomsich
2017-07-28 19:22 ` [U-Boot] [PATCH v3 42/66] rockchip: clk: rk3368: define DMA1_SRST_REQ and DMA2_SRST_REQ Philipp Tomsich
` (24 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:22 UTC (permalink / raw)
To: u-boot
To implement a TPL stage (incl. its DRAM controller setup) for the
RK3368, we'll want to configure the DPLL (DRAM PLL).
This commit implements setting the DPLL (CLK_DDR) and provides PLL
configuration details for the common DRAM operating speeds found on
RK3368 boards.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
Changes in v3: None
Changes in v2: None
drivers/clk/rockchip/clk_rk3368.c | 35 +++++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c
index d05be72..33d2946 100644
--- a/drivers/clk/rockchip/clk_rk3368.c
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -250,6 +250,37 @@ static ulong rk3368_clk_get_rate(struct clk *clk)
return rate;
}
+static ulong rk3368_ddr_set_clk(struct rk3368_cru *cru, ulong set_rate)
+{
+ const struct pll_div *dpll_cfg = NULL;
+ const ulong MHz = 1000000;
+
+ /* Fout = ((Fin /NR) * NF )/ NO */
+ static const struct pll_div dpll_1200 =
+ PLL_DIVISORS(1200 * MHz, 1, 1);
+ static const struct pll_div dpll_1332 =
+ PLL_DIVISORS(1332 * MHz, 2, 1);
+ static const struct pll_div dpll_1600 =
+ PLL_DIVISORS(1600 * MHz, 3, 2);
+
+ switch (set_rate) {
+ case 1200*MHz:
+ dpll_cfg = &dpll_1200;
+ break;
+ case 1332*MHz:
+ dpll_cfg = &dpll_1332;
+ break;
+ case 1600*MHz:
+ dpll_cfg = &dpll_1600;
+ break;
+ default:
+ error("Unsupported SDRAM frequency!,%ld\n", set_rate);
+ }
+ rkclk_set_pll(cru, DPLL, dpll_cfg);
+
+ return set_rate;
+}
+
static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
{
struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
@@ -257,6 +288,10 @@ static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
debug("%s id:%ld rate:%ld\n", __func__, clk->id, rate);
switch (clk->id) {
+ case CLK_DDR:
+ ret = rk3368_ddr_set_clk(priv->cru, rate);
+ break;
+
case SCLK_SDMMC:
case SCLK_EMMC:
ret = rk3368_mmc_set_clk(priv->cru, clk->id, rate);
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 42/66] rockchip: clk: rk3368: define DMA1_SRST_REQ and DMA2_SRST_REQ
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (40 preceding siblings ...)
2017-07-28 19:22 ` [U-Boot] [PATCH v3 41/66] rockchip: clk: rk3368: implement DPLL (DRAM PLL) support Philipp Tomsich
@ 2017-07-28 19:22 ` Philipp Tomsich
2017-07-28 19:22 ` [U-Boot] [PATCH v3 43/66] rockchip: clk: rk3368: implement MMC/SD clock reparenting Philipp Tomsich
` (23 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:22 UTC (permalink / raw)
To: u-boot
On he RK3368, we need to temporarily disable security on the DMA
engines during TPL and SPL to allow the MMC host to DMA into DRAM. To
do so, we need to reset the two DMA engines, which in turn requires
the DMA1_SRST_REQ and DMA2_SRST_REQ constants to refer to the
appropriate bits in the CRU.
As the ATF correctly initialises security (and only leaves EL3 after
doing so), this can not pose a security issue.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
Changes in v3: None
Changes in v2: None
arch/arm/include/asm/arch-rockchip/cru_rk3368.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
index 24a9cc0..bf09e2f 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
@@ -102,6 +102,10 @@ enum {
/* SOFTRST1_CON */
MCU_PO_SRST_MASK = BIT(13),
MCU_SYS_SRST_MASK = BIT(12),
+ DMA1_SRST_REQ = BIT(2),
+
+ /* SOFTRST4_CON */
+ DMA2_SRST_REQ = BIT(0),
/* GLB_RST_CON */
PMU_GLB_SRST_CTRL_SHIFT = 2,
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 43/66] rockchip: clk: rk3368: implement MMC/SD clock reparenting
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (41 preceding siblings ...)
2017-07-28 19:22 ` [U-Boot] [PATCH v3 42/66] rockchip: clk: rk3368: define DMA1_SRST_REQ and DMA2_SRST_REQ Philipp Tomsich
@ 2017-07-28 19:22 ` Philipp Tomsich
2017-07-28 19:22 ` [U-Boot] [PATCH v3 44/66] rockchip: clk: rk3368: support configuring the DRAM PLL (from TPL) Philipp Tomsich
` (22 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:22 UTC (permalink / raw)
To: u-boot
The original clock support for MMC/SD cards on the RK3368 suffered
from a tendency to select a divider less-or-equal to the the one
giving the requested clock-rate: this can lead to higher-than-expected
(or rather: higher than supported) clock rates for the MMC/SD
communiction.
This change rewrites the MMC/SD clock generation to:
* always generate a clock less-than-or-equal to the requested clock
* support reparenting among the CPLL, GPLL and OSC24M parents to
generate the highest clock that does not exceed the requested rate
In addition to this, the Linux DTS uses HCLK_MMC/HCLK_SDMMC instead of
SCLK_MMC/SCLK_SDMMC: to match this (and to ensure that clock setup
always works), we adjust the driver appropriately.
This includes the changes from:
- rockchip: clk: rk3368: convert MMC_PLL_SEL_* definitions to shifted-value form
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
Changes in v3: None
Changes in v2: None
arch/arm/include/asm/arch-rockchip/cru_rk3368.h | 8 +-
drivers/clk/rockchip/clk_rk3368.c | 119 ++++++++++++++++++------
2 files changed, 95 insertions(+), 32 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
index bf09e2f..21f11e0 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
@@ -92,10 +92,10 @@ enum {
/* CLKSEL51_CON */
MMC_PLL_SEL_SHIFT = 8,
MMC_PLL_SEL_MASK = GENMASK(9, 8),
- MMC_PLL_SEL_CPLL = 0,
- MMC_PLL_SEL_GPLL,
- MMC_PLL_SEL_USBPHY_480M,
- MMC_PLL_SEL_24M,
+ MMC_PLL_SEL_CPLL = (0 << MMC_PLL_SEL_SHIFT),
+ MMC_PLL_SEL_GPLL = (1 << MMC_PLL_SEL_SHIFT),
+ MMC_PLL_SEL_USBPHY_480M = (2 << MMC_PLL_SEL_SHIFT),
+ MMC_PLL_SEL_24M = (3 << MMC_PLL_SEL_SHIFT),
MMC_CLK_DIV_SHIFT = 0,
MMC_CLK_DIV_MASK = GENMASK(6, 0),
diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c
index 33d2946..1327116 100644
--- a/drivers/clk/rockchip/clk_rk3368.c
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -59,6 +59,8 @@ static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6);
#endif
#endif
+static ulong rk3368_clk_get_rate(struct clk *clk);
+
/* Get pll rate by id */
static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru,
enum rk3368_pll_id pll_id)
@@ -155,16 +157,17 @@ static void rkclk_init(struct rk3368_cru *cru)
}
#endif
+#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)
static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id)
{
u32 div, con, con_id, rate;
u32 pll_rate;
switch (clk_id) {
- case SCLK_SDMMC:
+ case HCLK_SDMMC:
con_id = 50;
break;
- case SCLK_EMMC:
+ case HCLK_EMMC:
con_id = 51;
break;
case SCLK_SDIO0:
@@ -175,7 +178,7 @@ static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id)
}
con = readl(&cru->clksel_con[con_id]);
- switch ((con & MMC_PLL_SEL_MASK) >> MMC_PLL_SEL_SHIFT) {
+ switch (con & MMC_PLL_SEL_MASK) {
case MMC_PLL_SEL_GPLL:
pll_rate = rkclk_pll_get_rate(cru, GPLL);
break;
@@ -183,6 +186,8 @@ static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id)
pll_rate = OSC_HZ;
break;
case MMC_PLL_SEL_CPLL:
+ pll_rate = rkclk_pll_get_rate(cru, CPLL);
+ break;
case MMC_PLL_SEL_USBPHY_480M:
default:
return -EINVAL;
@@ -190,23 +195,76 @@ static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id)
div = (con & MMC_CLK_DIV_MASK) >> MMC_CLK_DIV_SHIFT;
rate = DIV_TO_RATE(pll_rate, div);
+ debug("%s: raw rate %d (post-divide by 2)\n", __func__, rate);
return rate >> 1;
}
-static ulong rk3368_mmc_set_clk(struct rk3368_cru *cru,
- ulong clk_id, ulong rate)
+static ulong rk3368_mmc_find_best_rate_and_parent(struct clk *clk,
+ ulong rate,
+ u32 *best_mux,
+ u32 *best_div)
+{
+ int i;
+ ulong best_rate = 0;
+ const ulong MHz = 1000000;
+ const struct {
+ u32 mux;
+ ulong rate;
+ } parents[] = {
+ { .mux = MMC_PLL_SEL_CPLL, .rate = CPLL_HZ },
+ { .mux = MMC_PLL_SEL_GPLL, .rate = GPLL_HZ },
+ { .mux = MMC_PLL_SEL_24M, .rate = 24 * MHz }
+ };
+
+ debug("%s: target rate %ld\n", __func__, rate);
+ for (i = 0; i < ARRAY_SIZE(parents); ++i) {
+ /*
+ * Find the largest rate no larger than the target-rate for
+ * the current parent.
+ */
+ ulong parent_rate = parents[i].rate;
+ u32 div = DIV_ROUND_UP(parent_rate, rate);
+ u32 adj_div = div;
+ ulong new_rate = parent_rate / adj_div;
+
+ debug("%s: rate %ld, parent-mux %d, parent-rate %ld, div %d\n",
+ __func__, rate, parents[i].mux, parents[i].rate, div);
+
+ /* Skip, if not representable */
+ if ((div - 1) > MMC_CLK_DIV_MASK)
+ continue;
+
+ /* Skip, if we already have a better (or equal) solution */
+ if (new_rate <= best_rate)
+ continue;
+
+ /* This is our new best rate. */
+ best_rate = new_rate;
+ *best_mux = parents[i].mux;
+ *best_div = div - 1;
+ }
+
+ debug("%s: best_mux = %x, best_div = %d, best_rate = %ld\n",
+ __func__, *best_mux, *best_div, best_rate);
+
+ return best_rate;
+}
+
+static ulong rk3368_mmc_set_clk(struct clk *clk, ulong rate)
{
- u32 div;
- u32 con_id;
- u32 gpll_rate = rkclk_pll_get_rate(cru, GPLL);
+ struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
+ struct rk3368_cru *cru = priv->cru;
+ ulong clk_id = clk->id;
+ u32 con_id, mux = 0, div = 0;
- div = RATE_TO_DIV(gpll_rate, rate << 1);
+ /* Find the best parent and rate */
+ rk3368_mmc_find_best_rate_and_parent(clk, rate << 1, &mux, &div);
switch (clk_id) {
- case SCLK_SDMMC:
+ case HCLK_SDMMC:
con_id = 50;
break;
- case SCLK_EMMC:
+ case HCLK_EMMC:
con_id = 51;
break;
case SCLK_SDIO0:
@@ -216,33 +274,33 @@ static ulong rk3368_mmc_set_clk(struct rk3368_cru *cru,
return -EINVAL;
}
- if (div > 0x3f) {
- div = RATE_TO_DIV(OSC_HZ, rate);
- rk_clrsetreg(&cru->clksel_con[con_id],
- MMC_PLL_SEL_MASK | MMC_CLK_DIV_MASK,
- (MMC_PLL_SEL_24M << MMC_PLL_SEL_SHIFT) |
- (div << MMC_CLK_DIV_SHIFT));
- } else {
- rk_clrsetreg(&cru->clksel_con[con_id],
- MMC_PLL_SEL_MASK | MMC_CLK_DIV_MASK,
- (MMC_PLL_SEL_GPLL << MMC_PLL_SEL_SHIFT) |
- div << MMC_CLK_DIV_SHIFT);
- }
+ rk_clrsetreg(&cru->clksel_con[con_id],
+ MMC_PLL_SEL_MASK | MMC_CLK_DIV_MASK,
+ mux | div);
return rk3368_mmc_get_clk(cru, clk_id);
}
+#endif
static ulong rk3368_clk_get_rate(struct clk *clk)
{
struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
ulong rate = 0;
- debug("%s id:%ld\n", __func__, clk->id);
+ debug("%s: id %ld\n", __func__, clk->id);
switch (clk->id) {
+ case PLL_CPLL:
+ rate = rkclk_pll_get_rate(priv->cru, CPLL);
+ break;
+ case PLL_GPLL:
+ rate = rkclk_pll_get_rate(priv->cru, GPLL);
+ break;
+#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)
case HCLK_SDMMC:
case HCLK_EMMC:
rate = rk3368_mmc_get_clk(priv->cru, clk->id);
break;
+#endif
default:
return -ENOENT;
}
@@ -291,10 +349,15 @@ static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
case CLK_DDR:
ret = rk3368_ddr_set_clk(priv->cru, rate);
break;
-
- case SCLK_SDMMC:
- case SCLK_EMMC:
- ret = rk3368_mmc_set_clk(priv->cru, clk->id, rate);
+#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)
+ case HCLK_SDMMC:
+ case HCLK_EMMC:
+ ret = rk3368_mmc_set_clk(clk, rate);
+ break;
+#endif
+ case SCLK_MAC:
+ /* nothing to do, as this is an external clock */
+ ret = rate;
break;
default:
return -ENOENT;
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 44/66] rockchip: clk: rk3368: support configuring the DRAM PLL (from TPL)
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (42 preceding siblings ...)
2017-07-28 19:22 ` [U-Boot] [PATCH v3 43/66] rockchip: clk: rk3368: implement MMC/SD clock reparenting Philipp Tomsich
@ 2017-07-28 19:22 ` Philipp Tomsich
2017-07-28 19:22 ` [U-Boot] [PATCH v3 45/66] rockchip: clk: rk3368: add support for GMAC (SLCK_MAC) clock Philipp Tomsich
` (21 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:22 UTC (permalink / raw)
To: u-boot
As part of the DRAM initialisation process (running as part of the TPL
stage) on the RK3368, we need to set up the DRAM PLL.
This implements support for configuring the PLL to for 1200, 1332 or
1600 MHz (i.e. for DDR3-1200, DDR3-1333, DDR3-1600 operating modes).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
Changes in v3: None
Changes in v2: None
drivers/clk/rockchip/clk_rk3368.c | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c
index 1327116..1bed4e2 100644
--- a/drivers/clk/rockchip/clk_rk3368.c
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -308,18 +308,16 @@ static ulong rk3368_clk_get_rate(struct clk *clk)
return rate;
}
+#if IS_ENABLED(CONFIG_TPL_BUILD)
static ulong rk3368_ddr_set_clk(struct rk3368_cru *cru, ulong set_rate)
{
const struct pll_div *dpll_cfg = NULL;
const ulong MHz = 1000000;
/* Fout = ((Fin /NR) * NF )/ NO */
- static const struct pll_div dpll_1200 =
- PLL_DIVISORS(1200 * MHz, 1, 1);
- static const struct pll_div dpll_1332 =
- PLL_DIVISORS(1332 * MHz, 2, 1);
- static const struct pll_div dpll_1600 =
- PLL_DIVISORS(1600 * MHz, 3, 2);
+ static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1);
+ static const struct pll_div dpll_1332 = PLL_DIVISORS(1332 * MHz, 2, 1);
+ static const struct pll_div dpll_1600 = PLL_DIVISORS(1600 * MHz, 3, 2);
switch (set_rate) {
case 1200*MHz:
@@ -338,6 +336,7 @@ static ulong rk3368_ddr_set_clk(struct rk3368_cru *cru, ulong set_rate)
return set_rate;
}
+#endif
static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
{
@@ -346,9 +345,11 @@ static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
debug("%s id:%ld rate:%ld\n", __func__, clk->id, rate);
switch (clk->id) {
+#if IS_ENABLED(CONFIG_TPL_BUILD)
case CLK_DDR:
ret = rk3368_ddr_set_clk(priv->cru, rate);
break;
+#endif
#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)
case HCLK_SDMMC:
case HCLK_EMMC:
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 45/66] rockchip: clk: rk3368: add support for GMAC (SLCK_MAC) clock
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (43 preceding siblings ...)
2017-07-28 19:22 ` [U-Boot] [PATCH v3 44/66] rockchip: clk: rk3368: support configuring the DRAM PLL (from TPL) Philipp Tomsich
@ 2017-07-28 19:22 ` Philipp Tomsich
2017-07-28 19:22 ` [U-Boot] [PATCH v3 46/66] rockchip: clk: rk3368: mark 'priv' __maybe_unused in rk3368_clk_set_rate() Philipp Tomsich
` (20 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:22 UTC (permalink / raw)
To: u-boot
To enable the GMAC on the RK3368, we need to set up the clocking
appropriately to generate a tx_clk for the MAC.
This adds an implementation that implements the use of the <&ext_gmac>
clock (i.e. an external 125MHz clock for RGMII provided by the PHY).
This is the clock setup used by the boards currently supported by
U-Boot (i.e. Geekbox, Sheep and RK3368-uQ7).
This includes the change from commit
- rockchip: clk: rk3368: define GMAC_MUX_SEL_EXTCLK
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
Changes in v3: None
Changes in v2: None
arch/arm/include/asm/arch-rockchip/cru_rk3368.h | 3 +++
drivers/clk/rockchip/clk_rk3368.c | 19 +++++++++++++++++--
2 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
index 21f11e0..2b1197f 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
@@ -89,6 +89,9 @@ enum {
MCU_CLK_DIV_SHIFT = 0,
MCU_CLK_DIV_MASK = GENMASK(4, 0),
+ /* CLKSEL43_CON */
+ GMAC_MUX_SEL_EXTCLK = BIT(8),
+
/* CLKSEL51_CON */
MMC_PLL_SEL_SHIFT = 8,
MMC_PLL_SEL_MASK = GENMASK(9, 8),
diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c
index 1bed4e2..2b6c8da 100644
--- a/drivers/clk/rockchip/clk_rk3368.c
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -338,6 +338,19 @@ static ulong rk3368_ddr_set_clk(struct rk3368_cru *cru, ulong set_rate)
}
#endif
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
+static ulong rk3368_gmac_set_clk(struct rk3368_cru *cru,
+ ulong clk_id, ulong set_rate)
+{
+ /*
+ * This models the 'assigned-clock-parents = <&ext_gmac>' from
+ * the DTS and switches to the 'ext_gmac' clock parent.
+ */
+ rk_setreg(&cru->clksel_con[43], GMAC_MUX_SEL_EXTCLK);
+ return set_rate;
+}
+#endif
+
static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
{
struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
@@ -356,10 +369,12 @@ static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
ret = rk3368_mmc_set_clk(clk, rate);
break;
#endif
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
case SCLK_MAC:
- /* nothing to do, as this is an external clock */
- ret = rate;
+ /* select the external clock */
+ ret = rk3368_gmac_set_clk(priv->cru, clk->id, rate);
break;
+#endif
default:
return -ENOENT;
}
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 46/66] rockchip: clk: rk3368: mark 'priv' __maybe_unused in rk3368_clk_set_rate()
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (44 preceding siblings ...)
2017-07-28 19:22 ` [U-Boot] [PATCH v3 45/66] rockchip: clk: rk3368: add support for GMAC (SLCK_MAC) clock Philipp Tomsich
@ 2017-07-28 19:22 ` Philipp Tomsich
2017-07-28 19:22 ` [U-Boot] [PATCH v3 47/66] rockchip: clk: rk3368: add support for configuring the SPI clocks Philipp Tomsich
` (19 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:22 UTC (permalink / raw)
To: u-boot
With the clock support in rk3368_clk_set_rate() conditionalized on
various feature definitions, 'priv' can remain unused (e.g. in the
SPL build when only MMC is enabled).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
Changes in v3: None
Changes in v2: None
drivers/clk/rockchip/clk_rk3368.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c
index 2b6c8da..d3f6c29 100644
--- a/drivers/clk/rockchip/clk_rk3368.c
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -353,7 +353,7 @@ static ulong rk3368_gmac_set_clk(struct rk3368_cru *cru,
static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
{
- struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
+ __maybe_unused struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
ulong ret = 0;
debug("%s id:%ld rate:%ld\n", __func__, clk->id, rate);
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 47/66] rockchip: clk: rk3368: add support for configuring the SPI clocks
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (45 preceding siblings ...)
2017-07-28 19:22 ` [U-Boot] [PATCH v3 46/66] rockchip: clk: rk3368: mark 'priv' __maybe_unused in rk3368_clk_set_rate() Philipp Tomsich
@ 2017-07-28 19:22 ` Philipp Tomsich
2017-07-28 19:22 ` [U-Boot] [PATCH v3 48/66] net: gmac_rockchip: Add support for the RK3368 GMAC Philipp Tomsich
` (18 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:22 UTC (permalink / raw)
To: u-boot
As SPI support may be useful in the boot-flow, this adds support for
configuring the SPI controller's clocks in the RK3368 clock driver.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---
Changes in v3: None
Changes in v2:
- added SPI clock setup
drivers/clk/rockchip/clk_rk3368.c | 132 ++++++++++++++++++++++++++++++--------
1 file changed, 106 insertions(+), 26 deletions(-)
diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c
index d3f6c29..04f9b80 100644
--- a/drivers/clk/rockchip/clk_rk3368.c
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -282,32 +282,6 @@ static ulong rk3368_mmc_set_clk(struct clk *clk, ulong rate)
}
#endif
-static ulong rk3368_clk_get_rate(struct clk *clk)
-{
- struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
- ulong rate = 0;
-
- debug("%s: id %ld\n", __func__, clk->id);
- switch (clk->id) {
- case PLL_CPLL:
- rate = rkclk_pll_get_rate(priv->cru, CPLL);
- break;
- case PLL_GPLL:
- rate = rkclk_pll_get_rate(priv->cru, GPLL);
- break;
-#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)
- case HCLK_SDMMC:
- case HCLK_EMMC:
- rate = rk3368_mmc_get_clk(priv->cru, clk->id);
- break;
-#endif
- default:
- return -ENOENT;
- }
-
- return rate;
-}
-
#if IS_ENABLED(CONFIG_TPL_BUILD)
static ulong rk3368_ddr_set_clk(struct rk3368_cru *cru, ulong set_rate)
{
@@ -351,6 +325,109 @@ static ulong rk3368_gmac_set_clk(struct rk3368_cru *cru,
}
#endif
+/*
+ * RK3368 SPI clocks have a common divider-width (7 bits) and a single bit
+ * to select either CPLL or GPLL as the clock-parent. The location within
+ * the enclosing CLKSEL_CON (i.e. div_shift and sel_shift) are variable.
+ */
+
+struct spi_clkreg {
+ uint8_t reg; /* CLKSEL_CON[reg] register in CRU */
+ uint8_t div_shift;
+ uint8_t sel_shift;
+};
+
+/*
+ * The entries are numbered relative to their offset from SCLK_SPI0.
+ */
+static const struct spi_clkreg spi_clkregs[] = {
+ [0] = { .reg = 45, .div_shift = 0, .sel_shift = 7, },
+ [1] = { .reg = 45, .div_shift = 8, .sel_shift = 15, },
+ [2] = { .reg = 46, .div_shift = 8, .sel_shift = 15, },
+};
+
+static inline u32 extract_bits(u32 val, unsigned width, unsigned shift)
+{
+ return (val >> shift) & ((1 << width) - 1);
+}
+
+static ulong rk3368_spi_get_clk(struct rk3368_cru *cru, ulong clk_id)
+{
+ const struct spi_clkreg *spiclk = NULL;
+ u32 div, val;
+
+ switch (clk_id) {
+ case SCLK_SPI0 ... SCLK_SPI2:
+ spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
+ break;
+
+ default:
+ error("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
+ return -EINVAL;
+ }
+
+ val = readl(&cru->clksel_con[spiclk->reg]);
+ div = extract_bits(val, 7, spiclk->div_shift);
+
+ debug("%s: div 0x%x\n", __func__, div);
+ return DIV_TO_RATE(GPLL_HZ, div);
+}
+
+static ulong rk3368_spi_set_clk(struct rk3368_cru *cru, ulong clk_id, uint hz)
+{
+ const struct spi_clkreg *spiclk = NULL;
+ int src_clk_div;
+
+ src_clk_div = RATE_TO_DIV(GPLL_HZ, hz);
+ assert(src_clk_div < 127);
+
+ switch (clk_id) {
+ case SCLK_SPI0 ... SCLK_SPI2:
+ spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
+ break;
+
+ default:
+ error("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
+ return -EINVAL;
+ }
+
+ rk_clrsetreg(&cru->clksel_con[spiclk->reg],
+ ((0x7f << spiclk->div_shift) | (0x1 << spiclk->sel_shift)),
+ ((src_clk_div << spiclk->div_shift) |
+ (1 /* TODO */ << spiclk->sel_shift)));
+
+ return rk3368_spi_get_clk(cru, clk_id);
+}
+
+static ulong rk3368_clk_get_rate(struct clk *clk)
+{
+ struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
+ ulong rate = 0;
+
+ debug("%s: id %ld\n", __func__, clk->id);
+ switch (clk->id) {
+ case PLL_CPLL:
+ rate = rkclk_pll_get_rate(priv->cru, CPLL);
+ break;
+ case PLL_GPLL:
+ rate = rkclk_pll_get_rate(priv->cru, GPLL);
+ break;
+ case SCLK_SPI0 ... SCLK_SPI2:
+ rate = rk3368_spi_get_clk(priv->cru, clk->id);
+ break;
+#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)
+ case HCLK_SDMMC:
+ case HCLK_EMMC:
+ rate = rk3368_mmc_get_clk(priv->cru, clk->id);
+ break;
+#endif
+ default:
+ return -ENOENT;
+ }
+
+ return rate;
+}
+
static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
{
__maybe_unused struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
@@ -358,6 +435,9 @@ static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
debug("%s id:%ld rate:%ld\n", __func__, clk->id, rate);
switch (clk->id) {
+ case SCLK_SPI0 ... SCLK_SPI2:
+ ret = rk3368_spi_set_clk(priv->cru, clk->id, rate);
+ break;
#if IS_ENABLED(CONFIG_TPL_BUILD)
case CLK_DDR:
ret = rk3368_ddr_set_clk(priv->cru, rate);
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 48/66] net: gmac_rockchip: Add support for the RK3368 GMAC
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (46 preceding siblings ...)
2017-07-28 19:22 ` [U-Boot] [PATCH v3 47/66] rockchip: clk: rk3368: add support for configuring the SPI clocks Philipp Tomsich
@ 2017-07-28 19:22 ` Philipp Tomsich
2017-08-01 9:49 ` Simon Glass
2017-07-28 19:22 ` [U-Boot] [PATCH v3 49/66] rockchip: Makefile: streamline SPL/TPL configuration Philipp Tomsich
` (17 subsequent siblings)
65 siblings, 1 reply; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:22 UTC (permalink / raw)
To: u-boot
The GMAC in the RK3368 once again is identical to the incarnation in
the RK3288 and the RK3399, except for where some of the configuration
and control registers are located in the GRF.
This adds the RK3368-specific logic necessary to reuse this driver.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
---
Changes in v3: None
Changes in v2:
- moves the bit-definitions (for GRF registers) specific to the GMAC
into the GMAC driver: these include interface speed selection and
configuring the RGMII output mode
arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 1 +
drivers/net/gmac_rockchip.c | 78 +++++++++++++++++++++++++
2 files changed, 79 insertions(+)
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
index ec42d7a..1f84ff9 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
@@ -129,4 +129,5 @@ enum {
MCU_CODE_BASE_BIT31_BIT28_SHIFT = 0,
MCU_CODE_BASE_BIT31_BIT28_MASK = GENMASK(3, 0),
};
+
#endif
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index c9f9e83..586ccbf 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -16,6 +16,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/hardware.h>
#include <asm/arch/grf_rk3288.h>
+#include <asm/arch/grf_rk3368.h>
#include <asm/arch/grf_rk3399.h>
#include <dm/pinctrl.h>
#include <dt-bindings/clock/rk3288-cru.h>
@@ -83,6 +84,38 @@ static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
return 0;
}
+static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+{
+ struct rk3368_grf *grf;
+ int clk;
+ enum {
+ RK3368_GMAC_CLK_SEL_2_5M = 2 << 4,
+ RK3368_GMAC_CLK_SEL_25M = 3 << 4,
+ RK3368_GMAC_CLK_SEL_125M = 0 << 4,
+ RK3368_GMAC_CLK_SEL_MASK = GENMASK(5, 4),
+ };
+
+ switch (priv->phydev->speed) {
+ case 10:
+ clk = RK3368_GMAC_CLK_SEL_2_5M;
+ break;
+ case 100:
+ clk = RK3368_GMAC_CLK_SEL_25M;
+ break;
+ case 1000:
+ clk = RK3368_GMAC_CLK_SEL_125M;
+ break;
+ default:
+ debug("Unknown phy speed: %d\n", priv->phydev->speed);
+ return -EINVAL;
+ }
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk);
+
+ return 0;
+}
+
static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv)
{
struct rk3399_grf_regs *grf;
@@ -129,6 +162,44 @@ static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
}
+static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+{
+ struct rk3368_grf *grf;
+ enum {
+ RK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9,
+ RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9),
+ RK3368_RMII_MODE_MASK = BIT(6),
+ RK3368_RMII_MODE = BIT(6),
+ };
+ enum {
+ RK3368_RXCLK_DLY_ENA_GMAC_MASK = BIT(15),
+ RK3368_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
+ RK3368_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15),
+ RK3368_TXCLK_DLY_ENA_GMAC_MASK = BIT(7),
+ RK3368_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
+ RK3368_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7),
+ RK3368_CLK_RX_DL_CFG_GMAC_SHIFT = 8,
+ RK3368_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8),
+ RK3368_CLK_TX_DL_CFG_GMAC_SHIFT = 0,
+ RK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
+ };
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(&grf->soc_con15,
+ RK3368_RMII_MODE_MASK | RK3368_GMAC_PHY_INTF_SEL_MASK,
+ RK3368_GMAC_PHY_INTF_SEL_RGMII);
+
+ rk_clrsetreg(&grf->soc_con16,
+ RK3368_RXCLK_DLY_ENA_GMAC_MASK |
+ RK3368_TXCLK_DLY_ENA_GMAC_MASK |
+ RK3368_CLK_RX_DL_CFG_GMAC_MASK |
+ RK3368_CLK_TX_DL_CFG_GMAC_MASK,
+ RK3368_RXCLK_DLY_ENA_GMAC_ENABLE |
+ RK3368_TXCLK_DLY_ENA_GMAC_ENABLE |
+ pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT |
+ pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT);
+}
+
static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
{
struct rk3399_grf_regs *grf;
@@ -208,6 +279,11 @@ const struct rk_gmac_ops rk3288_gmac_ops = {
.set_to_rgmii = rk3288_gmac_set_to_rgmii,
};
+const struct rk_gmac_ops rk3368_gmac_ops = {
+ .fix_mac_speed = rk3368_gmac_fix_mac_speed,
+ .set_to_rgmii = rk3368_gmac_set_to_rgmii,
+};
+
const struct rk_gmac_ops rk3399_gmac_ops = {
.fix_mac_speed = rk3399_gmac_fix_mac_speed,
.set_to_rgmii = rk3399_gmac_set_to_rgmii,
@@ -216,6 +292,8 @@ const struct rk_gmac_ops rk3399_gmac_ops = {
static const struct udevice_id rockchip_gmac_ids[] = {
{ .compatible = "rockchip,rk3288-gmac",
.data = (ulong)&rk3288_gmac_ops },
+ { .compatible = "rockchip,rk3368-gmac",
+ .data = (ulong)&rk3368_gmac_ops },
{ .compatible = "rockchip,rk3399-gmac",
.data = (ulong)&rk3399_gmac_ops },
{ }
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 48/66] net: gmac_rockchip: Add support for the RK3368 GMAC
2017-07-28 19:22 ` [U-Boot] [PATCH v3 48/66] net: gmac_rockchip: Add support for the RK3368 GMAC Philipp Tomsich
@ 2017-08-01 9:49 ` Simon Glass
2017-08-01 9:57 ` Dr. Philipp Tomsich
0 siblings, 1 reply; 95+ messages in thread
From: Simon Glass @ 2017-08-01 9:49 UTC (permalink / raw)
To: u-boot
Hi Philipp,
On 28 July 2017 at 13:22, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> The GMAC in the RK3368 once again is identical to the incarnation in
> the RK3288 and the RK3399, except for where some of the configuration
> and control registers are located in the GRF.
>
> This adds the RK3368-specific logic necessary to reuse this driver.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>
> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
> ---
>
> Changes in v3: None
> Changes in v2:
> - moves the bit-definitions (for GRF registers) specific to the GMAC
> into the GMAC driver: these include interface speed selection and
> configuring the RGMII output mode
>
> arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 1 +
> drivers/net/gmac_rockchip.c | 78 +++++++++++++++++++++++++
> 2 files changed, 79 insertions(+)
>
Reviewed-by: Simon Glass <sjg@chromium.org>
I still think we should look at splitting these out into (e.g.) ioctl
operations on syscon.
^ permalink raw reply [flat|nested] 95+ messages in thread
* [U-Boot] [PATCH v3 48/66] net: gmac_rockchip: Add support for the RK3368 GMAC
2017-08-01 9:49 ` Simon Glass
@ 2017-08-01 9:57 ` Dr. Philipp Tomsich
0 siblings, 0 replies; 95+ messages in thread
From: Dr. Philipp Tomsich @ 2017-08-01 9:57 UTC (permalink / raw)
To: u-boot
Simon,
> On 01 Aug 2017, at 11:49, Simon Glass <sjg@chromium.org> wrote:
>
> Hi Philipp,
>
> On 28 July 2017 at 13:22, Philipp Tomsich
> <philipp.tomsich@theobroma-systems.com> wrote:
>> The GMAC in the RK3368 once again is identical to the incarnation in
>> the RK3288 and the RK3399, except for where some of the configuration
>> and control registers are located in the GRF.
>>
>> This adds the RK3368-specific logic necessary to reuse this driver.
>>
>> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>>
>> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
>> ---
>>
>> Changes in v3: None
>> Changes in v2:
>> - moves the bit-definitions (for GRF registers) specific to the GMAC
>> into the GMAC driver: these include interface speed selection and
>> configuring the RGMII output mode
>>
>> arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 1 +
>> drivers/net/gmac_rockchip.c | 78 +++++++++++++++++++++++++
>> 2 files changed, 79 insertions(+)
>>
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
>
> I still think we should look at splitting these out into (e.g.) ioctl
> operations on syscon.
I still agree with you and plan to look into this for the next cycle.
Thanks,
Philipp.
^ permalink raw reply [flat|nested] 95+ messages in thread
* [U-Boot] [PATCH v3 49/66] rockchip: Makefile: streamline SPL/TPL configuration
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (47 preceding siblings ...)
2017-07-28 19:22 ` [U-Boot] [PATCH v3 48/66] net: gmac_rockchip: Add support for the RK3368 GMAC Philipp Tomsich
@ 2017-07-28 19:22 ` Philipp Tomsich
2017-07-28 19:22 ` [U-Boot] [PATCH v3 50/66] rockchip: rk3368: add DRAM controller driver with DRAM initialisation Philipp Tomsich
` (16 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:22 UTC (permalink / raw)
To: u-boot
Handling TPL and SPL in the Makefile for mach-rockchip was based on
nested if checks and/or if-else-if paths. This can be simplified and
made more readable by using $(SPL_TPL_) and by introducing
intermediate variables for the aggregation of SPL and TPL features.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
Changes in v3: None
Changes in v2: None
arch/arm/mach-rockchip/Makefile | 46 +++++++++++++++++++++++++----------------
1 file changed, 28 insertions(+), 18 deletions(-)
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 8a3cb9f..633c91e 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -4,37 +4,47 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
-obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o
+# We don't want the bootrom-helper present in a full U-Boot build, as
+# this may have entered from ATF with the stack-pointer pointing to
+# inaccessible/protected memory (and the bootrom-helper assumes that
+# the stack-pointer is valid before switching to the U-Boot stack).
+obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o save_boot_param.o
+obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o save_boot_param.o
+
+obj-tpl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-tpl.o
+
+obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
+obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o
+obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o
+obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o
+obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o
+obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o
-ifdef CONFIG_TPL_BUILD
-obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-tpl.o
-obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += save_boot_param.o
-else ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
-obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o
-obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o
-obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o
-obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o
-obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += save_boot_param.o
-else
+ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o
obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board.o
obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o
obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o
endif
+
+obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o
+
ifndef CONFIG_ARM64
obj-y += rk_timer.o
endif
-obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
-
-ifndef CONFIG_TPL_BUILD
-obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/
-endif
+obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
+obj-tpl-$(CONFIG_ROCKCHIP_RK3188) += rk3188/
obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x/
obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/
obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108/
+
+# Clear out SPL objects, in case this is a TPL build
+obj-spl-$(CONFIG_TPL_BUILD) =
+
+# Now add SPL/TPL objects back into the main build
+obj-$(CONFIG_SPL_BUILD) += $(obj-spl-y)
+obj-$(CONFIG_TPL_BUILD) += $(obj-tpl-y)
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 50/66] rockchip: rk3368: add DRAM controller driver with DRAM initialisation
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (48 preceding siblings ...)
2017-07-28 19:22 ` [U-Boot] [PATCH v3 49/66] rockchip: Makefile: streamline SPL/TPL configuration Philipp Tomsich
@ 2017-07-28 19:22 ` Philipp Tomsich
2017-08-01 1:30 ` Andy Yan
2017-08-02 10:06 ` Andy Yan
2017-07-28 19:22 ` [U-Boot] [PATCH v3 51/66] rockchip: rk3368: dts: add DMC node in rk3368.dtsi Philipp Tomsich
` (15 subsequent siblings)
65 siblings, 2 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:22 UTC (permalink / raw)
To: u-boot
This adds a DRAM controller driver for the RK3368 and places it in
drivers/ram/rockchip (where the other DM-enabled DRAM controller
drivers for rockchip devices should also be moved eventually).
At this stage, only the following feature-set is supported:
- DDR3
- 32-bit configuration (i.e. fully populated)
- dual-rank (i.e. no auto-detection of ranks)
- DDR3-1600K speed-bin
This driver expects to run from a TPL stage that will later return to
the RK3368 BROM. It communicates with later stages through the
os_reg2 in the pmugrf (i.e. using the same mechanism as Rockchip's DDR
init code).
Unlike other DMC drivers for RK32xx and RK33xx parts, the required
timings are calculated within the driver based on a target frequency
and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this
time).
The RK3368 also has the DDRC0_CON0 (DDR ch. 0, control-register 0)
register for controlling the operation of its (single-channel) DRAM
controller in the GRF block. This provides for selecting DDR3, mobile
DDR modes, and control low-power operation.
As part of this change, DDRC0_CON0 is also added to the GRF structure
definition (at offset 0x600).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
Changes in v3:
- correctly states the location of the driver in the commit message
Changes in v2: None
arch/arm/include/asm/arch-rockchip/ddr_rk3368.h | 187 ++++
arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 3 +
arch/arm/mach-rockchip/rk3368/Makefile | 1 -
arch/arm/mach-rockchip/rk3368/sdram_rk3368.c | 60 --
.../clock/rockchip,rk3368-dmc.txt | 67 ++
drivers/ram/Makefile | 2 +
drivers/ram/rockchip/Makefile | 7 +
drivers/ram/rockchip/dmc-rk3368.c | 990 +++++++++++++++++++++
include/dt-bindings/memory/rk3368-dmc.h | 30 +
9 files changed, 1286 insertions(+), 61 deletions(-)
create mode 100644 arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
delete mode 100644 arch/arm/mach-rockchip/rk3368/sdram_rk3368.c
create mode 100644 doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt
create mode 100644 drivers/ram/rockchip/Makefile
create mode 100644 drivers/ram/rockchip/dmc-rk3368.c
create mode 100644 include/dt-bindings/memory/rk3368-dmc.h
diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h b/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
new file mode 100644
index 0000000..4e2b233
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
@@ -0,0 +1,187 @@
+/*
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __ASM_ARCH_DDR_RK3368_H__
+#define __ASM_ARCH_DDR_RK3368_H__
+
+/*
+ * The RK3368 DDR PCTL differs from the incarnation in the RK3288 only
+ * in a few details. Most notably, it has an additional field to track
+ * tREFI in controller cycles (i.e. trefi_mem_ddr3).
+ */
+struct rk3368_ddr_pctl {
+ u32 scfg;
+ u32 sctl;
+ u32 stat;
+ u32 intrstat;
+ u32 reserved0[12];
+ u32 mcmd;
+ u32 powctl;
+ u32 powstat;
+ u32 cmdtstat;
+ u32 cmdtstaten;
+ u32 reserved1[3];
+ u32 mrrcfg0;
+ u32 mrrstat0;
+ u32 mrrstat1;
+ u32 reserved2[4];
+ u32 mcfg1;
+ u32 mcfg;
+ u32 ppcfg;
+ u32 mstat;
+ u32 lpddr2zqcfg;
+ u32 reserved3;
+ u32 dtupdes;
+ u32 dtuna;
+ u32 dtune;
+ u32 dtuprd0;
+ u32 dtuprd1;
+ u32 dtuprd2;
+ u32 dtuprd3;
+ u32 dtuawdt;
+ u32 reserved4[3];
+ u32 togcnt1u;
+ u32 tinit;
+ u32 trsth;
+ u32 togcnt100n;
+ u32 trefi;
+ u32 tmrd;
+ u32 trfc;
+ u32 trp;
+ u32 trtw;
+ u32 tal;
+ u32 tcl;
+ u32 tcwl;
+ u32 tras;
+ u32 trc;
+ u32 trcd;
+ u32 trrd;
+ u32 trtp;
+ u32 twr;
+ u32 twtr;
+ u32 texsr;
+ u32 txp;
+ u32 txpdll;
+ u32 tzqcs;
+ u32 tzqcsi;
+ u32 tdqs;
+ u32 tcksre;
+ u32 tcksrx;
+ u32 tcke;
+ u32 tmod;
+ u32 trstl;
+ u32 tzqcl;
+ u32 tmrr;
+ u32 tckesr;
+ u32 tdpd;
+ u32 trefi_mem_ddr3;
+ u32 reserved5[45];
+ u32 dtuwactl;
+ u32 dturactl;
+ u32 dtucfg;
+ u32 dtuectl;
+ u32 dtuwd0;
+ u32 dtuwd1;
+ u32 dtuwd2;
+ u32 dtuwd3;
+ u32 dtuwdm;
+ u32 dturd0;
+ u32 dturd1;
+ u32 dturd2;
+ u32 dturd3;
+ u32 dtulfsrwd;
+ u32 dtulfsrrd;
+ u32 dtueaf;
+ u32 dfitctrldelay;
+ u32 dfiodtcfg;
+ u32 dfiodtcfg1;
+ u32 dfiodtrankmap;
+ u32 dfitphywrdata;
+ u32 dfitphywrlat;
+ u32 reserved7[2];
+ u32 dfitrddataen;
+ u32 dfitphyrdlat;
+ u32 reserved8[2];
+ u32 dfitphyupdtype0;
+ u32 dfitphyupdtype1;
+ u32 dfitphyupdtype2;
+ u32 dfitphyupdtype3;
+ u32 dfitctrlupdmin;
+ u32 dfitctrlupdmax;
+ u32 dfitctrlupddly;
+ u32 reserved9;
+ u32 dfiupdcfg;
+ u32 dfitrefmski;
+ u32 dfitctrlupdi;
+ u32 reserved10[4];
+ u32 dfitrcfg0;
+ u32 dfitrstat0;
+ u32 dfitrwrlvlen;
+ u32 dfitrrdlvlen;
+ u32 dfitrrdlvlgateen;
+ u32 dfiststat0;
+ u32 dfistcfg0;
+ u32 dfistcfg1;
+ u32 reserved11;
+ u32 dfitdramclken;
+ u32 dfitdramclkdis;
+ u32 dfistcfg2;
+ u32 dfistparclr;
+ u32 dfistparlog;
+ u32 reserved12[3];
+ u32 dfilpcfg0;
+ u32 reserved13[3];
+ u32 dfitrwrlvlresp0;
+ u32 dfitrwrlvlresp1;
+ u32 dfitrwrlvlresp2;
+ u32 dfitrrdlvlresp0;
+ u32 dfitrrdlvlresp1;
+ u32 dfitrrdlvlresp2;
+ u32 dfitrwrlvldelay0;
+ u32 dfitrwrlvldelay1;
+ u32 dfitrwrlvldelay2;
+ u32 dfitrrdlvldelay0;
+ u32 dfitrrdlvldelay1;
+ u32 dfitrrdlvldelay2;
+ u32 dfitrrdlvlgatedelay0;
+ u32 dfitrrdlvlgatedelay1;
+ u32 dfitrrdlvlgatedelay2;
+ u32 dfitrcmd;
+ u32 reserved14[46];
+ u32 ipvr;
+ u32 iptr;
+};
+check_member(rk3368_ddr_pctl, iptr, 0x03fc);
+
+struct rk3368_ddrphy {
+ u32 reg[0x100];
+};
+check_member(rk3368_ddrphy, reg[0xff], 0x03fc);
+
+struct rk3368_msch {
+ u32 coreid;
+ u32 revisionid;
+ u32 ddrconf;
+ u32 ddrtiming;
+ u32 ddrmode;
+ u32 readlatency;
+ u32 reserved1[8];
+ u32 activate;
+ u32 devtodev;
+};
+check_member(rk3368_msch, devtodev, 0x003c);
+
+/* GRF_SOC_CON0 */
+enum {
+ NOC_RSP_ERR_STALL = BIT(9),
+ MOBILE_DDR_SEL = BIT(4),
+ DDR0_16BIT_EN = BIT(3),
+ MSCH0_MAINDDR3_DDR3 = BIT(2),
+ MSCH0_MAINPARTIALPOP = BIT(1),
+ UPCTL_C_ACTIVE = BIT(0),
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
index 1f84ff9..6b6651a 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
@@ -76,8 +76,11 @@ struct rk3368_grf {
u32 soc_con15;
u32 soc_con16;
u32 soc_con17;
+ u32 reserved5[0x6e];
+ u32 ddrc0_con0;
};
check_member(rk3368_grf, soc_con17, 0x444);
+check_member(rk3368_grf, ddrc0_con0, 0x600);
struct rk3368_pmu_grf {
u32 gpio0a_iomux;
diff --git a/arch/arm/mach-rockchip/rk3368/Makefile b/arch/arm/mach-rockchip/rk3368/Makefile
index 0390716..46798c2 100644
--- a/arch/arm/mach-rockchip/rk3368/Makefile
+++ b/arch/arm/mach-rockchip/rk3368/Makefile
@@ -5,5 +5,4 @@
#
obj-y += clk_rk3368.o
obj-y += rk3368.o
-obj-y += sdram_rk3368.o
obj-y += syscon_rk3368.o
diff --git a/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c b/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c
deleted file mode 100644
index d0d0900..0000000
--- a/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd.
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#include <common.h>
-#include <dm.h>
-#include <ram.h>
-#include <syscon.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/grf_rk3368.h>
-#include <asm/arch/sdram_common.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-struct dram_info {
- struct ram_info info;
- struct rk3368_pmu_grf *pmugrf;
-};
-
-static int rk3368_dmc_probe(struct udevice *dev)
-{
- struct dram_info *priv = dev_get_priv(dev);
-
- priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
- debug("%s: grf=%p\n", __func__, priv->pmugrf);
- priv->info.base = CONFIG_SYS_SDRAM_BASE;
- priv->info.size = rockchip_sdram_size(
- (phys_addr_t)&priv->pmugrf->os_reg[2]);
-
- return 0;
-}
-
-static int rk3368_dmc_get_info(struct udevice *dev, struct ram_info *info)
-{
- struct dram_info *priv = dev_get_priv(dev);
-
- *info = priv->info;
-
- return 0;
-}
-
-static struct ram_ops rk3368_dmc_ops = {
- .get_info = rk3368_dmc_get_info,
-};
-
-
-static const struct udevice_id rk3368_dmc_ids[] = {
- { .compatible = "rockchip,rk3368-dmc" },
- { }
-};
-
-U_BOOT_DRIVER(dmc_rk3368) = {
- .name = "rockchip_rk3368_dmc",
- .id = UCLASS_RAM,
- .of_match = rk3368_dmc_ids,
- .ops = &rk3368_dmc_ops,
- .probe = rk3368_dmc_probe,
- .priv_auto_alloc_size = sizeof(struct dram_info),
-};
diff --git a/doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt b/doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt
new file mode 100644
index 0000000..8e7357d
--- /dev/null
+++ b/doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt
@@ -0,0 +1,67 @@
+RK3368 dynamic memory controller driver
+=======================================
+
+The RK3368 DMC (dynamic memory controller) driver supports setup/initialisation
+during TPL using configuration data from the DTS (i.e. OF_PLATDATA), based on
+the following key configuration data:
+ (a) a target-frequency (i.e. operating point) for the memory operation
+ (b) a speed-bin (as defined in JESD-79) for the DDR3 used in hardware
+ (c) a memory-schedule (i.e. mapping from physical addresses to the address
+ pins of the memory bus)
+
+Required properties
+-------------------
+
+- compatible: "rockchip,rk3368-dmc"
+- reg
+ protocol controller (PCTL) address and PHY controller (DDRPHY) address
+- rockchip,ddr-speed-bin
+ the DDR3 device's speed-bin (as specified according to JESD-79)
+ DDR3_800D (5-5-5)
+ DDR3_800E (6-6-6)
+ DDR3_1066E (6-6-6)
+ DDR3_1066F (7-7-7)
+ DDR3_1066G (8-8-8)
+ DDR3_1333F (7-7-7)
+ DDR3_1333G (8-8-8)
+ DDR3_1333H (9-9-9)
+ DDR3_1333J (10-10-10)
+ DDR3_1600G (8-8-8)
+ DDR3_1600H (9-9-9)
+ DDR3_1600J (10-10-10)
+ DDR3_1600K (11-11-11)
+ DDR3_1866J (10-10-10)
+ DDR3_1866K (11-11-11)
+ DDR3_1866L (12-12-12)
+ DDR3_1866M (13-13-13)
+ DDR3_2133K (11-11-11)
+ DDR3_2133L (12-12-12)
+ DDR3_2133M (13-13-13)
+ DDR3_2133N (14-14-14)
+- rockchip,ddr-frequency:
+ target DDR clock frequency in Hz (not all frequencies may be supported,
+ as there's some cooperation from the clock-driver required)
+- rockchip,memory-schedule:
+ controls the decoding of physical addresses to DRAM addressing (i.e. how
+ the physical address maps onto the address pins/chip-select of the device)
+ DMC_MSCH_CBDR: column -> bank -> device -> row
+ DMC_MSCH_CBRD: column -> band -> row -> device
+ DMC_MSCH_CRBD: column -> row -> band -> device
+
+Example (for DDR3-1600K and 800MHz)
+-----------------------------------
+
+ #include <dt-bindings/memory/rk3368-dmc.h>
+
+ dmc: dmc at ff610000 {
+ u-boot,dm-pre-reloc;
+ compatible = "rockchip,rk3368-dmc";
+ reg = <0 0xff610000 0 0x400
+ 0 0xff620000 0 0x400>;
+ };
+
+ &dmc {
+ rockchip,ddr-speed-bin = <DDR3_1600K>;
+ rockchip,ddr-frequency = <800000000>;
+ rockchip,memory-schedule = <DMC_MSCH_CBRD>;
+ };
diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
index c409c48..51ae6be 100644
--- a/drivers/ram/Makefile
+++ b/drivers/ram/Makefile
@@ -8,3 +8,5 @@ obj-$(CONFIG_RAM) += ram-uclass.o
obj-$(CONFIG_SANDBOX) += sandbox_ram.o
obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o
obj-$(CONFIG_ARCH_BMIPS) += bmips_ram.o
+
+obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile
new file mode 100644
index 0000000..b09d03c
--- /dev/null
+++ b/drivers/ram/rockchip/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_ROCKCHIP_RK3368) = dmc-rk3368.o
diff --git a/drivers/ram/rockchip/dmc-rk3368.c b/drivers/ram/rockchip/dmc-rk3368.c
new file mode 100644
index 0000000..fea96a5
--- /dev/null
+++ b/drivers/ram/rockchip/dmc-rk3368.c
@@ -0,0 +1,990 @@
+/*
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <dt-bindings/memory/rk3368-dmc.h>
+#include <dt-structs.h>
+#include <ram.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3368.h>
+#include <asm/arch/grf_rk3368.h>
+#include <asm/arch/ddr_rk3368.h>
+#include <asm/arch/sdram.h>
+#include <asm/arch/sdram_common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct dram_info {
+ struct ram_info info;
+ struct clk ddr_clk;
+ struct rk3368_cru *cru;
+ struct rk3368_grf *grf;
+ struct rk3368_ddr_pctl *pctl;
+ struct rk3368_ddrphy *phy;
+ struct rk3368_pmu_grf *pmugrf;
+ struct rk3368_msch *msch;
+};
+
+struct rk3368_sdram_params {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct dtd_rockchip_rk3368_dmc of_plat;
+#endif
+ struct rk3288_sdram_pctl_timing pctl_timing;
+ u32 trefi_mem_ddr3;
+ struct rk3288_sdram_channel chan;
+ struct regmap *map;
+ u32 ddr_freq;
+ u32 memory_schedule;
+ u32 ddr_speed_bin;
+ u32 tfaw_mult;
+};
+
+/* PTCL bits */
+enum {
+ /* PCTL_DFISTCFG0 */
+ DFI_INIT_START = BIT(0),
+ DFI_DATA_BYTE_DISABLE_EN = BIT(2),
+
+ /* PCTL_DFISTCFG1 */
+ DFI_DRAM_CLK_SR_EN = BIT(0),
+ DFI_DRAM_CLK_DPD_EN = BIT(1),
+ ODT_LEN_BL8_W_SHIFT = 16,
+
+ /* PCTL_DFISTCFG2 */
+ DFI_PARITY_INTR_EN = BIT(0),
+ DFI_PARITY_EN = BIT(1),
+
+ /* PCTL_DFILPCFG0 */
+ TLP_RESP_TIME_SHIFT = 16,
+ LP_SR_EN = BIT(8),
+ LP_PD_EN = BIT(0),
+
+ /* PCTL_DFIODTCFG */
+ RANK0_ODT_WRITE_SEL = BIT(3),
+ RANK1_ODT_WRITE_SEL = BIT(11),
+
+ /* PCTL_SCFG */
+ HW_LOW_POWER_EN = BIT(0),
+
+ /* PCTL_MCMD */
+ START_CMD = BIT(31),
+ MCMD_RANK0 = BIT(20),
+ MCMD_RANK1 = BIT(21),
+ DESELECT_CMD = 0,
+ PREA_CMD,
+ REF_CMD,
+ MRS_CMD,
+ ZQCS_CMD,
+ ZQCL_CMD,
+ RSTL_CMD,
+ MRR_CMD = 8,
+ DPDE_CMD,
+
+ /* PCTL_POWCTL */
+ POWER_UP_START = BIT(0),
+
+ /* PCTL_POWSTAT */
+ POWER_UP_DONE = BIT(0),
+
+ /* PCTL_SCTL */
+ INIT_STATE = 0,
+ CFG_STATE,
+ GO_STATE,
+ SLEEP_STATE,
+ WAKEUP_STATE,
+
+ /* PCTL_STAT */
+ LP_TRIG_SHIFT = 4,
+ LP_TRIG_MASK = 7,
+ PCTL_STAT_MSK = 7,
+ INIT_MEM = 0,
+ CONFIG,
+ CONFIG_REQ,
+ ACCESS,
+ ACCESS_REQ,
+ LOW_POWER,
+ LOW_POWER_ENTRY_REQ,
+ LOW_POWER_EXIT_REQ,
+
+ /* PCTL_MCFG */
+ DDR2_DDR3_BL_8 = BIT(0),
+ DDR3_EN = BIT(5),
+ TFAW_TRRD_MULT4 = (0 << 18),
+ TFAW_TRRD_MULT5 = (1 << 18),
+ TFAW_TRRD_MULT6 = (2 << 18),
+};
+
+#define DDR3_MR0_WR(n) \
+ ((n <= 8) ? ((n - 4) << 9) : (((n >> 1) & 0x7) << 9))
+#define DDR3_MR0_CL(n) \
+ ((((n - 4) & 0x7) << 4) | (((n - 4) & 0x8) >> 2))
+#define DDR3_MR0_BL8 \
+ (0 << 0)
+#define DDR3_MR0_DLL_RESET \
+ (1 << 8)
+#define DDR3_MR1_RTT120OHM \
+ ((0 << 9) | (1 << 6) | (0 << 2))
+#define DDR3_MR2_TWL(n) \
+ (((n - 5) & 0x7) << 3)
+
+
+#ifdef CONFIG_TPL_BUILD
+
+static void ddr_set_noc_spr_err_stall(struct rk3368_grf *grf, bool enable)
+{
+ if (enable)
+ rk_setreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL);
+ else
+ rk_clrreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL);
+}
+
+static void ddr_set_ddr3_mode(struct rk3368_grf *grf, bool ddr3_mode)
+{
+ if (ddr3_mode)
+ rk_setreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3);
+ else
+ rk_clrreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3);
+}
+
+static void ddrphy_config(struct rk3368_ddrphy *phy,
+ u32 tcl, u32 tal, u32 tcwl)
+{
+ int i;
+
+ /* Set to DDR3 mode */
+ clrsetbits_le32(&phy->reg[1], 0x3, 0x0);
+
+ /* DDRPHY_REGB: CL, AL */
+ clrsetbits_le32(&phy->reg[0xb], 0xff, tcl << 4 | tal);
+ /* DDRPHY_REGC: CWL */
+ clrsetbits_le32(&phy->reg[0xc], 0x0f, tcwl);
+
+ /* Update drive-strength */
+ writel(0xcc, &phy->reg[0x11]);
+ writel(0xaa, &phy->reg[0x16]);
+ /*
+ * Update NRCOMP/PRCOMP for all 4 channels (for details of all
+ * affected registers refer to the documentation of DDRPHY_REG20
+ * and DDRPHY_REG21 in the RK3368 TRM.
+ */
+ for (i = 0; i < 4; ++i) {
+ writel(0xcc, &phy->reg[0x20 + i * 0x10]);
+ writel(0x44, &phy->reg[0x21 + i * 0x10]);
+ }
+
+ /* Enable write-leveling calibration bypass */
+ setbits_le32(&phy->reg[2], BIT(3));
+}
+
+static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
+{
+ int i;
+
+ for (i = 0; i < n / sizeof(u32); i++)
+ writel(*src++, dest++);
+}
+
+static void send_command(struct rk3368_ddr_pctl *pctl, u32 rank, u32 cmd)
+{
+ u32 mcmd = START_CMD | cmd | rank;
+
+ debug("%s: writing %x to MCMD\n", __func__, mcmd);
+ writel(mcmd, &pctl->mcmd);
+ while (readl(&pctl->mcmd) & START_CMD)
+ /* spin */;
+}
+
+static void send_mrs(struct rk3368_ddr_pctl *pctl,
+ u32 rank, u32 mr_num, u32 mr_data)
+{
+ u32 mcmd = START_CMD | MRS_CMD | rank | (mr_num << 17) | (mr_data << 4);
+
+ debug("%s: writing %x to MCMD\n", __func__, mcmd);
+ writel(mcmd, &pctl->mcmd);
+ while (readl(&pctl->mcmd) & START_CMD)
+ /* spin */;
+}
+
+static int memory_init(struct rk3368_ddr_pctl *pctl,
+ struct rk3368_sdram_params *params)
+{
+ u32 mr[4];
+ const ulong timeout_ms = 500;
+ ulong tmp;
+
+ /*
+ * Power up DRAM by DDR_PCTL_POWCTL[0] register of PCTL and
+ * wait power up DRAM finish with DDR_PCTL_POWSTAT[0] register
+ * of PCTL.
+ */
+ writel(POWER_UP_START, &pctl->powctl);
+
+ tmp = get_timer(0);
+ do {
+ if (get_timer(tmp) > timeout_ms) {
+ error("%s: POWER_UP_START did not complete in %ld ms\n",
+ __func__, timeout_ms);
+ return -ETIME;
+ }
+ } while (!(readl(&pctl->powstat) & POWER_UP_DONE));
+
+ /* Configure MR0 through MR3 */
+ mr[0] = DDR3_MR0_WR(params->pctl_timing.twr) |
+ DDR3_MR0_CL(params->pctl_timing.tcl) |
+ DDR3_MR0_DLL_RESET;
+ mr[1] = DDR3_MR1_RTT120OHM;
+ mr[2] = DDR3_MR2_TWL(params->pctl_timing.tcwl);
+ mr[3] = 0;
+
+ /*
+ * Also see RK3368 Technical Reference Manual:
+ * "16.6.2 Initialization (DDR3 Initialization Sequence)"
+ */
+ send_command(pctl, MCMD_RANK0 | MCMD_RANK1, DESELECT_CMD);
+ udelay(1);
+ send_command(pctl, MCMD_RANK0 | MCMD_RANK1, PREA_CMD);
+ send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 2, mr[2]);
+ send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 3, mr[3]);
+ send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 1, mr[1]);
+ send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 0, mr[0]);
+ send_command(pctl, MCMD_RANK0 | MCMD_RANK1, ZQCL_CMD);
+
+ return 0;
+}
+
+static void move_to_config_state(struct rk3368_ddr_pctl *pctl)
+{
+ /*
+ * Also see RK3368 Technical Reference Manual:
+ * "16.6.1 State transition of PCTL (Moving to Config State)"
+ */
+ u32 state = readl(&pctl->stat) & PCTL_STAT_MSK;
+
+ switch (state) {
+ case LOW_POWER:
+ writel(WAKEUP_STATE, &pctl->sctl);
+ while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
+ /* spin */;
+
+ /* fall-through */
+ case ACCESS:
+ case INIT_MEM:
+ writel(CFG_STATE, &pctl->sctl);
+ while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
+ /* spin */;
+ break;
+
+ case CONFIG:
+ return;
+
+ default:
+ break;
+ }
+}
+
+static void move_to_access_state(struct rk3368_ddr_pctl *pctl)
+{
+ /*
+ * Also see RK3368 Technical Reference Manual:
+ * "16.6.1 State transition of PCTL (Moving to Access State)"
+ */
+ u32 state = readl(&pctl->stat) & PCTL_STAT_MSK;
+
+ switch (state) {
+ case LOW_POWER:
+ if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) &
+ LP_TRIG_MASK) == 1)
+ return;
+
+ writel(WAKEUP_STATE, &pctl->sctl);
+ while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
+ /* spin */;
+
+ /* fall-through */
+ case INIT_MEM:
+ writel(CFG_STATE, &pctl->sctl);
+ while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
+ /* spin */;
+
+ /* fall-through */
+ case CONFIG:
+ writel(GO_STATE, &pctl->sctl);
+ while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG)
+ /* spin */;
+ break;
+
+ case ACCESS:
+ return;
+
+ default:
+ break;
+ }
+}
+
+static void ddrctl_reset(struct rk3368_cru *cru)
+{
+ const u32 ctl_reset = BIT(3) | BIT(2);
+ const u32 phy_reset = BIT(1) | BIT(0);
+
+ rk_setreg(&cru->softrst_con[10], ctl_reset | phy_reset);
+ udelay(1);
+ rk_clrreg(&cru->softrst_con[10], ctl_reset | phy_reset);
+}
+
+static void ddrphy_reset(struct rk3368_ddrphy *ddrphy)
+{
+ clrbits_le32(&ddrphy->reg[0], BIT(3) | BIT(2));
+ udelay(1);
+ setbits_le32(&ddrphy->reg[0], BIT(3) | BIT(2));
+}
+
+static void ddrphy_config_delays(struct rk3368_ddrphy *ddrphy, u32 freq)
+{
+ u32 dqs_dll_delay;
+
+ setbits_le32(&ddrphy->reg[0x13], BIT(4));
+ clrbits_le32(&ddrphy->reg[0x14], BIT(3));
+
+ setbits_le32(&ddrphy->reg[0x26], BIT(4));
+ clrbits_le32(&ddrphy->reg[0x27], BIT(3));
+
+ setbits_le32(&ddrphy->reg[0x36], BIT(4));
+ clrbits_le32(&ddrphy->reg[0x37], BIT(3));
+
+ setbits_le32(&ddrphy->reg[0x46], BIT(4));
+ clrbits_le32(&ddrphy->reg[0x47], BIT(3));
+
+ setbits_le32(&ddrphy->reg[0x56], BIT(4));
+ clrbits_le32(&ddrphy->reg[0x57], BIT(3));
+
+ if (freq <= 400000000)
+ setbits_le32(&ddrphy->reg[0xa4], 0x1f);
+ else
+ clrbits_le32(&ddrphy->reg[0xa4], 0x1f);
+
+ if (freq < 681000000)
+ dqs_dll_delay = 3; /* 67.5 degree delay */
+ else
+ dqs_dll_delay = 2; /* 45 degree delay */
+
+ writel(dqs_dll_delay, &ddrphy->reg[0x28]);
+ writel(dqs_dll_delay, &ddrphy->reg[0x38]);
+ writel(dqs_dll_delay, &ddrphy->reg[0x48]);
+ writel(dqs_dll_delay, &ddrphy->reg[0x58]);
+}
+
+static int dfi_cfg(struct rk3368_ddr_pctl *pctl)
+{
+ const ulong timeout_ms = 200;
+ ulong tmp;
+
+ writel(DFI_DATA_BYTE_DISABLE_EN, &pctl->dfistcfg0);
+
+ writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN,
+ &pctl->dfistcfg1);
+ writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2);
+ writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN,
+ &pctl->dfilpcfg0);
+
+ writel(1, &pctl->dfitphyupdtype0);
+
+ writel(0x1f, &pctl->dfitphyrdlat);
+ writel(0, &pctl->dfitphywrdata);
+ writel(0, &pctl->dfiupdcfg); /* phyupd and ctrlupd disabled */
+
+ setbits_le32(&pctl->dfistcfg0, DFI_INIT_START);
+
+ tmp = get_timer(0);
+ do {
+ if (get_timer(tmp) > timeout_ms) {
+ error("%s: DFI init did not complete within %ld ms\n",
+ __func__, timeout_ms);
+ return -ETIME;
+ }
+ } while ((readl(&pctl->dfiststat0) & 1) == 0);
+
+ return 0;
+}
+
+static inline u32 ps_to_tCK(const u32 ps, const ulong freq)
+{
+ const ulong MHz = 1000000;
+ return DIV_ROUND_UP(ps * freq, 1000000 * MHz);
+}
+
+static inline u32 ns_to_tCK(const u32 ns, const ulong freq)
+{
+ return ps_to_tCK(ns * 1000, freq);
+}
+
+static inline u32 tCK_to_ps(const ulong tCK, const ulong freq)
+{
+ const ulong MHz = 1000000;
+ return DIV_ROUND_UP(tCK * 1000000 * MHz, freq);
+}
+
+static int pctl_calc_timings(struct rk3368_sdram_params *params,
+ ulong freq)
+{
+ struct rk3288_sdram_pctl_timing *pctl_timing = ¶ms->pctl_timing;
+ const ulong MHz = 1000000;
+ u32 tccd;
+ u32 tfaw_as_ps;
+
+ if (params->ddr_speed_bin != DDR3_1600K) {
+ error("%s: unimplemented DDR3 speed bin %d\n",
+ __func__, params->ddr_speed_bin);
+ return -1;
+ }
+
+ /* PCTL is clocked at 1/2 the DRAM clock; err on the side of caution */
+ pctl_timing->togcnt1u = DIV_ROUND_UP(freq, 2 * MHz);
+ pctl_timing->togcnt100n = DIV_ROUND_UP(freq / 10, 2 * MHz);
+
+ pctl_timing->tinit = 200; /* 200 usec */
+ pctl_timing->trsth = 500; /* 500 usec */
+ pctl_timing->trefi = 78; /* 7.8usec = 78 * 100ns */
+ params->trefi_mem_ddr3 = ns_to_tCK(pctl_timing->trefi * 100, freq);
+
+ if (freq <= (400 * MHz)) {
+ pctl_timing->tcl = 6;
+ pctl_timing->tcwl = 10;
+ } else if (freq <= (533 * MHz)) {
+ pctl_timing->tcl = 8;
+ pctl_timing->tcwl = 6;
+ } else if (freq <= (666 * MHz)) {
+ pctl_timing->tcl = 10;
+ pctl_timing->tcwl = 7;
+ } else {
+ pctl_timing->tcl = 11;
+ pctl_timing->tcwl = 8;
+ }
+
+ pctl_timing->tmrd = 4; /* 4 tCK (all speed bins) */
+ pctl_timing->trfc = ns_to_tCK(350, freq); /* tRFC: 350 (max) @ 8GBit */
+ pctl_timing->trp = max(4u, ps_to_tCK(13750, freq));
+ /*
+ * JESD-79:
+ * READ to WRITE Command Delay = RL + tCCD / 2 + 2tCK - WL
+ */
+ tccd = 4;
+ pctl_timing->trtw = pctl_timing->tcl + tccd/2 + 2 - pctl_timing->tcwl;
+ pctl_timing->tal = 0;
+ pctl_timing->tras = ps_to_tCK(35000, freq);
+ pctl_timing->trc = ps_to_tCK(48750, freq);
+ pctl_timing->trcd = ps_to_tCK(13750, freq);
+ pctl_timing->trrd = max(4u, ps_to_tCK(7500, freq));
+ pctl_timing->trtp = max(4u, ps_to_tCK(7500, freq));
+ pctl_timing->twr = ps_to_tCK(15000, freq);
+ /* The DDR3 mode-register does only support even values for tWR > 8. */
+ if (pctl_timing->twr > 8)
+ pctl_timing->twr = (pctl_timing->twr + 1) & ~1;
+ pctl_timing->twtr = max(4u, ps_to_tCK(7500, freq));
+ pctl_timing->texsr = 512; /* tEXSR(max) is tDLLLK */
+ pctl_timing->txp = max(3u, ps_to_tCK(6000, freq));
+ pctl_timing->txpdll = max(10u, ps_to_tCK(24000, freq));
+ pctl_timing->tzqcs = max(64u, ps_to_tCK(80000, freq));
+ pctl_timing->tzqcsi = 10000; /* as used by Rockchip */
+ pctl_timing->tdqs = 1; /* fixed for DDR3 */
+ pctl_timing->tcksre = max(5u, ps_to_tCK(10000, freq));
+ pctl_timing->tcksrx = max(5u, ps_to_tCK(10000, freq));
+ pctl_timing->tcke = max(3u, ps_to_tCK(5000, freq));
+ pctl_timing->tmod = max(12u, ps_to_tCK(15000, freq));
+ pctl_timing->trstl = ns_to_tCK(100, freq);
+ pctl_timing->tzqcl = max(256u, ps_to_tCK(320000, freq)); /* tZQoper */
+ pctl_timing->tmrr = 0;
+ pctl_timing->tckesr = pctl_timing->tcke + 1; /* JESD-79: tCKE + 1tCK */
+ pctl_timing->tdpd = 0; /* RK3368 TRM: "allowed values for DDR3: 0" */
+
+
+ /*
+ * The controller can represent tFAW as 4x, 5x or 6x tRRD only.
+ * We want to use the smallest multiplier that satisfies the tFAW
+ * requirements of the given speed-bin. If necessary, we stretch out
+ * tRRD to allow us to operate on a 6x multiplier for tFAW.
+ */
+ tfaw_as_ps = 40000; /* 40ns: tFAW for DDR3-1600K, 2KB page-size */
+ if (tCK_to_ps(pctl_timing->trrd * 6, freq) < tfaw_as_ps) {
+ /* If tFAW is > 6 x tRRD, we need to stretch tRRD */
+ pctl_timing->trrd = ps_to_tCK(DIV_ROUND_UP(40000, 6), freq);
+ params->tfaw_mult = TFAW_TRRD_MULT6;
+ } else if (tCK_to_ps(pctl_timing->trrd * 5, freq) < tfaw_as_ps) {
+ params->tfaw_mult = TFAW_TRRD_MULT6;
+ } else if (tCK_to_ps(pctl_timing->trrd * 4, freq) < tfaw_as_ps) {
+ params->tfaw_mult = TFAW_TRRD_MULT5;
+ } else {
+ params->tfaw_mult = TFAW_TRRD_MULT4;
+ }
+
+ return 0;
+}
+
+static void pctl_cfg(struct rk3368_ddr_pctl *pctl,
+ struct rk3368_sdram_params *params,
+ struct rk3368_grf *grf)
+{
+ /* Configure PCTL timing registers */
+ params->pctl_timing.trefi |= BIT(31); /* see PCTL_TREFI */
+ copy_to_reg(&pctl->togcnt1u, ¶ms->pctl_timing.togcnt1u,
+ sizeof(params->pctl_timing));
+ writel(params->trefi_mem_ddr3, &pctl->trefi_mem_ddr3);
+
+ /* Set up ODT write selector and ODT write length */
+ writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL), &pctl->dfiodtcfg);
+ writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1);
+
+ /* Set up the CL/CWL-dependent timings of DFI */
+ writel((params->pctl_timing.tcl - 1) / 2 - 1, &pctl->dfitrddataen);
+ writel((params->pctl_timing.tcwl - 1) / 2 - 1, &pctl->dfitphywrlat);
+
+ /* DDR3 */
+ writel(params->tfaw_mult | DDR3_EN | DDR2_DDR3_BL_8, &pctl->mcfg);
+ writel(0x001c0004, &grf->ddrc0_con0);
+
+ setbits_le32(&pctl->scfg, HW_LOW_POWER_EN);
+}
+
+static int ddrphy_data_training(struct rk3368_ddr_pctl *pctl,
+ struct rk3368_ddrphy *ddrphy)
+{
+ const u32 trefi = readl(&pctl->trefi);
+ const ulong timeout_ms = 500;
+ ulong tmp;
+
+ /* disable auto-refresh */
+ writel(0 | BIT(31), &pctl->trefi);
+
+ clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x20);
+ clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x21);
+
+ tmp = get_timer(0);
+ do {
+ if (get_timer(tmp) > timeout_ms) {
+ error("%s: did not complete within %ld ms\n",
+ __func__, timeout_ms);
+ return -ETIME;
+ }
+ } while ((readl(&ddrphy->reg[0xff]) & 0xf) != 0xf);
+
+ send_command(pctl, MCMD_RANK0 | MCMD_RANK1, PREA_CMD);
+ clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x20);
+ /* resume auto-refresh */
+ writel(trefi | BIT(31), &pctl->trefi);
+
+ return 0;
+}
+
+static int sdram_col_row_detect(struct udevice *dev)
+{
+ struct dram_info *priv = dev_get_priv(dev);
+ struct rk3368_sdram_params *params = dev_get_platdata(dev);
+ struct rk3368_ddr_pctl *pctl = priv->pctl;
+ struct rk3368_msch *msch = priv->msch;
+ const u32 test_pattern = 0x5aa5f00f;
+ int row, col;
+ uintptr_t addr;
+
+ move_to_config_state(pctl);
+ writel(6, &msch->ddrconf);
+ move_to_access_state(pctl);
+
+ /* Detect col */
+ for (col = 11; col >= 9; col--) {
+ writel(0, CONFIG_SYS_SDRAM_BASE);
+ addr = CONFIG_SYS_SDRAM_BASE +
+ (1 << (col + params->chan.bw - 1));
+ writel(test_pattern, addr);
+ if ((readl(addr) == test_pattern) &&
+ (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+ break;
+ }
+
+ if (col == 8) {
+ error("%s: col detect error\n", __func__);
+ return -EINVAL;
+ }
+
+ move_to_config_state(pctl);
+ writel(15, &msch->ddrconf);
+ move_to_access_state(pctl);
+
+ /* Detect row*/
+ for (row = 16; row >= 12; row--) {
+ writel(0, CONFIG_SYS_SDRAM_BASE);
+ addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
+ writel(test_pattern, addr);
+ if ((readl(addr) == test_pattern) &&
+ (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+ break;
+ }
+
+ if (row == 11) {
+ error("%s: row detect error\n", __func__);
+ return -EINVAL;
+ }
+
+ /* Record results */
+ debug("%s: col %d, row %d\n", __func__, col, row);
+ params->chan.col = col;
+ params->chan.cs0_row = row;
+ params->chan.cs1_row = row;
+ params->chan.row_3_4 = 0;
+
+ return 0;
+}
+
+static int msch_niu_config(struct rk3368_msch *msch,
+ struct rk3368_sdram_params *params)
+{
+ int i;
+ const u8 cols = params->chan.col - ((params->chan.bw == 2) ? 0 : 1);
+ const u8 rows = params->chan.cs0_row;
+
+ /*
+ * The DDR address-translation table always assumes a 32bit
+ * bus and the comparison below takes care of adjusting for
+ * a 16bit bus (i.e. one column-address is consumed).
+ */
+ const struct {
+ u8 rows;
+ u8 columns;
+ u8 type;
+ } ddrconf_table[] = {
+ /*
+ * C-B-R-D patterns are first. For these we require an
+ * exact match for the columns and rows (as there's
+ * one entry per possible configuration).
+ */
+ [0] = { .rows = 13, .columns = 10, .type = DMC_MSCH_CBRD },
+ [1] = { .rows = 14, .columns = 10, .type = DMC_MSCH_CBRD },
+ [2] = { .rows = 15, .columns = 10, .type = DMC_MSCH_CBRD },
+ [3] = { .rows = 16, .columns = 10, .type = DMC_MSCH_CBRD },
+ [4] = { .rows = 14, .columns = 11, .type = DMC_MSCH_CBRD },
+ [5] = { .rows = 15, .columns = 11, .type = DMC_MSCH_CBRD },
+ [6] = { .rows = 16, .columns = 11, .type = DMC_MSCH_CBRD },
+ [7] = { .rows = 13, .columns = 9, .type = DMC_MSCH_CBRD },
+ [8] = { .rows = 14, .columns = 9, .type = DMC_MSCH_CBRD },
+ [9] = { .rows = 15, .columns = 9, .type = DMC_MSCH_CBRD },
+ [10] = { .rows = 16, .columns = 9, .type = DMC_MSCH_CBRD },
+ /*
+ * 11 through 13 are C-R-B-D patterns. These are
+ * matched for an exact number of columns and to
+ * ensure that the hardware uses at least as many rows
+ * as the pattern requires (i.e. we make sure that
+ * there's no gaps up until we hit the device/chip-select;
+ * however, these patterns can accept up to 16 rows,
+ * as the row-address continues right after the CS
+ * switching)
+ */
+ [11] = { .rows = 15, .columns = 10, .type = DMC_MSCH_CRBD },
+ [12] = { .rows = 14, .columns = 11, .type = DMC_MSCH_CRBD },
+ [13] = { .rows = 13, .columns = 10, .type = DMC_MSCH_CRBD },
+ /*
+ * 14 and 15 are catch-all variants using a C-B-D-R
+ * scheme (i.e. alternating the chip-select every time
+ * C-B overflows) and stuffing the remaining C-bits
+ * into the top. Matching needs to make sure that the
+ * number of columns is either an exact match (i.e. we
+ * can use less the the maximum number of rows) -or-
+ * that the columns exceed what is given in this table
+ * and the rows are an exact match (in which case the
+ * remaining C-bits will be stuffed onto the top after
+ * the device/chip-select switches).
+ */
+ [14] = { .rows = 16, .columns = 10, .type = DMC_MSCH_CBDR },
+ [15] = { .rows = 16, .columns = 9, .type = DMC_MSCH_CBDR },
+ };
+
+ /*
+ * For C-B-R-D, we need an exact match (i.e. both for the number of
+ * columns and rows), while for C-B-D-R, only the the number of
+ * columns needs to match.
+ */
+ for (i = 0; i < ARRAY_SIZE(ddrconf_table); i++) {
+ bool match = false;
+
+ /* If this entry if for a different matcher, then skip it */
+ if (ddrconf_table[i].type != params->memory_schedule)
+ continue;
+
+ /*
+ * Match according to the rules (exact/inexact/at-least)
+ * documented in the ddrconf_table above.
+ */
+ switch (params->memory_schedule) {
+ case DMC_MSCH_CBRD:
+ match = (ddrconf_table[i].columns == cols) &&
+ (ddrconf_table[i].rows == rows);
+ break;
+
+ case DMC_MSCH_CRBD:
+ match = (ddrconf_table[i].columns == cols) &&
+ (ddrconf_table[i].rows <= rows);
+ break;
+
+ case DMC_MSCH_CBDR:
+ match = (ddrconf_table[i].columns == cols) ||
+ ((ddrconf_table[i].columns <= cols) &&
+ (ddrconf_table[i].rows == rows));
+ break;
+
+ default:
+ break;
+ }
+
+ if (match) {
+ debug("%s: setting ddrconf 0x%x\n", __func__, i);
+ writel(i, &msch->ddrconf);
+ return 0;
+ }
+ }
+
+ error("%s: ddrconf (NIU config) not found\n", __func__);
+ return -EINVAL;
+}
+
+static void dram_all_config(struct udevice *dev)
+{
+ struct dram_info *priv = dev_get_priv(dev);
+ struct rk3368_pmu_grf *pmugrf = priv->pmugrf;
+ struct rk3368_sdram_params *params = dev_get_platdata(dev);
+ const struct rk3288_sdram_channel *info = ¶ms->chan;
+ u32 sys_reg = 0;
+ const int chan = 0;
+
+ sys_reg |= DDR3 << SYS_REG_DDRTYPE_SHIFT;
+ sys_reg |= 0 << SYS_REG_NUM_CH_SHIFT;
+
+ sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan);
+ sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan);
+ sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan);
+ sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan);
+ sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan);
+ sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan);
+ sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan);
+ sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan);
+ sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan);
+
+ writel(sys_reg, &pmugrf->os_reg[2]);
+}
+
+static int setup_sdram(struct udevice *dev)
+{
+ struct dram_info *priv = dev_get_priv(dev);
+ struct rk3368_sdram_params *params = dev_get_platdata(dev);
+
+ struct rk3368_ddr_pctl *pctl = priv->pctl;
+ struct rk3368_ddrphy *ddrphy = priv->phy;
+ struct rk3368_cru *cru = priv->cru;
+ struct rk3368_grf *grf = priv->grf;
+ struct rk3368_msch *msch = priv->msch;
+
+ int ret;
+
+ /* The input clock (i.e. DPLL) needs to be 2x the DRAM frequency */
+ ret = clk_set_rate(&priv->ddr_clk, 2 * params->ddr_freq);
+ if (ret < 0) {
+ debug("%s: could not set DDR clock: %d\n", __func__, ret);
+ return ret;
+ }
+
+ /* Update the read-latency for the RK3368 */
+ writel(0x32, &msch->readlatency);
+
+ /* Initialise the DDR PCTL and DDR PHY */
+ ddrctl_reset(cru);
+ ddrphy_reset(ddrphy);
+ ddrphy_config_delays(ddrphy, params->ddr_freq);
+ dfi_cfg(pctl);
+ /* Configure relative system information of grf_ddrc0_con0 register */
+ ddr_set_ddr3_mode(grf, true);
+ ddr_set_noc_spr_err_stall(grf, true);
+ /* Calculate timings */
+ pctl_calc_timings(params, params->ddr_freq);
+ /* Initialise the device timings in protocol controller */
+ pctl_cfg(pctl, params, grf);
+ /* Configure AL, CL ... information of PHY registers */
+ ddrphy_config(ddrphy,
+ params->pctl_timing.tcl,
+ params->pctl_timing.tal,
+ params->pctl_timing.tcwl);
+
+ /* Initialize DRAM and configure with mode-register values */
+ ret = memory_init(pctl, params);
+ if (ret)
+ goto error;
+
+ move_to_config_state(pctl);
+ /* Perform data-training */
+ ddrphy_data_training(pctl, ddrphy);
+ move_to_access_state(pctl);
+
+ /* TODO(prt): could detect rank in training... */
+ params->chan.rank = 2;
+ /* TODO(prt): bus width is not auto-detected (yet)... */
+ params->chan.bw = 2; /* 32bit wide bus */
+ params->chan.dbw = params->chan.dbw; /* 32bit wide bus */
+
+ /* DDR3 is always 8 bank */
+ params->chan.bk = 3;
+ /* Detect col and row number */
+ ret = sdram_col_row_detect(dev);
+ if (ret)
+ goto error;
+
+ /* Configure NIU DDR configuration */
+ ret = msch_niu_config(msch, params);
+ if (ret)
+ goto error;
+
+ /* set up OS_REG to communicate w/ next stage and OS */
+ dram_all_config(dev);
+
+ return 0;
+
+error:
+ printf("DRAM init failed!\n");
+ hang();
+}
+#endif
+
+static int rk3368_dmc_ofdata_to_platdata(struct udevice *dev)
+{
+ int ret = 0;
+
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct rk3368_sdram_params *plat = dev_get_platdata(dev);
+
+ ret = regmap_init_mem(dev, &plat->map);
+ if (ret)
+ return ret;
+#endif
+
+ return ret;
+}
+
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+static int conv_of_platdata(struct udevice *dev)
+{
+ struct rk3368_sdram_params *plat = dev_get_platdata(dev);
+ struct dtd_rockchip_rk3368_dmc *of_plat = &plat->of_plat;
+ int ret;
+
+ plat->ddr_freq = of_plat->rockchip_ddr_frequency;
+ plat->ddr_speed_bin = of_plat->rockchip_ddr_speed_bin;
+ plat->memory_schedule = of_plat->rockchip_memory_schedule;
+
+ ret = regmap_init_mem_platdata(dev, of_plat->reg,
+ ARRAY_SIZE(of_plat->reg) / 2,
+ &plat->map);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+#endif
+
+static int rk3368_dmc_probe(struct udevice *dev)
+{
+#ifdef CONFIG_TPL_BUILD
+ struct rk3368_sdram_params *plat = dev_get_platdata(dev);
+ struct rk3368_ddr_pctl *pctl;
+ struct rk3368_ddrphy *ddrphy;
+ struct rk3368_cru *cru;
+ struct rk3368_grf *grf;
+ struct rk3368_msch *msch;
+ int ret;
+ struct udevice *dev_clk;
+#endif
+ struct dram_info *priv = dev_get_priv(dev);
+
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ ret = conv_of_platdata(dev);
+ if (ret)
+ return ret;
+#endif
+
+ priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
+ debug("%s: pmugrf=%p\n", __func__, priv->pmugrf);
+
+#ifdef CONFIG_TPL_BUILD
+ pctl = regmap_get_range(plat->map, 0);
+ ddrphy = regmap_get_range(plat->map, 1);
+ msch = syscon_get_first_range(ROCKCHIP_SYSCON_MSCH);
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+ priv->pctl = pctl;
+ priv->phy = ddrphy;
+ priv->msch = msch;
+ priv->grf = grf;
+
+ ret = rockchip_get_clk(&dev_clk);
+ if (ret)
+ return ret;
+ priv->ddr_clk.id = CLK_DDR;
+ ret = clk_request(dev_clk, &priv->ddr_clk);
+ if (ret)
+ return ret;
+
+ cru = rockchip_get_cru();
+ priv->cru = cru;
+ if (IS_ERR(priv->cru))
+ return PTR_ERR(priv->cru);
+
+ ret = setup_sdram(dev);
+ if (ret)
+ return ret;
+#endif
+
+ priv->info.base = 0;
+ priv->info.size =
+ rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg[2]);
+
+ /*
+ * we use the 0x00000000~0xfdffffff space since 0xff000000~0xffffffff
+ * is SoC register space (i.e. reserved), and 0xfe000000~0xfeffffff is
+ * inaccessible for some IP controller.
+ */
+ priv->info.size = min(priv->info.size, (size_t)0xfe000000);
+
+ return 0;
+}
+
+static int rk3368_dmc_get_info(struct udevice *dev, struct ram_info *info)
+{
+ struct dram_info *priv = dev_get_priv(dev);
+
+ *info = priv->info;
+ return 0;
+}
+
+static struct ram_ops rk3368_dmc_ops = {
+ .get_info = rk3368_dmc_get_info,
+};
+
+
+static const struct udevice_id rk3368_dmc_ids[] = {
+ { .compatible = "rockchip,rk3368-dmc" },
+ { }
+};
+
+U_BOOT_DRIVER(dmc_rk3368) = {
+ .name = "rockchip_rk3368_dmc",
+ .id = UCLASS_RAM,
+ .of_match = rk3368_dmc_ids,
+ .ops = &rk3368_dmc_ops,
+ .probe = rk3368_dmc_probe,
+ .priv_auto_alloc_size = sizeof(struct dram_info),
+ .ofdata_to_platdata = rk3368_dmc_ofdata_to_platdata,
+ .probe = rk3368_dmc_probe,
+ .priv_auto_alloc_size = sizeof(struct dram_info),
+ .platdata_auto_alloc_size = sizeof(struct rk3368_sdram_params),
+};
diff --git a/include/dt-bindings/memory/rk3368-dmc.h b/include/dt-bindings/memory/rk3368-dmc.h
new file mode 100644
index 0000000..b06ffde
--- /dev/null
+++ b/include/dt-bindings/memory/rk3368-dmc.h
@@ -0,0 +1,30 @@
+#ifndef DT_BINDINGS_RK3368_DMC_H
+#define DT_BINDINGS_RK3368_DMC_H
+
+#define DMC_MSCH_CBDR 0x0
+#define DMC_MSCH_CBRD 0x1
+#define DMC_MSCH_CRBD 0x2
+
+#define DDR3_800D 0
+#define DDR3_800E 1
+#define DDR3_1066E 2
+#define DDR3_1066F 3
+#define DDR3_1066G 4
+#define DDR3_1333F 5
+#define DDR3_1333G 6
+#define DDR3_1333H 7
+#define DDR3_1333J 8
+#define DDR3_1600G 9
+#define DDR3_1600H 10
+#define DDR3_1600J 11
+#define DDR3_1600K 12
+#define DDR3_1866J 13
+#define DDR3_1866K 14
+#define DDR3_1866L 15
+#define DDR3_1866M 16
+#define DDR3_2133K 17
+#define DDR3_2133L 18
+#define DDR3_2133M 19
+#define DDR3_2133N 20
+
+#endif
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 50/66] rockchip: rk3368: add DRAM controller driver with DRAM initialisation
2017-07-28 19:22 ` [U-Boot] [PATCH v3 50/66] rockchip: rk3368: add DRAM controller driver with DRAM initialisation Philipp Tomsich
@ 2017-08-01 1:30 ` Andy Yan
2017-08-01 2:09 ` 汤云平
2017-08-02 10:06 ` Andy Yan
1 sibling, 1 reply; 95+ messages in thread
From: Andy Yan @ 2017-08-01 1:30 UTC (permalink / raw)
To: u-boot
add Tony from our dram team, maybe he has some ideas for this patch.
On 2017年07月29日 03:22, Philipp Tomsich wrote:
> This adds a DRAM controller driver for the RK3368 and places it in
> drivers/ram/rockchip (where the other DM-enabled DRAM controller
> drivers for rockchip devices should also be moved eventually).
>
> At this stage, only the following feature-set is supported:
> - DDR3
> - 32-bit configuration (i.e. fully populated)
> - dual-rank (i.e. no auto-detection of ranks)
> - DDR3-1600K speed-bin
>
> This driver expects to run from a TPL stage that will later return to
> the RK3368 BROM. It communicates with later stages through the
> os_reg2 in the pmugrf (i.e. using the same mechanism as Rockchip's DDR
> init code).
>
> Unlike other DMC drivers for RK32xx and RK33xx parts, the required
> timings are calculated within the driver based on a target frequency
> and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this
> time).
>
> The RK3368 also has the DDRC0_CON0 (DDR ch. 0, control-register 0)
> register for controlling the operation of its (single-channel) DRAM
> controller in the GRF block. This provides for selecting DDR3, mobile
> DDR modes, and control low-power operation.
> As part of this change, DDRC0_CON0 is also added to the GRF structure
> definition (at offset 0x600).
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v3:
> - correctly states the location of the driver in the commit message
>
> Changes in v2: None
>
> arch/arm/include/asm/arch-rockchip/ddr_rk3368.h | 187 ++++
> arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 3 +
> arch/arm/mach-rockchip/rk3368/Makefile | 1 -
> arch/arm/mach-rockchip/rk3368/sdram_rk3368.c | 60 --
> .../clock/rockchip,rk3368-dmc.txt | 67 ++
> drivers/ram/Makefile | 2 +
> drivers/ram/rockchip/Makefile | 7 +
> drivers/ram/rockchip/dmc-rk3368.c | 990 +++++++++++++++++++++
> include/dt-bindings/memory/rk3368-dmc.h | 30 +
> 9 files changed, 1286 insertions(+), 61 deletions(-)
> create mode 100644 arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
> delete mode 100644 arch/arm/mach-rockchip/rk3368/sdram_rk3368.c
> create mode 100644 doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt
> create mode 100644 drivers/ram/rockchip/Makefile
> create mode 100644 drivers/ram/rockchip/dmc-rk3368.c
> create mode 100644 include/dt-bindings/memory/rk3368-dmc.h
>
> diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h b/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
> new file mode 100644
> index 0000000..4e2b233
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
> @@ -0,0 +1,187 @@
> +/*
> + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + */
> +
> +#ifndef __ASM_ARCH_DDR_RK3368_H__
> +#define __ASM_ARCH_DDR_RK3368_H__
> +
> +/*
> + * The RK3368 DDR PCTL differs from the incarnation in the RK3288 only
> + * in a few details. Most notably, it has an additional field to track
> + * tREFI in controller cycles (i.e. trefi_mem_ddr3).
> + */
> +struct rk3368_ddr_pctl {
> + u32 scfg;
> + u32 sctl;
> + u32 stat;
> + u32 intrstat;
> + u32 reserved0[12];
> + u32 mcmd;
> + u32 powctl;
> + u32 powstat;
> + u32 cmdtstat;
> + u32 cmdtstaten;
> + u32 reserved1[3];
> + u32 mrrcfg0;
> + u32 mrrstat0;
> + u32 mrrstat1;
> + u32 reserved2[4];
> + u32 mcfg1;
> + u32 mcfg;
> + u32 ppcfg;
> + u32 mstat;
> + u32 lpddr2zqcfg;
> + u32 reserved3;
> + u32 dtupdes;
> + u32 dtuna;
> + u32 dtune;
> + u32 dtuprd0;
> + u32 dtuprd1;
> + u32 dtuprd2;
> + u32 dtuprd3;
> + u32 dtuawdt;
> + u32 reserved4[3];
> + u32 togcnt1u;
> + u32 tinit;
> + u32 trsth;
> + u32 togcnt100n;
> + u32 trefi;
> + u32 tmrd;
> + u32 trfc;
> + u32 trp;
> + u32 trtw;
> + u32 tal;
> + u32 tcl;
> + u32 tcwl;
> + u32 tras;
> + u32 trc;
> + u32 trcd;
> + u32 trrd;
> + u32 trtp;
> + u32 twr;
> + u32 twtr;
> + u32 texsr;
> + u32 txp;
> + u32 txpdll;
> + u32 tzqcs;
> + u32 tzqcsi;
> + u32 tdqs;
> + u32 tcksre;
> + u32 tcksrx;
> + u32 tcke;
> + u32 tmod;
> + u32 trstl;
> + u32 tzqcl;
> + u32 tmrr;
> + u32 tckesr;
> + u32 tdpd;
> + u32 trefi_mem_ddr3;
> + u32 reserved5[45];
> + u32 dtuwactl;
> + u32 dturactl;
> + u32 dtucfg;
> + u32 dtuectl;
> + u32 dtuwd0;
> + u32 dtuwd1;
> + u32 dtuwd2;
> + u32 dtuwd3;
> + u32 dtuwdm;
> + u32 dturd0;
> + u32 dturd1;
> + u32 dturd2;
> + u32 dturd3;
> + u32 dtulfsrwd;
> + u32 dtulfsrrd;
> + u32 dtueaf;
> + u32 dfitctrldelay;
> + u32 dfiodtcfg;
> + u32 dfiodtcfg1;
> + u32 dfiodtrankmap;
> + u32 dfitphywrdata;
> + u32 dfitphywrlat;
> + u32 reserved7[2];
> + u32 dfitrddataen;
> + u32 dfitphyrdlat;
> + u32 reserved8[2];
> + u32 dfitphyupdtype0;
> + u32 dfitphyupdtype1;
> + u32 dfitphyupdtype2;
> + u32 dfitphyupdtype3;
> + u32 dfitctrlupdmin;
> + u32 dfitctrlupdmax;
> + u32 dfitctrlupddly;
> + u32 reserved9;
> + u32 dfiupdcfg;
> + u32 dfitrefmski;
> + u32 dfitctrlupdi;
> + u32 reserved10[4];
> + u32 dfitrcfg0;
> + u32 dfitrstat0;
> + u32 dfitrwrlvlen;
> + u32 dfitrrdlvlen;
> + u32 dfitrrdlvlgateen;
> + u32 dfiststat0;
> + u32 dfistcfg0;
> + u32 dfistcfg1;
> + u32 reserved11;
> + u32 dfitdramclken;
> + u32 dfitdramclkdis;
> + u32 dfistcfg2;
> + u32 dfistparclr;
> + u32 dfistparlog;
> + u32 reserved12[3];
> + u32 dfilpcfg0;
> + u32 reserved13[3];
> + u32 dfitrwrlvlresp0;
> + u32 dfitrwrlvlresp1;
> + u32 dfitrwrlvlresp2;
> + u32 dfitrrdlvlresp0;
> + u32 dfitrrdlvlresp1;
> + u32 dfitrrdlvlresp2;
> + u32 dfitrwrlvldelay0;
> + u32 dfitrwrlvldelay1;
> + u32 dfitrwrlvldelay2;
> + u32 dfitrrdlvldelay0;
> + u32 dfitrrdlvldelay1;
> + u32 dfitrrdlvldelay2;
> + u32 dfitrrdlvlgatedelay0;
> + u32 dfitrrdlvlgatedelay1;
> + u32 dfitrrdlvlgatedelay2;
> + u32 dfitrcmd;
> + u32 reserved14[46];
> + u32 ipvr;
> + u32 iptr;
> +};
> +check_member(rk3368_ddr_pctl, iptr, 0x03fc);
> +
> +struct rk3368_ddrphy {
> + u32 reg[0x100];
> +};
> +check_member(rk3368_ddrphy, reg[0xff], 0x03fc);
> +
> +struct rk3368_msch {
> + u32 coreid;
> + u32 revisionid;
> + u32 ddrconf;
> + u32 ddrtiming;
> + u32 ddrmode;
> + u32 readlatency;
> + u32 reserved1[8];
> + u32 activate;
> + u32 devtodev;
> +};
> +check_member(rk3368_msch, devtodev, 0x003c);
> +
> +/* GRF_SOC_CON0 */
> +enum {
> + NOC_RSP_ERR_STALL = BIT(9),
> + MOBILE_DDR_SEL = BIT(4),
> + DDR0_16BIT_EN = BIT(3),
> + MSCH0_MAINDDR3_DDR3 = BIT(2),
> + MSCH0_MAINPARTIALPOP = BIT(1),
> + UPCTL_C_ACTIVE = BIT(0),
> +};
> +
> +#endif
> diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
> index 1f84ff9..6b6651a 100644
> --- a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
> +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
> @@ -76,8 +76,11 @@ struct rk3368_grf {
> u32 soc_con15;
> u32 soc_con16;
> u32 soc_con17;
> + u32 reserved5[0x6e];
> + u32 ddrc0_con0;
> };
> check_member(rk3368_grf, soc_con17, 0x444);
> +check_member(rk3368_grf, ddrc0_con0, 0x600);
>
> struct rk3368_pmu_grf {
> u32 gpio0a_iomux;
> diff --git a/arch/arm/mach-rockchip/rk3368/Makefile b/arch/arm/mach-rockchip/rk3368/Makefile
> index 0390716..46798c2 100644
> --- a/arch/arm/mach-rockchip/rk3368/Makefile
> +++ b/arch/arm/mach-rockchip/rk3368/Makefile
> @@ -5,5 +5,4 @@
> #
> obj-y += clk_rk3368.o
> obj-y += rk3368.o
> -obj-y += sdram_rk3368.o
> obj-y += syscon_rk3368.o
> diff --git a/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c b/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c
> deleted file mode 100644
> index d0d0900..0000000
> --- a/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c
> +++ /dev/null
> @@ -1,60 +0,0 @@
> -/*
> - * (C) Copyright 2016 Rockchip Electronics Co., Ltd.
> - *
> - * SPDX-License-Identifier: GPL-2.0
> - */
> -
> -#include <common.h>
> -#include <dm.h>
> -#include <ram.h>
> -#include <syscon.h>
> -#include <asm/arch/clock.h>
> -#include <asm/arch/grf_rk3368.h>
> -#include <asm/arch/sdram_common.h>
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -struct dram_info {
> - struct ram_info info;
> - struct rk3368_pmu_grf *pmugrf;
> -};
> -
> -static int rk3368_dmc_probe(struct udevice *dev)
> -{
> - struct dram_info *priv = dev_get_priv(dev);
> -
> - priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
> - debug("%s: grf=%p\n", __func__, priv->pmugrf);
> - priv->info.base = CONFIG_SYS_SDRAM_BASE;
> - priv->info.size = rockchip_sdram_size(
> - (phys_addr_t)&priv->pmugrf->os_reg[2]);
> -
> - return 0;
> -}
> -
> -static int rk3368_dmc_get_info(struct udevice *dev, struct ram_info *info)
> -{
> - struct dram_info *priv = dev_get_priv(dev);
> -
> - *info = priv->info;
> -
> - return 0;
> -}
> -
> -static struct ram_ops rk3368_dmc_ops = {
> - .get_info = rk3368_dmc_get_info,
> -};
> -
> -
> -static const struct udevice_id rk3368_dmc_ids[] = {
> - { .compatible = "rockchip,rk3368-dmc" },
> - { }
> -};
> -
> -U_BOOT_DRIVER(dmc_rk3368) = {
> - .name = "rockchip_rk3368_dmc",
> - .id = UCLASS_RAM,
> - .of_match = rk3368_dmc_ids,
> - .ops = &rk3368_dmc_ops,
> - .probe = rk3368_dmc_probe,
> - .priv_auto_alloc_size = sizeof(struct dram_info),
> -};
> diff --git a/doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt b/doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt
> new file mode 100644
> index 0000000..8e7357d
> --- /dev/null
> +++ b/doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt
> @@ -0,0 +1,67 @@
> +RK3368 dynamic memory controller driver
> +=======================================
> +
> +The RK3368 DMC (dynamic memory controller) driver supports setup/initialisation
> +during TPL using configuration data from the DTS (i.e. OF_PLATDATA), based on
> +the following key configuration data:
> + (a) a target-frequency (i.e. operating point) for the memory operation
> + (b) a speed-bin (as defined in JESD-79) for the DDR3 used in hardware
> + (c) a memory-schedule (i.e. mapping from physical addresses to the address
> + pins of the memory bus)
> +
> +Required properties
> +-------------------
> +
> +- compatible: "rockchip,rk3368-dmc"
> +- reg
> + protocol controller (PCTL) address and PHY controller (DDRPHY) address
> +- rockchip,ddr-speed-bin
> + the DDR3 device's speed-bin (as specified according to JESD-79)
> + DDR3_800D (5-5-5)
> + DDR3_800E (6-6-6)
> + DDR3_1066E (6-6-6)
> + DDR3_1066F (7-7-7)
> + DDR3_1066G (8-8-8)
> + DDR3_1333F (7-7-7)
> + DDR3_1333G (8-8-8)
> + DDR3_1333H (9-9-9)
> + DDR3_1333J (10-10-10)
> + DDR3_1600G (8-8-8)
> + DDR3_1600H (9-9-9)
> + DDR3_1600J (10-10-10)
> + DDR3_1600K (11-11-11)
> + DDR3_1866J (10-10-10)
> + DDR3_1866K (11-11-11)
> + DDR3_1866L (12-12-12)
> + DDR3_1866M (13-13-13)
> + DDR3_2133K (11-11-11)
> + DDR3_2133L (12-12-12)
> + DDR3_2133M (13-13-13)
> + DDR3_2133N (14-14-14)
> +- rockchip,ddr-frequency:
> + target DDR clock frequency in Hz (not all frequencies may be supported,
> + as there's some cooperation from the clock-driver required)
> +- rockchip,memory-schedule:
> + controls the decoding of physical addresses to DRAM addressing (i.e. how
> + the physical address maps onto the address pins/chip-select of the device)
> + DMC_MSCH_CBDR: column -> bank -> device -> row
> + DMC_MSCH_CBRD: column -> band -> row -> device
> + DMC_MSCH_CRBD: column -> row -> band -> device
> +
> +Example (for DDR3-1600K and 800MHz)
> +-----------------------------------
> +
> + #include <dt-bindings/memory/rk3368-dmc.h>
> +
> + dmc: dmc at ff610000 {
> + u-boot,dm-pre-reloc;
> + compatible = "rockchip,rk3368-dmc";
> + reg = <0 0xff610000 0 0x400
> + 0 0xff620000 0 0x400>;
> + };
> +
> + &dmc {
> + rockchip,ddr-speed-bin = <DDR3_1600K>;
> + rockchip,ddr-frequency = <800000000>;
> + rockchip,memory-schedule = <DMC_MSCH_CBRD>;
> + };
> diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
> index c409c48..51ae6be 100644
> --- a/drivers/ram/Makefile
> +++ b/drivers/ram/Makefile
> @@ -8,3 +8,5 @@ obj-$(CONFIG_RAM) += ram-uclass.o
> obj-$(CONFIG_SANDBOX) += sandbox_ram.o
> obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o
> obj-$(CONFIG_ARCH_BMIPS) += bmips_ram.o
> +
> +obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
> diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile
> new file mode 100644
> index 0000000..b09d03c
> --- /dev/null
> +++ b/drivers/ram/rockchip/Makefile
> @@ -0,0 +1,7 @@
> +#
> +# Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +
> +obj-$(CONFIG_ROCKCHIP_RK3368) = dmc-rk3368.o
> diff --git a/drivers/ram/rockchip/dmc-rk3368.c b/drivers/ram/rockchip/dmc-rk3368.c
> new file mode 100644
> index 0000000..fea96a5
> --- /dev/null
> +++ b/drivers/ram/rockchip/dmc-rk3368.c
> @@ -0,0 +1,990 @@
> +/*
> + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + */
> +
> +#include <common.h>
> +#include <clk.h>
> +#include <dm.h>
> +#include <dt-bindings/memory/rk3368-dmc.h>
> +#include <dt-structs.h>
> +#include <ram.h>
> +#include <regmap.h>
> +#include <syscon.h>
> +#include <asm/io.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/cru_rk3368.h>
> +#include <asm/arch/grf_rk3368.h>
> +#include <asm/arch/ddr_rk3368.h>
> +#include <asm/arch/sdram.h>
> +#include <asm/arch/sdram_common.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct dram_info {
> + struct ram_info info;
> + struct clk ddr_clk;
> + struct rk3368_cru *cru;
> + struct rk3368_grf *grf;
> + struct rk3368_ddr_pctl *pctl;
> + struct rk3368_ddrphy *phy;
> + struct rk3368_pmu_grf *pmugrf;
> + struct rk3368_msch *msch;
> +};
> +
> +struct rk3368_sdram_params {
> +#if CONFIG_IS_ENABLED(OF_PLATDATA)
> + struct dtd_rockchip_rk3368_dmc of_plat;
> +#endif
> + struct rk3288_sdram_pctl_timing pctl_timing;
> + u32 trefi_mem_ddr3;
> + struct rk3288_sdram_channel chan;
> + struct regmap *map;
> + u32 ddr_freq;
> + u32 memory_schedule;
> + u32 ddr_speed_bin;
> + u32 tfaw_mult;
> +};
> +
> +/* PTCL bits */
> +enum {
> + /* PCTL_DFISTCFG0 */
> + DFI_INIT_START = BIT(0),
> + DFI_DATA_BYTE_DISABLE_EN = BIT(2),
> +
> + /* PCTL_DFISTCFG1 */
> + DFI_DRAM_CLK_SR_EN = BIT(0),
> + DFI_DRAM_CLK_DPD_EN = BIT(1),
> + ODT_LEN_BL8_W_SHIFT = 16,
> +
> + /* PCTL_DFISTCFG2 */
> + DFI_PARITY_INTR_EN = BIT(0),
> + DFI_PARITY_EN = BIT(1),
> +
> + /* PCTL_DFILPCFG0 */
> + TLP_RESP_TIME_SHIFT = 16,
> + LP_SR_EN = BIT(8),
> + LP_PD_EN = BIT(0),
> +
> + /* PCTL_DFIODTCFG */
> + RANK0_ODT_WRITE_SEL = BIT(3),
> + RANK1_ODT_WRITE_SEL = BIT(11),
> +
> + /* PCTL_SCFG */
> + HW_LOW_POWER_EN = BIT(0),
> +
> + /* PCTL_MCMD */
> + START_CMD = BIT(31),
> + MCMD_RANK0 = BIT(20),
> + MCMD_RANK1 = BIT(21),
> + DESELECT_CMD = 0,
> + PREA_CMD,
> + REF_CMD,
> + MRS_CMD,
> + ZQCS_CMD,
> + ZQCL_CMD,
> + RSTL_CMD,
> + MRR_CMD = 8,
> + DPDE_CMD,
> +
> + /* PCTL_POWCTL */
> + POWER_UP_START = BIT(0),
> +
> + /* PCTL_POWSTAT */
> + POWER_UP_DONE = BIT(0),
> +
> + /* PCTL_SCTL */
> + INIT_STATE = 0,
> + CFG_STATE,
> + GO_STATE,
> + SLEEP_STATE,
> + WAKEUP_STATE,
> +
> + /* PCTL_STAT */
> + LP_TRIG_SHIFT = 4,
> + LP_TRIG_MASK = 7,
> + PCTL_STAT_MSK = 7,
> + INIT_MEM = 0,
> + CONFIG,
> + CONFIG_REQ,
> + ACCESS,
> + ACCESS_REQ,
> + LOW_POWER,
> + LOW_POWER_ENTRY_REQ,
> + LOW_POWER_EXIT_REQ,
> +
> + /* PCTL_MCFG */
> + DDR2_DDR3_BL_8 = BIT(0),
> + DDR3_EN = BIT(5),
> + TFAW_TRRD_MULT4 = (0 << 18),
> + TFAW_TRRD_MULT5 = (1 << 18),
> + TFAW_TRRD_MULT6 = (2 << 18),
> +};
> +
> +#define DDR3_MR0_WR(n) \
> + ((n <= 8) ? ((n - 4) << 9) : (((n >> 1) & 0x7) << 9))
> +#define DDR3_MR0_CL(n) \
> + ((((n - 4) & 0x7) << 4) | (((n - 4) & 0x8) >> 2))
> +#define DDR3_MR0_BL8 \
> + (0 << 0)
> +#define DDR3_MR0_DLL_RESET \
> + (1 << 8)
> +#define DDR3_MR1_RTT120OHM \
> + ((0 << 9) | (1 << 6) | (0 << 2))
> +#define DDR3_MR2_TWL(n) \
> + (((n - 5) & 0x7) << 3)
> +
> +
> +#ifdef CONFIG_TPL_BUILD
> +
> +static void ddr_set_noc_spr_err_stall(struct rk3368_grf *grf, bool enable)
> +{
> + if (enable)
> + rk_setreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL);
> + else
> + rk_clrreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL);
> +}
> +
> +static void ddr_set_ddr3_mode(struct rk3368_grf *grf, bool ddr3_mode)
> +{
> + if (ddr3_mode)
> + rk_setreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3);
> + else
> + rk_clrreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3);
> +}
> +
> +static void ddrphy_config(struct rk3368_ddrphy *phy,
> + u32 tcl, u32 tal, u32 tcwl)
> +{
> + int i;
> +
> + /* Set to DDR3 mode */
> + clrsetbits_le32(&phy->reg[1], 0x3, 0x0);
> +
> + /* DDRPHY_REGB: CL, AL */
> + clrsetbits_le32(&phy->reg[0xb], 0xff, tcl << 4 | tal);
> + /* DDRPHY_REGC: CWL */
> + clrsetbits_le32(&phy->reg[0xc], 0x0f, tcwl);
> +
> + /* Update drive-strength */
> + writel(0xcc, &phy->reg[0x11]);
> + writel(0xaa, &phy->reg[0x16]);
> + /*
> + * Update NRCOMP/PRCOMP for all 4 channels (for details of all
> + * affected registers refer to the documentation of DDRPHY_REG20
> + * and DDRPHY_REG21 in the RK3368 TRM.
> + */
> + for (i = 0; i < 4; ++i) {
> + writel(0xcc, &phy->reg[0x20 + i * 0x10]);
> + writel(0x44, &phy->reg[0x21 + i * 0x10]);
> + }
> +
> + /* Enable write-leveling calibration bypass */
> + setbits_le32(&phy->reg[2], BIT(3));
> +}
> +
> +static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
> +{
> + int i;
> +
> + for (i = 0; i < n / sizeof(u32); i++)
> + writel(*src++, dest++);
> +}
> +
> +static void send_command(struct rk3368_ddr_pctl *pctl, u32 rank, u32 cmd)
> +{
> + u32 mcmd = START_CMD | cmd | rank;
> +
> + debug("%s: writing %x to MCMD\n", __func__, mcmd);
> + writel(mcmd, &pctl->mcmd);
> + while (readl(&pctl->mcmd) & START_CMD)
> + /* spin */;
> +}
> +
> +static void send_mrs(struct rk3368_ddr_pctl *pctl,
> + u32 rank, u32 mr_num, u32 mr_data)
> +{
> + u32 mcmd = START_CMD | MRS_CMD | rank | (mr_num << 17) | (mr_data << 4);
> +
> + debug("%s: writing %x to MCMD\n", __func__, mcmd);
> + writel(mcmd, &pctl->mcmd);
> + while (readl(&pctl->mcmd) & START_CMD)
> + /* spin */;
> +}
> +
> +static int memory_init(struct rk3368_ddr_pctl *pctl,
> + struct rk3368_sdram_params *params)
> +{
> + u32 mr[4];
> + const ulong timeout_ms = 500;
> + ulong tmp;
> +
> + /*
> + * Power up DRAM by DDR_PCTL_POWCTL[0] register of PCTL and
> + * wait power up DRAM finish with DDR_PCTL_POWSTAT[0] register
> + * of PCTL.
> + */
> + writel(POWER_UP_START, &pctl->powctl);
> +
> + tmp = get_timer(0);
> + do {
> + if (get_timer(tmp) > timeout_ms) {
> + error("%s: POWER_UP_START did not complete in %ld ms\n",
> + __func__, timeout_ms);
> + return -ETIME;
> + }
> + } while (!(readl(&pctl->powstat) & POWER_UP_DONE));
> +
> + /* Configure MR0 through MR3 */
> + mr[0] = DDR3_MR0_WR(params->pctl_timing.twr) |
> + DDR3_MR0_CL(params->pctl_timing.tcl) |
> + DDR3_MR0_DLL_RESET;
> + mr[1] = DDR3_MR1_RTT120OHM;
> + mr[2] = DDR3_MR2_TWL(params->pctl_timing.tcwl);
> + mr[3] = 0;
> +
> + /*
> + * Also see RK3368 Technical Reference Manual:
> + * "16.6.2 Initialization (DDR3 Initialization Sequence)"
> + */
> + send_command(pctl, MCMD_RANK0 | MCMD_RANK1, DESELECT_CMD);
> + udelay(1);
> + send_command(pctl, MCMD_RANK0 | MCMD_RANK1, PREA_CMD);
> + send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 2, mr[2]);
> + send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 3, mr[3]);
> + send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 1, mr[1]);
> + send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 0, mr[0]);
> + send_command(pctl, MCMD_RANK0 | MCMD_RANK1, ZQCL_CMD);
> +
> + return 0;
> +}
> +
> +static void move_to_config_state(struct rk3368_ddr_pctl *pctl)
> +{
> + /*
> + * Also see RK3368 Technical Reference Manual:
> + * "16.6.1 State transition of PCTL (Moving to Config State)"
> + */
> + u32 state = readl(&pctl->stat) & PCTL_STAT_MSK;
> +
> + switch (state) {
> + case LOW_POWER:
> + writel(WAKEUP_STATE, &pctl->sctl);
> + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
> + /* spin */;
> +
> + /* fall-through */
> + case ACCESS:
> + case INIT_MEM:
> + writel(CFG_STATE, &pctl->sctl);
> + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
> + /* spin */;
> + break;
> +
> + case CONFIG:
> + return;
> +
> + default:
> + break;
> + }
> +}
> +
> +static void move_to_access_state(struct rk3368_ddr_pctl *pctl)
> +{
> + /*
> + * Also see RK3368 Technical Reference Manual:
> + * "16.6.1 State transition of PCTL (Moving to Access State)"
> + */
> + u32 state = readl(&pctl->stat) & PCTL_STAT_MSK;
> +
> + switch (state) {
> + case LOW_POWER:
> + if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) &
> + LP_TRIG_MASK) == 1)
> + return;
> +
> + writel(WAKEUP_STATE, &pctl->sctl);
> + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
> + /* spin */;
> +
> + /* fall-through */
> + case INIT_MEM:
> + writel(CFG_STATE, &pctl->sctl);
> + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
> + /* spin */;
> +
> + /* fall-through */
> + case CONFIG:
> + writel(GO_STATE, &pctl->sctl);
> + while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG)
> + /* spin */;
> + break;
> +
> + case ACCESS:
> + return;
> +
> + default:
> + break;
> + }
> +}
> +
> +static void ddrctl_reset(struct rk3368_cru *cru)
> +{
> + const u32 ctl_reset = BIT(3) | BIT(2);
> + const u32 phy_reset = BIT(1) | BIT(0);
> +
> + rk_setreg(&cru->softrst_con[10], ctl_reset | phy_reset);
> + udelay(1);
> + rk_clrreg(&cru->softrst_con[10], ctl_reset | phy_reset);
> +}
> +
> +static void ddrphy_reset(struct rk3368_ddrphy *ddrphy)
> +{
> + clrbits_le32(&ddrphy->reg[0], BIT(3) | BIT(2));
> + udelay(1);
> + setbits_le32(&ddrphy->reg[0], BIT(3) | BIT(2));
> +}
> +
> +static void ddrphy_config_delays(struct rk3368_ddrphy *ddrphy, u32 freq)
> +{
> + u32 dqs_dll_delay;
> +
> + setbits_le32(&ddrphy->reg[0x13], BIT(4));
> + clrbits_le32(&ddrphy->reg[0x14], BIT(3));
> +
> + setbits_le32(&ddrphy->reg[0x26], BIT(4));
> + clrbits_le32(&ddrphy->reg[0x27], BIT(3));
> +
> + setbits_le32(&ddrphy->reg[0x36], BIT(4));
> + clrbits_le32(&ddrphy->reg[0x37], BIT(3));
> +
> + setbits_le32(&ddrphy->reg[0x46], BIT(4));
> + clrbits_le32(&ddrphy->reg[0x47], BIT(3));
> +
> + setbits_le32(&ddrphy->reg[0x56], BIT(4));
> + clrbits_le32(&ddrphy->reg[0x57], BIT(3));
> +
> + if (freq <= 400000000)
> + setbits_le32(&ddrphy->reg[0xa4], 0x1f);
> + else
> + clrbits_le32(&ddrphy->reg[0xa4], 0x1f);
> +
> + if (freq < 681000000)
> + dqs_dll_delay = 3; /* 67.5 degree delay */
> + else
> + dqs_dll_delay = 2; /* 45 degree delay */
> +
> + writel(dqs_dll_delay, &ddrphy->reg[0x28]);
> + writel(dqs_dll_delay, &ddrphy->reg[0x38]);
> + writel(dqs_dll_delay, &ddrphy->reg[0x48]);
> + writel(dqs_dll_delay, &ddrphy->reg[0x58]);
> +}
> +
> +static int dfi_cfg(struct rk3368_ddr_pctl *pctl)
> +{
> + const ulong timeout_ms = 200;
> + ulong tmp;
> +
> + writel(DFI_DATA_BYTE_DISABLE_EN, &pctl->dfistcfg0);
> +
> + writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN,
> + &pctl->dfistcfg1);
> + writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2);
> + writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN,
> + &pctl->dfilpcfg0);
> +
> + writel(1, &pctl->dfitphyupdtype0);
> +
> + writel(0x1f, &pctl->dfitphyrdlat);
> + writel(0, &pctl->dfitphywrdata);
> + writel(0, &pctl->dfiupdcfg); /* phyupd and ctrlupd disabled */
> +
> + setbits_le32(&pctl->dfistcfg0, DFI_INIT_START);
> +
> + tmp = get_timer(0);
> + do {
> + if (get_timer(tmp) > timeout_ms) {
> + error("%s: DFI init did not complete within %ld ms\n",
> + __func__, timeout_ms);
> + return -ETIME;
> + }
> + } while ((readl(&pctl->dfiststat0) & 1) == 0);
> +
> + return 0;
> +}
> +
> +static inline u32 ps_to_tCK(const u32 ps, const ulong freq)
> +{
> + const ulong MHz = 1000000;
> + return DIV_ROUND_UP(ps * freq, 1000000 * MHz);
> +}
> +
> +static inline u32 ns_to_tCK(const u32 ns, const ulong freq)
> +{
> + return ps_to_tCK(ns * 1000, freq);
> +}
> +
> +static inline u32 tCK_to_ps(const ulong tCK, const ulong freq)
> +{
> + const ulong MHz = 1000000;
> + return DIV_ROUND_UP(tCK * 1000000 * MHz, freq);
> +}
> +
> +static int pctl_calc_timings(struct rk3368_sdram_params *params,
> + ulong freq)
> +{
> + struct rk3288_sdram_pctl_timing *pctl_timing = ¶ms->pctl_timing;
> + const ulong MHz = 1000000;
> + u32 tccd;
> + u32 tfaw_as_ps;
> +
> + if (params->ddr_speed_bin != DDR3_1600K) {
> + error("%s: unimplemented DDR3 speed bin %d\n",
> + __func__, params->ddr_speed_bin);
> + return -1;
> + }
> +
> + /* PCTL is clocked at 1/2 the DRAM clock; err on the side of caution */
> + pctl_timing->togcnt1u = DIV_ROUND_UP(freq, 2 * MHz);
> + pctl_timing->togcnt100n = DIV_ROUND_UP(freq / 10, 2 * MHz);
> +
> + pctl_timing->tinit = 200; /* 200 usec */
> + pctl_timing->trsth = 500; /* 500 usec */
> + pctl_timing->trefi = 78; /* 7.8usec = 78 * 100ns */
> + params->trefi_mem_ddr3 = ns_to_tCK(pctl_timing->trefi * 100, freq);
> +
> + if (freq <= (400 * MHz)) {
> + pctl_timing->tcl = 6;
> + pctl_timing->tcwl = 10;
> + } else if (freq <= (533 * MHz)) {
> + pctl_timing->tcl = 8;
> + pctl_timing->tcwl = 6;
> + } else if (freq <= (666 * MHz)) {
> + pctl_timing->tcl = 10;
> + pctl_timing->tcwl = 7;
> + } else {
> + pctl_timing->tcl = 11;
> + pctl_timing->tcwl = 8;
> + }
> +
> + pctl_timing->tmrd = 4; /* 4 tCK (all speed bins) */
> + pctl_timing->trfc = ns_to_tCK(350, freq); /* tRFC: 350 (max) @ 8GBit */
> + pctl_timing->trp = max(4u, ps_to_tCK(13750, freq));
> + /*
> + * JESD-79:
> + * READ to WRITE Command Delay = RL + tCCD / 2 + 2tCK - WL
> + */
> + tccd = 4;
> + pctl_timing->trtw = pctl_timing->tcl + tccd/2 + 2 - pctl_timing->tcwl;
> + pctl_timing->tal = 0;
> + pctl_timing->tras = ps_to_tCK(35000, freq);
> + pctl_timing->trc = ps_to_tCK(48750, freq);
> + pctl_timing->trcd = ps_to_tCK(13750, freq);
> + pctl_timing->trrd = max(4u, ps_to_tCK(7500, freq));
> + pctl_timing->trtp = max(4u, ps_to_tCK(7500, freq));
> + pctl_timing->twr = ps_to_tCK(15000, freq);
> + /* The DDR3 mode-register does only support even values for tWR > 8. */
> + if (pctl_timing->twr > 8)
> + pctl_timing->twr = (pctl_timing->twr + 1) & ~1;
> + pctl_timing->twtr = max(4u, ps_to_tCK(7500, freq));
> + pctl_timing->texsr = 512; /* tEXSR(max) is tDLLLK */
> + pctl_timing->txp = max(3u, ps_to_tCK(6000, freq));
> + pctl_timing->txpdll = max(10u, ps_to_tCK(24000, freq));
> + pctl_timing->tzqcs = max(64u, ps_to_tCK(80000, freq));
> + pctl_timing->tzqcsi = 10000; /* as used by Rockchip */
> + pctl_timing->tdqs = 1; /* fixed for DDR3 */
> + pctl_timing->tcksre = max(5u, ps_to_tCK(10000, freq));
> + pctl_timing->tcksrx = max(5u, ps_to_tCK(10000, freq));
> + pctl_timing->tcke = max(3u, ps_to_tCK(5000, freq));
> + pctl_timing->tmod = max(12u, ps_to_tCK(15000, freq));
> + pctl_timing->trstl = ns_to_tCK(100, freq);
> + pctl_timing->tzqcl = max(256u, ps_to_tCK(320000, freq)); /* tZQoper */
> + pctl_timing->tmrr = 0;
> + pctl_timing->tckesr = pctl_timing->tcke + 1; /* JESD-79: tCKE + 1tCK */
> + pctl_timing->tdpd = 0; /* RK3368 TRM: "allowed values for DDR3: 0" */
> +
> +
> + /*
> + * The controller can represent tFAW as 4x, 5x or 6x tRRD only.
> + * We want to use the smallest multiplier that satisfies the tFAW
> + * requirements of the given speed-bin. If necessary, we stretch out
> + * tRRD to allow us to operate on a 6x multiplier for tFAW.
> + */
> + tfaw_as_ps = 40000; /* 40ns: tFAW for DDR3-1600K, 2KB page-size */
> + if (tCK_to_ps(pctl_timing->trrd * 6, freq) < tfaw_as_ps) {
> + /* If tFAW is > 6 x tRRD, we need to stretch tRRD */
> + pctl_timing->trrd = ps_to_tCK(DIV_ROUND_UP(40000, 6), freq);
> + params->tfaw_mult = TFAW_TRRD_MULT6;
> + } else if (tCK_to_ps(pctl_timing->trrd * 5, freq) < tfaw_as_ps) {
> + params->tfaw_mult = TFAW_TRRD_MULT6;
> + } else if (tCK_to_ps(pctl_timing->trrd * 4, freq) < tfaw_as_ps) {
> + params->tfaw_mult = TFAW_TRRD_MULT5;
> + } else {
> + params->tfaw_mult = TFAW_TRRD_MULT4;
> + }
> +
> + return 0;
> +}
> +
> +static void pctl_cfg(struct rk3368_ddr_pctl *pctl,
> + struct rk3368_sdram_params *params,
> + struct rk3368_grf *grf)
> +{
> + /* Configure PCTL timing registers */
> + params->pctl_timing.trefi |= BIT(31); /* see PCTL_TREFI */
> + copy_to_reg(&pctl->togcnt1u, ¶ms->pctl_timing.togcnt1u,
> + sizeof(params->pctl_timing));
> + writel(params->trefi_mem_ddr3, &pctl->trefi_mem_ddr3);
> +
> + /* Set up ODT write selector and ODT write length */
> + writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL), &pctl->dfiodtcfg);
> + writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1);
> +
> + /* Set up the CL/CWL-dependent timings of DFI */
> + writel((params->pctl_timing.tcl - 1) / 2 - 1, &pctl->dfitrddataen);
> + writel((params->pctl_timing.tcwl - 1) / 2 - 1, &pctl->dfitphywrlat);
> +
> + /* DDR3 */
> + writel(params->tfaw_mult | DDR3_EN | DDR2_DDR3_BL_8, &pctl->mcfg);
> + writel(0x001c0004, &grf->ddrc0_con0);
> +
> + setbits_le32(&pctl->scfg, HW_LOW_POWER_EN);
> +}
> +
> +static int ddrphy_data_training(struct rk3368_ddr_pctl *pctl,
> + struct rk3368_ddrphy *ddrphy)
> +{
> + const u32 trefi = readl(&pctl->trefi);
> + const ulong timeout_ms = 500;
> + ulong tmp;
> +
> + /* disable auto-refresh */
> + writel(0 | BIT(31), &pctl->trefi);
> +
> + clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x20);
> + clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x21);
> +
> + tmp = get_timer(0);
> + do {
> + if (get_timer(tmp) > timeout_ms) {
> + error("%s: did not complete within %ld ms\n",
> + __func__, timeout_ms);
> + return -ETIME;
> + }
> + } while ((readl(&ddrphy->reg[0xff]) & 0xf) != 0xf);
> +
> + send_command(pctl, MCMD_RANK0 | MCMD_RANK1, PREA_CMD);
> + clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x20);
> + /* resume auto-refresh */
> + writel(trefi | BIT(31), &pctl->trefi);
> +
> + return 0;
> +}
> +
> +static int sdram_col_row_detect(struct udevice *dev)
> +{
> + struct dram_info *priv = dev_get_priv(dev);
> + struct rk3368_sdram_params *params = dev_get_platdata(dev);
> + struct rk3368_ddr_pctl *pctl = priv->pctl;
> + struct rk3368_msch *msch = priv->msch;
> + const u32 test_pattern = 0x5aa5f00f;
> + int row, col;
> + uintptr_t addr;
> +
> + move_to_config_state(pctl);
> + writel(6, &msch->ddrconf);
> + move_to_access_state(pctl);
> +
> + /* Detect col */
> + for (col = 11; col >= 9; col--) {
> + writel(0, CONFIG_SYS_SDRAM_BASE);
> + addr = CONFIG_SYS_SDRAM_BASE +
> + (1 << (col + params->chan.bw - 1));
> + writel(test_pattern, addr);
> + if ((readl(addr) == test_pattern) &&
> + (readl(CONFIG_SYS_SDRAM_BASE) == 0))
> + break;
> + }
> +
> + if (col == 8) {
> + error("%s: col detect error\n", __func__);
> + return -EINVAL;
> + }
> +
> + move_to_config_state(pctl);
> + writel(15, &msch->ddrconf);
> + move_to_access_state(pctl);
> +
> + /* Detect row*/
> + for (row = 16; row >= 12; row--) {
> + writel(0, CONFIG_SYS_SDRAM_BASE);
> + addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
> + writel(test_pattern, addr);
> + if ((readl(addr) == test_pattern) &&
> + (readl(CONFIG_SYS_SDRAM_BASE) == 0))
> + break;
> + }
> +
> + if (row == 11) {
> + error("%s: row detect error\n", __func__);
> + return -EINVAL;
> + }
> +
> + /* Record results */
> + debug("%s: col %d, row %d\n", __func__, col, row);
> + params->chan.col = col;
> + params->chan.cs0_row = row;
> + params->chan.cs1_row = row;
> + params->chan.row_3_4 = 0;
> +
> + return 0;
> +}
> +
> +static int msch_niu_config(struct rk3368_msch *msch,
> + struct rk3368_sdram_params *params)
> +{
> + int i;
> + const u8 cols = params->chan.col - ((params->chan.bw == 2) ? 0 : 1);
> + const u8 rows = params->chan.cs0_row;
> +
> + /*
> + * The DDR address-translation table always assumes a 32bit
> + * bus and the comparison below takes care of adjusting for
> + * a 16bit bus (i.e. one column-address is consumed).
> + */
> + const struct {
> + u8 rows;
> + u8 columns;
> + u8 type;
> + } ddrconf_table[] = {
> + /*
> + * C-B-R-D patterns are first. For these we require an
> + * exact match for the columns and rows (as there's
> + * one entry per possible configuration).
> + */
> + [0] = { .rows = 13, .columns = 10, .type = DMC_MSCH_CBRD },
> + [1] = { .rows = 14, .columns = 10, .type = DMC_MSCH_CBRD },
> + [2] = { .rows = 15, .columns = 10, .type = DMC_MSCH_CBRD },
> + [3] = { .rows = 16, .columns = 10, .type = DMC_MSCH_CBRD },
> + [4] = { .rows = 14, .columns = 11, .type = DMC_MSCH_CBRD },
> + [5] = { .rows = 15, .columns = 11, .type = DMC_MSCH_CBRD },
> + [6] = { .rows = 16, .columns = 11, .type = DMC_MSCH_CBRD },
> + [7] = { .rows = 13, .columns = 9, .type = DMC_MSCH_CBRD },
> + [8] = { .rows = 14, .columns = 9, .type = DMC_MSCH_CBRD },
> + [9] = { .rows = 15, .columns = 9, .type = DMC_MSCH_CBRD },
> + [10] = { .rows = 16, .columns = 9, .type = DMC_MSCH_CBRD },
> + /*
> + * 11 through 13 are C-R-B-D patterns. These are
> + * matched for an exact number of columns and to
> + * ensure that the hardware uses at least as many rows
> + * as the pattern requires (i.e. we make sure that
> + * there's no gaps up until we hit the device/chip-select;
> + * however, these patterns can accept up to 16 rows,
> + * as the row-address continues right after the CS
> + * switching)
> + */
> + [11] = { .rows = 15, .columns = 10, .type = DMC_MSCH_CRBD },
> + [12] = { .rows = 14, .columns = 11, .type = DMC_MSCH_CRBD },
> + [13] = { .rows = 13, .columns = 10, .type = DMC_MSCH_CRBD },
> + /*
> + * 14 and 15 are catch-all variants using a C-B-D-R
> + * scheme (i.e. alternating the chip-select every time
> + * C-B overflows) and stuffing the remaining C-bits
> + * into the top. Matching needs to make sure that the
> + * number of columns is either an exact match (i.e. we
> + * can use less the the maximum number of rows) -or-
> + * that the columns exceed what is given in this table
> + * and the rows are an exact match (in which case the
> + * remaining C-bits will be stuffed onto the top after
> + * the device/chip-select switches).
> + */
> + [14] = { .rows = 16, .columns = 10, .type = DMC_MSCH_CBDR },
> + [15] = { .rows = 16, .columns = 9, .type = DMC_MSCH_CBDR },
> + };
> +
> + /*
> + * For C-B-R-D, we need an exact match (i.e. both for the number of
> + * columns and rows), while for C-B-D-R, only the the number of
> + * columns needs to match.
> + */
> + for (i = 0; i < ARRAY_SIZE(ddrconf_table); i++) {
> + bool match = false;
> +
> + /* If this entry if for a different matcher, then skip it */
> + if (ddrconf_table[i].type != params->memory_schedule)
> + continue;
> +
> + /*
> + * Match according to the rules (exact/inexact/at-least)
> + * documented in the ddrconf_table above.
> + */
> + switch (params->memory_schedule) {
> + case DMC_MSCH_CBRD:
> + match = (ddrconf_table[i].columns == cols) &&
> + (ddrconf_table[i].rows == rows);
> + break;
> +
> + case DMC_MSCH_CRBD:
> + match = (ddrconf_table[i].columns == cols) &&
> + (ddrconf_table[i].rows <= rows);
> + break;
> +
> + case DMC_MSCH_CBDR:
> + match = (ddrconf_table[i].columns == cols) ||
> + ((ddrconf_table[i].columns <= cols) &&
> + (ddrconf_table[i].rows == rows));
> + break;
> +
> + default:
> + break;
> + }
> +
> + if (match) {
> + debug("%s: setting ddrconf 0x%x\n", __func__, i);
> + writel(i, &msch->ddrconf);
> + return 0;
> + }
> + }
> +
> + error("%s: ddrconf (NIU config) not found\n", __func__);
> + return -EINVAL;
> +}
> +
> +static void dram_all_config(struct udevice *dev)
> +{
> + struct dram_info *priv = dev_get_priv(dev);
> + struct rk3368_pmu_grf *pmugrf = priv->pmugrf;
> + struct rk3368_sdram_params *params = dev_get_platdata(dev);
> + const struct rk3288_sdram_channel *info = ¶ms->chan;
> + u32 sys_reg = 0;
> + const int chan = 0;
> +
> + sys_reg |= DDR3 << SYS_REG_DDRTYPE_SHIFT;
> + sys_reg |= 0 << SYS_REG_NUM_CH_SHIFT;
> +
> + sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan);
> + sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan);
> + sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan);
> + sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan);
> + sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan);
> + sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan);
> + sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan);
> + sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan);
> + sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan);
> +
> + writel(sys_reg, &pmugrf->os_reg[2]);
> +}
> +
> +static int setup_sdram(struct udevice *dev)
> +{
> + struct dram_info *priv = dev_get_priv(dev);
> + struct rk3368_sdram_params *params = dev_get_platdata(dev);
> +
> + struct rk3368_ddr_pctl *pctl = priv->pctl;
> + struct rk3368_ddrphy *ddrphy = priv->phy;
> + struct rk3368_cru *cru = priv->cru;
> + struct rk3368_grf *grf = priv->grf;
> + struct rk3368_msch *msch = priv->msch;
> +
> + int ret;
> +
> + /* The input clock (i.e. DPLL) needs to be 2x the DRAM frequency */
> + ret = clk_set_rate(&priv->ddr_clk, 2 * params->ddr_freq);
> + if (ret < 0) {
> + debug("%s: could not set DDR clock: %d\n", __func__, ret);
> + return ret;
> + }
> +
> + /* Update the read-latency for the RK3368 */
> + writel(0x32, &msch->readlatency);
> +
> + /* Initialise the DDR PCTL and DDR PHY */
> + ddrctl_reset(cru);
> + ddrphy_reset(ddrphy);
> + ddrphy_config_delays(ddrphy, params->ddr_freq);
> + dfi_cfg(pctl);
> + /* Configure relative system information of grf_ddrc0_con0 register */
> + ddr_set_ddr3_mode(grf, true);
> + ddr_set_noc_spr_err_stall(grf, true);
> + /* Calculate timings */
> + pctl_calc_timings(params, params->ddr_freq);
> + /* Initialise the device timings in protocol controller */
> + pctl_cfg(pctl, params, grf);
> + /* Configure AL, CL ... information of PHY registers */
> + ddrphy_config(ddrphy,
> + params->pctl_timing.tcl,
> + params->pctl_timing.tal,
> + params->pctl_timing.tcwl);
> +
> + /* Initialize DRAM and configure with mode-register values */
> + ret = memory_init(pctl, params);
> + if (ret)
> + goto error;
> +
> + move_to_config_state(pctl);
> + /* Perform data-training */
> + ddrphy_data_training(pctl, ddrphy);
> + move_to_access_state(pctl);
> +
> + /* TODO(prt): could detect rank in training... */
> + params->chan.rank = 2;
> + /* TODO(prt): bus width is not auto-detected (yet)... */
> + params->chan.bw = 2; /* 32bit wide bus */
> + params->chan.dbw = params->chan.dbw; /* 32bit wide bus */
> +
> + /* DDR3 is always 8 bank */
> + params->chan.bk = 3;
> + /* Detect col and row number */
> + ret = sdram_col_row_detect(dev);
> + if (ret)
> + goto error;
> +
> + /* Configure NIU DDR configuration */
> + ret = msch_niu_config(msch, params);
> + if (ret)
> + goto error;
> +
> + /* set up OS_REG to communicate w/ next stage and OS */
> + dram_all_config(dev);
> +
> + return 0;
> +
> +error:
> + printf("DRAM init failed!\n");
> + hang();
> +}
> +#endif
> +
> +static int rk3368_dmc_ofdata_to_platdata(struct udevice *dev)
> +{
> + int ret = 0;
> +
> +#if !CONFIG_IS_ENABLED(OF_PLATDATA)
> + struct rk3368_sdram_params *plat = dev_get_platdata(dev);
> +
> + ret = regmap_init_mem(dev, &plat->map);
> + if (ret)
> + return ret;
> +#endif
> +
> + return ret;
> +}
> +
> +#if CONFIG_IS_ENABLED(OF_PLATDATA)
> +static int conv_of_platdata(struct udevice *dev)
> +{
> + struct rk3368_sdram_params *plat = dev_get_platdata(dev);
> + struct dtd_rockchip_rk3368_dmc *of_plat = &plat->of_plat;
> + int ret;
> +
> + plat->ddr_freq = of_plat->rockchip_ddr_frequency;
> + plat->ddr_speed_bin = of_plat->rockchip_ddr_speed_bin;
> + plat->memory_schedule = of_plat->rockchip_memory_schedule;
> +
> + ret = regmap_init_mem_platdata(dev, of_plat->reg,
> + ARRAY_SIZE(of_plat->reg) / 2,
> + &plat->map);
> + if (ret)
> + return ret;
> +
> + return 0;
> +}
> +#endif
> +
> +static int rk3368_dmc_probe(struct udevice *dev)
> +{
> +#ifdef CONFIG_TPL_BUILD
> + struct rk3368_sdram_params *plat = dev_get_platdata(dev);
> + struct rk3368_ddr_pctl *pctl;
> + struct rk3368_ddrphy *ddrphy;
> + struct rk3368_cru *cru;
> + struct rk3368_grf *grf;
> + struct rk3368_msch *msch;
> + int ret;
> + struct udevice *dev_clk;
> +#endif
> + struct dram_info *priv = dev_get_priv(dev);
> +
> +#if CONFIG_IS_ENABLED(OF_PLATDATA)
> + ret = conv_of_platdata(dev);
> + if (ret)
> + return ret;
> +#endif
> +
> + priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
> + debug("%s: pmugrf=%p\n", __func__, priv->pmugrf);
> +
> +#ifdef CONFIG_TPL_BUILD
> + pctl = regmap_get_range(plat->map, 0);
> + ddrphy = regmap_get_range(plat->map, 1);
> + msch = syscon_get_first_range(ROCKCHIP_SYSCON_MSCH);
> + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
> +
> + priv->pctl = pctl;
> + priv->phy = ddrphy;
> + priv->msch = msch;
> + priv->grf = grf;
> +
> + ret = rockchip_get_clk(&dev_clk);
> + if (ret)
> + return ret;
> + priv->ddr_clk.id = CLK_DDR;
> + ret = clk_request(dev_clk, &priv->ddr_clk);
> + if (ret)
> + return ret;
> +
> + cru = rockchip_get_cru();
> + priv->cru = cru;
> + if (IS_ERR(priv->cru))
> + return PTR_ERR(priv->cru);
> +
> + ret = setup_sdram(dev);
> + if (ret)
> + return ret;
> +#endif
> +
> + priv->info.base = 0;
> + priv->info.size =
> + rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg[2]);
> +
> + /*
> + * we use the 0x00000000~0xfdffffff space since 0xff000000~0xffffffff
> + * is SoC register space (i.e. reserved), and 0xfe000000~0xfeffffff is
> + * inaccessible for some IP controller.
> + */
> + priv->info.size = min(priv->info.size, (size_t)0xfe000000);
> +
> + return 0;
> +}
> +
> +static int rk3368_dmc_get_info(struct udevice *dev, struct ram_info *info)
> +{
> + struct dram_info *priv = dev_get_priv(dev);
> +
> + *info = priv->info;
> + return 0;
> +}
> +
> +static struct ram_ops rk3368_dmc_ops = {
> + .get_info = rk3368_dmc_get_info,
> +};
> +
> +
> +static const struct udevice_id rk3368_dmc_ids[] = {
> + { .compatible = "rockchip,rk3368-dmc" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(dmc_rk3368) = {
> + .name = "rockchip_rk3368_dmc",
> + .id = UCLASS_RAM,
> + .of_match = rk3368_dmc_ids,
> + .ops = &rk3368_dmc_ops,
> + .probe = rk3368_dmc_probe,
> + .priv_auto_alloc_size = sizeof(struct dram_info),
> + .ofdata_to_platdata = rk3368_dmc_ofdata_to_platdata,
> + .probe = rk3368_dmc_probe,
> + .priv_auto_alloc_size = sizeof(struct dram_info),
> + .platdata_auto_alloc_size = sizeof(struct rk3368_sdram_params),
> +};
> diff --git a/include/dt-bindings/memory/rk3368-dmc.h b/include/dt-bindings/memory/rk3368-dmc.h
> new file mode 100644
> index 0000000..b06ffde
> --- /dev/null
> +++ b/include/dt-bindings/memory/rk3368-dmc.h
> @@ -0,0 +1,30 @@
> +#ifndef DT_BINDINGS_RK3368_DMC_H
> +#define DT_BINDINGS_RK3368_DMC_H
> +
> +#define DMC_MSCH_CBDR 0x0
> +#define DMC_MSCH_CBRD 0x1
> +#define DMC_MSCH_CRBD 0x2
> +
> +#define DDR3_800D 0
> +#define DDR3_800E 1
> +#define DDR3_1066E 2
> +#define DDR3_1066F 3
> +#define DDR3_1066G 4
> +#define DDR3_1333F 5
> +#define DDR3_1333G 6
> +#define DDR3_1333H 7
> +#define DDR3_1333J 8
> +#define DDR3_1600G 9
> +#define DDR3_1600H 10
> +#define DDR3_1600J 11
> +#define DDR3_1600K 12
> +#define DDR3_1866J 13
> +#define DDR3_1866K 14
> +#define DDR3_1866L 15
> +#define DDR3_1866M 16
> +#define DDR3_2133K 17
> +#define DDR3_2133L 18
> +#define DDR3_2133M 19
> +#define DDR3_2133N 20
> +
> +#endif
^ permalink raw reply [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 50/66] rockchip: rk3368: add DRAM controller driver with DRAM initialisation
2017-08-01 1:30 ` Andy Yan
@ 2017-08-01 2:09 ` 汤云平
0 siblings, 0 replies; 95+ messages in thread
From: 汤云平 @ 2017-08-01 2:09 UTC (permalink / raw)
To: u-boot
Dear Tomsich：
see as below，
diff --git a/drivers/ram/rockchip/dmc-rk3368.c b/drivers/ram/rockchip/dmc-rk3368.c
index fea96a5..d4cece5 100644
--- a/drivers/ram/rockchip/dmc-rk3368.c
+++ b/drivers/ram/rockchip/dmc-rk3368.c
@@ -333,17 +333,25 @@ static void ddrctl_reset(struct rk3368_cru *cru)
{
const u32 ctl_reset = BIT(3) | BIT(2);
const u32 phy_reset = BIT(1) | BIT(0);
-
+ /* should de-reset phy before de-reset pctl */
rk_setreg(&cru->softrst_con[10], ctl_reset | phy_reset);
udelay(1);
- rk_clrreg(&cru->softrst_con[10], ctl_reset | phy_reset);
+ rk_clrreg(&cru->softrst_con[10], phy_reset);
+ udelay(5);
+ rk_clrreg(&cru->softrst_con[10], ctl_reset);
}
static void ddrphy_reset(struct rk3368_ddrphy *ddrphy)
{
+ /*
+ * phy de-reset should de-reset analog part before
+ * digital part abort 1000 dram cycle.
+ */
clrbits_le32(&ddrphy->reg[0], BIT(3) | BIT(2));
udelay(1);
- setbits_le32(&ddrphy->reg[0], BIT(3) | BIT(2));
+ setbits_le32(&ddrphy->reg[0], BIT(2));
+ udelay(5);
+ setbits_le32(&ddrphy->reg[0], BIT(3));
}
@@ -984,7 +992,6 @@ U_BOOT_DRIVER(dmc_rk3368) = {
.probe = rk3368_dmc_probe,
.priv_auto_alloc_size = sizeof(struct dram_info),
.ofdata_to_platdata = rk3368_dmc_ofdata_to_platdata,
- .probe = rk3368_dmc_probe,
.priv_auto_alloc_size = sizeof(struct dram_info),
.platdata_auto_alloc_size = sizeof(struct rk3368_sdram_params),
};
Thanks
--------------
汤云平
福州瑞芯微电子有限公司
Fuzhou Rockchip Electronics Co.Ltd
福建省福州市铜盘路软件大道89号软件园A区21号楼 (350003)
No. 21 Building, A District, No.89,software Boulevard Fuzhou,Fujian,PRC
mail: typ at rock-chips.com
phone of Fuzhou：0591－83991906/07 -8884
保密提示：
本邮件及其附件含有机密信息，仅发送给本邮件所指特定收件人。
若非该特定收件人，请勿复制、 使用或披露本邮件的任何内容。
若误收本邮件，请从系统中永久性删除本邮件及所有附件，并以回复邮件或其他方式即刻告知发件人。
福州瑞芯微电子有限公司拥有本邮件信息的著作权及解释权，禁止任何未经授权许可的侵权行为。
IMPORTANT NOTICE:
This email is from Fuzhou Rockchip Electronics Co., Ltd .
The contents of this email and any attachments may contain information that is privileged, confidential and/or exempt from disclosure under applicable law and relevant NDA.
If you are not the intended recipient, you are hereby notified that any disclosure, copying, distribution, or use of the information is STRICTLY PROHIBITED.
Please immediately contact the sender as soon as possible and destroy the material in its entirety in any format. Thank you.
--------------------------------------------------------
From: Andy Yan
Date: 2017-08-01 09:30
To: Philipp Tomsich; u-boot
CC: Kever Yang; Klaus Goger; Simon Glass; Andreas Färber; Álvaro Fernández Rojas; Albert Aribaud; Vikas Manocha; Joe Hershberger; tony.tang
Subject: Re: [PATCH v3 50/66] rockchip: rk3368: add DRAM controller driver with DRAM initialisation
add Tony from our dram team, maybe he has some ideas for this patch.
On 2017年07月29日 03:22, Philipp Tomsich wrote:
> This adds a DRAM controller driver for the RK3368 and places it in
> drivers/ram/rockchip (where the other DM-enabled DRAM controller
> drivers for rockchip devices should also be moved eventually).
>
> At this stage, only the following feature-set is supported:
> - DDR3
> - 32-bit configuration (i.e. fully populated)
> - dual-rank (i.e. no auto-detection of ranks)
> - DDR3-1600K speed-bin
>
> This driver expects to run from a TPL stage that will later return to
> the RK3368 BROM. It communicates with later stages through the
> os_reg2 in the pmugrf (i.e. using the same mechanism as Rockchip's DDR
> init code).
>
> Unlike other DMC drivers for RK32xx and RK33xx parts, the required
> timings are calculated within the driver based on a target frequency
> and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this
> time).
>
> The RK3368 also has the DDRC0_CON0 (DDR ch. 0, control-register 0)
> register for controlling the operation of its (single-channel) DRAM
> controller in the GRF block. This provides for selecting DDR3, mobile
> DDR modes, and control low-power operation.
> As part of this change, DDRC0_CON0 is also added to the GRF structure
> definition (at offset 0x600).
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v3:
> - correctly states the location of the driver in the commit message
>
> Changes in v2: None
>
> arch/arm/include/asm/arch-rockchip/ddr_rk3368.h | 187 ++++
> arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 3 +
> arch/arm/mach-rockchip/rk3368/Makefile | 1 -
> arch/arm/mach-rockchip/rk3368/sdram_rk3368.c | 60 --
> .../clock/rockchip,rk3368-dmc.txt | 67 ++
> drivers/ram/Makefile | 2 +
> drivers/ram/rockchip/Makefile | 7 +
> drivers/ram/rockchip/dmc-rk3368.c | 990 +++++++++++++++++++++
> include/dt-bindings/memory/rk3368-dmc.h | 30 +
> 9 files changed, 1286 insertions(+), 61 deletions(-)
> create mode 100644 arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
> delete mode 100644 arch/arm/mach-rockchip/rk3368/sdram_rk3368.c
> create mode 100644 doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt
> create mode 100644 drivers/ram/rockchip/Makefile
> create mode 100644 drivers/ram/rockchip/dmc-rk3368.c
> create mode 100644 include/dt-bindings/memory/rk3368-dmc.h
>
> diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h b/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
> new file mode 100644
> index 0000000..4e2b233
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
> @@ -0,0 +1,187 @@
> +/*
> + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + */
> +
> +#ifndef __ASM_ARCH_DDR_RK3368_H__
> +#define __ASM_ARCH_DDR_RK3368_H__
> +
> +/*
> + * The RK3368 DDR PCTL differs from the incarnation in the RK3288 only
> + * in a few details. Most notably, it has an additional field to track
> + * tREFI in controller cycles (i.e. trefi_mem_ddr3).
> + */
> +struct rk3368_ddr_pctl {
> + u32 scfg;
> + u32 sctl;
> + u32 stat;
> + u32 intrstat;
> + u32 reserved0[12];
> + u32 mcmd;
> + u32 powctl;
> + u32 powstat;
> + u32 cmdtstat;
> + u32 cmdtstaten;
> + u32 reserved1[3];
> + u32 mrrcfg0;
> + u32 mrrstat0;
> + u32 mrrstat1;
> + u32 reserved2[4];
> + u32 mcfg1;
> + u32 mcfg;
> + u32 ppcfg;
> + u32 mstat;
> + u32 lpddr2zqcfg;
> + u32 reserved3;
> + u32 dtupdes;
> + u32 dtuna;
> + u32 dtune;
> + u32 dtuprd0;
> + u32 dtuprd1;
> + u32 dtuprd2;
> + u32 dtuprd3;
> + u32 dtuawdt;
> + u32 reserved4[3];
> + u32 togcnt1u;
> + u32 tinit;
> + u32 trsth;
> + u32 togcnt100n;
> + u32 trefi;
> + u32 tmrd;
> + u32 trfc;
> + u32 trp;
> + u32 trtw;
> + u32 tal;
> + u32 tcl;
> + u32 tcwl;
> + u32 tras;
> + u32 trc;
> + u32 trcd;
> + u32 trrd;
> + u32 trtp;
> + u32 twr;
> + u32 twtr;
> + u32 texsr;
> + u32 txp;
> + u32 txpdll;
> + u32 tzqcs;
> + u32 tzqcsi;
> + u32 tdqs;
> + u32 tcksre;
> + u32 tcksrx;
> + u32 tcke;
> + u32 tmod;
> + u32 trstl;
> + u32 tzqcl;
> + u32 tmrr;
> + u32 tckesr;
> + u32 tdpd;
> + u32 trefi_mem_ddr3;
> + u32 reserved5[45];
> + u32 dtuwactl;
> + u32 dturactl;
> + u32 dtucfg;
> + u32 dtuectl;
> + u32 dtuwd0;
> + u32 dtuwd1;
> + u32 dtuwd2;
> + u32 dtuwd3;
> + u32 dtuwdm;
> + u32 dturd0;
> + u32 dturd1;
> + u32 dturd2;
> + u32 dturd3;
> + u32 dtulfsrwd;
> + u32 dtulfsrrd;
> + u32 dtueaf;
> + u32 dfitctrldelay;
> + u32 dfiodtcfg;
> + u32 dfiodtcfg1;
> + u32 dfiodtrankmap;
> + u32 dfitphywrdata;
> + u32 dfitphywrlat;
> + u32 reserved7[2];
> + u32 dfitrddataen;
> + u32 dfitphyrdlat;
> + u32 reserved8[2];
> + u32 dfitphyupdtype0;
> + u32 dfitphyupdtype1;
> + u32 dfitphyupdtype2;
> + u32 dfitphyupdtype3;
> + u32 dfitctrlupdmin;
> + u32 dfitctrlupdmax;
> + u32 dfitctrlupddly;
> + u32 reserved9;
> + u32 dfiupdcfg;
> + u32 dfitrefmski;
> + u32 dfitctrlupdi;
> + u32 reserved10[4];
> + u32 dfitrcfg0;
> + u32 dfitrstat0;
> + u32 dfitrwrlvlen;
> + u32 dfitrrdlvlen;
> + u32 dfitrrdlvlgateen;
> + u32 dfiststat0;
> + u32 dfistcfg0;
> + u32 dfistcfg1;
> + u32 reserved11;
> + u32 dfitdramclken;
> + u32 dfitdramclkdis;
> + u32 dfistcfg2;
> + u32 dfistparclr;
> + u32 dfistparlog;
> + u32 reserved12[3];
> + u32 dfilpcfg0;
> + u32 reserved13[3];
> + u32 dfitrwrlvlresp0;
> + u32 dfitrwrlvlresp1;
> + u32 dfitrwrlvlresp2;
> + u32 dfitrrdlvlresp0;
> + u32 dfitrrdlvlresp1;
> + u32 dfitrrdlvlresp2;
> + u32 dfitrwrlvldelay0;
> + u32 dfitrwrlvldelay1;
> + u32 dfitrwrlvldelay2;
> + u32 dfitrrdlvldelay0;
> + u32 dfitrrdlvldelay1;
> + u32 dfitrrdlvldelay2;
> + u32 dfitrrdlvlgatedelay0;
> + u32 dfitrrdlvlgatedelay1;
> + u32 dfitrrdlvlgatedelay2;
> + u32 dfitrcmd;
> + u32 reserved14[46];
> + u32 ipvr;
> + u32 iptr;
> +};
> +check_member(rk3368_ddr_pctl, iptr, 0x03fc);
> +
> +struct rk3368_ddrphy {
> + u32 reg[0x100];
> +};
> +check_member(rk3368_ddrphy, reg[0xff], 0x03fc);
> +
> +struct rk3368_msch {
> + u32 coreid;
> + u32 revisionid;
> + u32 ddrconf;
> + u32 ddrtiming;
> + u32 ddrmode;
> + u32 readlatency;
> + u32 reserved1[8];
> + u32 activate;
> + u32 devtodev;
> +};
> +check_member(rk3368_msch, devtodev, 0x003c);
> +
> +/* GRF_SOC_CON0 */
> +enum {
> + NOC_RSP_ERR_STALL = BIT(9),
> + MOBILE_DDR_SEL = BIT(4),
> + DDR0_16BIT_EN = BIT(3),
> + MSCH0_MAINDDR3_DDR3 = BIT(2),
> + MSCH0_MAINPARTIALPOP = BIT(1),
> + UPCTL_C_ACTIVE = BIT(0),
> +};
> +
> +#endif
> diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
> index 1f84ff9..6b6651a 100644
> --- a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
> +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
> @@ -76,8 +76,11 @@ struct rk3368_grf {
> u32 soc_con15;
> u32 soc_con16;
> u32 soc_con17;
> + u32 reserved5[0x6e];
> + u32 ddrc0_con0;
> };
> check_member(rk3368_grf, soc_con17, 0x444);
> +check_member(rk3368_grf, ddrc0_con0, 0x600);
>
> struct rk3368_pmu_grf {
> u32 gpio0a_iomux;
> diff --git a/arch/arm/mach-rockchip/rk3368/Makefile b/arch/arm/mach-rockchip/rk3368/Makefile
> index 0390716..46798c2 100644
> --- a/arch/arm/mach-rockchip/rk3368/Makefile
> +++ b/arch/arm/mach-rockchip/rk3368/Makefile
> @@ -5,5 +5,4 @@
> #
> obj-y += clk_rk3368.o
> obj-y += rk3368.o
> -obj-y += sdram_rk3368.o
> obj-y += syscon_rk3368.o
> diff --git a/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c b/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c
> deleted file mode 100644
> index d0d0900..0000000
> --- a/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c
> +++ /dev/null
> @@ -1,60 +0,0 @@
> -/*
> - * (C) Copyright 2016 Rockchip Electronics Co., Ltd.
> - *
> - * SPDX-License-Identifier: GPL-2.0
> - */
> -
> -#include <common.h>
> -#include <dm.h>
> -#include <ram.h>
> -#include <syscon.h>
> -#include <asm/arch/clock.h>
> -#include <asm/arch/grf_rk3368.h>
> -#include <asm/arch/sdram_common.h>
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -struct dram_info {
> - struct ram_info info;
> - struct rk3368_pmu_grf *pmugrf;
> -};
> -
> -static int rk3368_dmc_probe(struct udevice *dev)
> -{
> - struct dram_info *priv = dev_get_priv(dev);
> -
> - priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
> - debug("%s: grf=%p\n", __func__, priv->pmugrf);
> - priv->info.base = CONFIG_SYS_SDRAM_BASE;
> - priv->info.size = rockchip_sdram_size(
> - (phys_addr_t)&priv->pmugrf->os_reg[2]);
> -
> - return 0;
> -}
> -
> -static int rk3368_dmc_get_info(struct udevice *dev, struct ram_info *info)
> -{
> - struct dram_info *priv = dev_get_priv(dev);
> -
> - *info = priv->info;
> -
> - return 0;
> -}
> -
> -static struct ram_ops rk3368_dmc_ops = {
> - .get_info = rk3368_dmc_get_info,
> -};
> -
> -
> -static const struct udevice_id rk3368_dmc_ids[] = {
> - { .compatible = "rockchip,rk3368-dmc" },
> - { }
> -};
> -
> -U_BOOT_DRIVER(dmc_rk3368) = {
> - .name = "rockchip_rk3368_dmc",
> - .id = UCLASS_RAM,
> - .of_match = rk3368_dmc_ids,
> - .ops = &rk3368_dmc_ops,
> - .probe = rk3368_dmc_probe,
> - .priv_auto_alloc_size = sizeof(struct dram_info),
> -};
> diff --git a/doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt b/doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt
> new file mode 100644
> index 0000000..8e7357d
> --- /dev/null
> +++ b/doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt
> @@ -0,0 +1,67 @@
> +RK3368 dynamic memory controller driver
> +=======================================
> +
> +The RK3368 DMC (dynamic memory controller) driver supports setup/initialisation
> +during TPL using configuration data from the DTS (i.e. OF_PLATDATA), based on
> +the following key configuration data:
> + (a) a target-frequency (i.e. operating point) for the memory operation
> + (b) a speed-bin (as defined in JESD-79) for the DDR3 used in hardware
> + (c) a memory-schedule (i.e. mapping from physical addresses to the address
> + pins of the memory bus)
> +
> +Required properties
> +-------------------
> +
> +- compatible: "rockchip,rk3368-dmc"
> +- reg
> + protocol controller (PCTL) address and PHY controller (DDRPHY) address
> +- rockchip,ddr-speed-bin
> + the DDR3 device's speed-bin (as specified according to JESD-79)
> + DDR3_800D (5-5-5)
> + DDR3_800E (6-6-6)
> + DDR3_1066E (6-6-6)
> + DDR3_1066F (7-7-7)
> + DDR3_1066G (8-8-8)
> + DDR3_1333F (7-7-7)
> + DDR3_1333G (8-8-8)
> + DDR3_1333H (9-9-9)
> + DDR3_1333J (10-10-10)
> + DDR3_1600G (8-8-8)
> + DDR3_1600H (9-9-9)
> + DDR3_1600J (10-10-10)
> + DDR3_1600K (11-11-11)
> + DDR3_1866J (10-10-10)
> + DDR3_1866K (11-11-11)
> + DDR3_1866L (12-12-12)
> + DDR3_1866M (13-13-13)
> + DDR3_2133K (11-11-11)
> + DDR3_2133L (12-12-12)
> + DDR3_2133M (13-13-13)
> + DDR3_2133N (14-14-14)
> +- rockchip,ddr-frequency:
> + target DDR clock frequency in Hz (not all frequencies may be supported,
> + as there's some cooperation from the clock-driver required)
> +- rockchip,memory-schedule:
> + controls the decoding of physical addresses to DRAM addressing (i.e. how
> + the physical address maps onto the address pins/chip-select of the device)
> + DMC_MSCH_CBDR: column -> bank -> device -> row
> + DMC_MSCH_CBRD: column -> band -> row -> device
> + DMC_MSCH_CRBD: column -> row -> band -> device
> +
> +Example (for DDR3-1600K and 800MHz)
> +-----------------------------------
> +
> + #include <dt-bindings/memory/rk3368-dmc.h>
> +
> + dmc: dmc at ff610000 {
> + u-boot,dm-pre-reloc;
> + compatible = "rockchip,rk3368-dmc";
> + reg = <0 0xff610000 0 0x400
> + 0 0xff620000 0 0x400>;
> + };
> +
> + &dmc {
> + rockchip,ddr-speed-bin = <DDR3_1600K>;
> + rockchip,ddr-frequency = <800000000>;
> + rockchip,memory-schedule = <DMC_MSCH_CBRD>;
> + };
> diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
> index c409c48..51ae6be 100644
> --- a/drivers/ram/Makefile
> +++ b/drivers/ram/Makefile
> @@ -8,3 +8,5 @@ obj-$(CONFIG_RAM) += ram-uclass.o
> obj-$(CONFIG_SANDBOX) += sandbox_ram.o
> obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o
> obj-$(CONFIG_ARCH_BMIPS) += bmips_ram.o
> +
> +obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
> diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile
> new file mode 100644
> index 0000000..b09d03c
> --- /dev/null
> +++ b/drivers/ram/rockchip/Makefile
> @@ -0,0 +1,7 @@
> +#
> +# Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +
> +obj-$(CONFIG_ROCKCHIP_RK3368) = dmc-rk3368.o
> diff --git a/drivers/ram/rockchip/dmc-rk3368.c b/drivers/ram/rockchip/dmc-rk3368.c
> new file mode 100644
> index 0000000..fea96a5
> --- /dev/null
> +++ b/drivers/ram/rockchip/dmc-rk3368.c
> @@ -0,0 +1,990 @@
> +/*
> + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + */
> +
> +#include <common.h>
> +#include <clk.h>
> +#include <dm.h>
> +#include <dt-bindings/memory/rk3368-dmc.h>
> +#include <dt-structs.h>
> +#include <ram.h>
> +#include <regmap.h>
> +#include <syscon.h>
> +#include <asm/io.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/cru_rk3368.h>
> +#include <asm/arch/grf_rk3368.h>
> +#include <asm/arch/ddr_rk3368.h>
> +#include <asm/arch/sdram.h>
> +#include <asm/arch/sdram_common.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct dram_info {
> + struct ram_info info;
> + struct clk ddr_clk;
> + struct rk3368_cru *cru;
> + struct rk3368_grf *grf;
> + struct rk3368_ddr_pctl *pctl;
> + struct rk3368_ddrphy *phy;
> + struct rk3368_pmu_grf *pmugrf;
> + struct rk3368_msch *msch;
> +};
> +
> +struct rk3368_sdram_params {
> +#if CONFIG_IS_ENABLED(OF_PLATDATA)
> + struct dtd_rockchip_rk3368_dmc of_plat;
> +#endif
> + struct rk3288_sdram_pctl_timing pctl_timing;
> + u32 trefi_mem_ddr3;
> + struct rk3288_sdram_channel chan;
> + struct regmap *map;
> + u32 ddr_freq;
> + u32 memory_schedule;
> + u32 ddr_speed_bin;
> + u32 tfaw_mult;
> +};
> +
> +/* PTCL bits */
> +enum {
> + /* PCTL_DFISTCFG0 */
> + DFI_INIT_START = BIT(0),
> + DFI_DATA_BYTE_DISABLE_EN = BIT(2),
> +
> + /* PCTL_DFISTCFG1 */
> + DFI_DRAM_CLK_SR_EN = BIT(0),
> + DFI_DRAM_CLK_DPD_EN = BIT(1),
> + ODT_LEN_BL8_W_SHIFT = 16,
> +
> + /* PCTL_DFISTCFG2 */
> + DFI_PARITY_INTR_EN = BIT(0),
> + DFI_PARITY_EN = BIT(1),
> +
> + /* PCTL_DFILPCFG0 */
> + TLP_RESP_TIME_SHIFT = 16,
> + LP_SR_EN = BIT(8),
> + LP_PD_EN = BIT(0),
> +
> + /* PCTL_DFIODTCFG */
> + RANK0_ODT_WRITE_SEL = BIT(3),
> + RANK1_ODT_WRITE_SEL = BIT(11),
> +
> + /* PCTL_SCFG */
> + HW_LOW_POWER_EN = BIT(0),
> +
> + /* PCTL_MCMD */
> + START_CMD = BIT(31),
> + MCMD_RANK0 = BIT(20),
> + MCMD_RANK1 = BIT(21),
> + DESELECT_CMD = 0,
> + PREA_CMD,
> + REF_CMD,
> + MRS_CMD,
> + ZQCS_CMD,
> + ZQCL_CMD,
> + RSTL_CMD,
> + MRR_CMD = 8,
> + DPDE_CMD,
> +
> + /* PCTL_POWCTL */
> + POWER_UP_START = BIT(0),
> +
> + /* PCTL_POWSTAT */
> + POWER_UP_DONE = BIT(0),
> +
> + /* PCTL_SCTL */
> + INIT_STATE = 0,
> + CFG_STATE,
> + GO_STATE,
> + SLEEP_STATE,
> + WAKEUP_STATE,
> +
> + /* PCTL_STAT */
> + LP_TRIG_SHIFT = 4,
> + LP_TRIG_MASK = 7,
> + PCTL_STAT_MSK = 7,
> + INIT_MEM = 0,
> + CONFIG,
> + CONFIG_REQ,
> + ACCESS,
> + ACCESS_REQ,
> + LOW_POWER,
> + LOW_POWER_ENTRY_REQ,
> + LOW_POWER_EXIT_REQ,
> +
> + /* PCTL_MCFG */
> + DDR2_DDR3_BL_8 = BIT(0),
> + DDR3_EN = BIT(5),
> + TFAW_TRRD_MULT4 = (0 << 18),
> + TFAW_TRRD_MULT5 = (1 << 18),
> + TFAW_TRRD_MULT6 = (2 << 18),
> +};
> +
> +#define DDR3_MR0_WR(n) \
> + ((n <= 8) ? ((n - 4) << 9) : (((n >> 1) & 0x7) << 9))
> +#define DDR3_MR0_CL(n) \
> + ((((n - 4) & 0x7) << 4) | (((n - 4) & 0x8) >> 2))
> +#define DDR3_MR0_BL8 \
> + (0 << 0)
> +#define DDR3_MR0_DLL_RESET \
> + (1 << 8)
> +#define DDR3_MR1_RTT120OHM \
> + ((0 << 9) | (1 << 6) | (0 << 2))
> +#define DDR3_MR2_TWL(n) \
> + (((n - 5) & 0x7) << 3)
> +
> +
> +#ifdef CONFIG_TPL_BUILD
> +
> +static void ddr_set_noc_spr_err_stall(struct rk3368_grf *grf, bool enable)
> +{
> + if (enable)
> + rk_setreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL);
> + else
> + rk_clrreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL);
> +}
> +
> +static void ddr_set_ddr3_mode(struct rk3368_grf *grf, bool ddr3_mode)
> +{
> + if (ddr3_mode)
> + rk_setreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3);
> + else
> + rk_clrreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3);
> +}
> +
> +static void ddrphy_config(struct rk3368_ddrphy *phy,
> + u32 tcl, u32 tal, u32 tcwl)
> +{
> + int i;
> +
> + /* Set to DDR3 mode */
> + clrsetbits_le32(&phy->reg[1], 0x3, 0x0);
> +
> + /* DDRPHY_REGB: CL, AL */
> + clrsetbits_le32(&phy->reg[0xb], 0xff, tcl << 4 | tal);
> + /* DDRPHY_REGC: CWL */
> + clrsetbits_le32(&phy->reg[0xc], 0x0f, tcwl);
> +
> + /* Update drive-strength */
> + writel(0xcc, &phy->reg[0x11]);
> + writel(0xaa, &phy->reg[0x16]);
> + /*
> + * Update NRCOMP/PRCOMP for all 4 channels (for details of all
> + * affected registers refer to the documentation of DDRPHY_REG20
> + * and DDRPHY_REG21 in the RK3368 TRM.
> + */
> + for (i = 0; i < 4; ++i) {
> + writel(0xcc, &phy->reg[0x20 + i * 0x10]);
> + writel(0x44, &phy->reg[0x21 + i * 0x10]);
> + }
> +
> + /* Enable write-leveling calibration bypass */
> + setbits_le32(&phy->reg[2], BIT(3));
> +}
> +
> +static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
> +{
> + int i;
> +
> + for (i = 0; i < n / sizeof(u32); i++)
> + writel(*src++, dest++);
> +}
> +
> +static void send_command(struct rk3368_ddr_pctl *pctl, u32 rank, u32 cmd)
> +{
> + u32 mcmd = START_CMD | cmd | rank;
> +
> + debug("%s: writing %x to MCMD\n", __func__, mcmd);
> + writel(mcmd, &pctl->mcmd);
> + while (readl(&pctl->mcmd) & START_CMD)
> + /* spin */;
> +}
> +
> +static void send_mrs(struct rk3368_ddr_pctl *pctl,
> + u32 rank, u32 mr_num, u32 mr_data)
> +{
> + u32 mcmd = START_CMD | MRS_CMD | rank | (mr_num << 17) | (mr_data << 4);
> +
> + debug("%s: writing %x to MCMD\n", __func__, mcmd);
> + writel(mcmd, &pctl->mcmd);
> + while (readl(&pctl->mcmd) & START_CMD)
> + /* spin */;
> +}
> +
> +static int memory_init(struct rk3368_ddr_pctl *pctl,
> + struct rk3368_sdram_params *params)
> +{
> + u32 mr[4];
> + const ulong timeout_ms = 500;
> + ulong tmp;
> +
> + /*
> + * Power up DRAM by DDR_PCTL_POWCTL[0] register of PCTL and
> + * wait power up DRAM finish with DDR_PCTL_POWSTAT[0] register
> + * of PCTL.
> + */
> + writel(POWER_UP_START, &pctl->powctl);
> +
> + tmp = get_timer(0);
> + do {
> + if (get_timer(tmp) > timeout_ms) {
> + error("%s: POWER_UP_START did not complete in %ld ms\n",
> + __func__, timeout_ms);
> + return -ETIME;
> + }
> + } while (!(readl(&pctl->powstat) & POWER_UP_DONE));
> +
> + /* Configure MR0 through MR3 */
> + mr[0] = DDR3_MR0_WR(params->pctl_timing.twr) |
> + DDR3_MR0_CL(params->pctl_timing.tcl) |
> + DDR3_MR0_DLL_RESET;
> + mr[1] = DDR3_MR1_RTT120OHM;
> + mr[2] = DDR3_MR2_TWL(params->pctl_timing.tcwl);
> + mr[3] = 0;
> +
> + /*
> + * Also see RK3368 Technical Reference Manual:
> + * "16.6.2 Initialization (DDR3 Initialization Sequence)"
> + */
> + send_command(pctl, MCMD_RANK0 | MCMD_RANK1, DESELECT_CMD);
> + udelay(1);
> + send_command(pctl, MCMD_RANK0 | MCMD_RANK1, PREA_CMD);
> + send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 2, mr[2]);
> + send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 3, mr[3]);
> + send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 1, mr[1]);
> + send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 0, mr[0]);
> + send_command(pctl, MCMD_RANK0 | MCMD_RANK1, ZQCL_CMD);
> +
> + return 0;
> +}
> +
> +static void move_to_config_state(struct rk3368_ddr_pctl *pctl)
> +{
> + /*
> + * Also see RK3368 Technical Reference Manual:
> + * "16.6.1 State transition of PCTL (Moving to Config State)"
> + */
> + u32 state = readl(&pctl->stat) & PCTL_STAT_MSK;
> +
> + switch (state) {
> + case LOW_POWER:
> + writel(WAKEUP_STATE, &pctl->sctl);
> + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
> + /* spin */;
> +
> + /* fall-through */
> + case ACCESS:
> + case INIT_MEM:
> + writel(CFG_STATE, &pctl->sctl);
> + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
> + /* spin */;
> + break;
> +
> + case CONFIG:
> + return;
> +
> + default:
> + break;
> + }
> +}
> +
> +static void move_to_access_state(struct rk3368_ddr_pctl *pctl)
> +{
> + /*
> + * Also see RK3368 Technical Reference Manual:
> + * "16.6.1 State transition of PCTL (Moving to Access State)"
> + */
> + u32 state = readl(&pctl->stat) & PCTL_STAT_MSK;
> +
> + switch (state) {
> + case LOW_POWER:
> + if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) &
> + LP_TRIG_MASK) == 1)
> + return;
> +
> + writel(WAKEUP_STATE, &pctl->sctl);
> + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
> + /* spin */;
> +
> + /* fall-through */
> + case INIT_MEM:
> + writel(CFG_STATE, &pctl->sctl);
> + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
> + /* spin */;
> +
> + /* fall-through */
> + case CONFIG:
> + writel(GO_STATE, &pctl->sctl);
> + while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG)
> + /* spin */;
> + break;
> +
> + case ACCESS:
> + return;
> +
> + default:
> + break;
> + }
> +}
> +
> +static void ddrctl_reset(struct rk3368_cru *cru)
> +{
> + const u32 ctl_reset = BIT(3) | BIT(2);
> + const u32 phy_reset = BIT(1) | BIT(0);
> +
> + rk_setreg(&cru->softrst_con[10], ctl_reset | phy_reset);
> + udelay(1);
> + rk_clrreg(&cru->softrst_con[10], ctl_reset | phy_reset);
> +}
> +
> +static void ddrphy_reset(struct rk3368_ddrphy *ddrphy)
> +{
> + clrbits_le32(&ddrphy->reg[0], BIT(3) | BIT(2));
> + udelay(1);
> + setbits_le32(&ddrphy->reg[0], BIT(3) | BIT(2));
> +}
> +
> +static void ddrphy_config_delays(struct rk3368_ddrphy *ddrphy, u32 freq)
> +{
> + u32 dqs_dll_delay;
> +
> + setbits_le32(&ddrphy->reg[0x13], BIT(4));
> + clrbits_le32(&ddrphy->reg[0x14], BIT(3));
> +
> + setbits_le32(&ddrphy->reg[0x26], BIT(4));
> + clrbits_le32(&ddrphy->reg[0x27], BIT(3));
> +
> + setbits_le32(&ddrphy->reg[0x36], BIT(4));
> + clrbits_le32(&ddrphy->reg[0x37], BIT(3));
> +
> + setbits_le32(&ddrphy->reg[0x46], BIT(4));
> + clrbits_le32(&ddrphy->reg[0x47], BIT(3));
> +
> + setbits_le32(&ddrphy->reg[0x56], BIT(4));
> + clrbits_le32(&ddrphy->reg[0x57], BIT(3));
> +
> + if (freq <= 400000000)
> + setbits_le32(&ddrphy->reg[0xa4], 0x1f);
> + else
> + clrbits_le32(&ddrphy->reg[0xa4], 0x1f);
> +
> + if (freq < 681000000)
> + dqs_dll_delay = 3; /* 67.5 degree delay */
> + else
> + dqs_dll_delay = 2; /* 45 degree delay */
> +
> + writel(dqs_dll_delay, &ddrphy->reg[0x28]);
> + writel(dqs_dll_delay, &ddrphy->reg[0x38]);
> + writel(dqs_dll_delay, &ddrphy->reg[0x48]);
> + writel(dqs_dll_delay, &ddrphy->reg[0x58]);
> +}
> +
> +static int dfi_cfg(struct rk3368_ddr_pctl *pctl)
> +{
> + const ulong timeout_ms = 200;
> + ulong tmp;
> +
> + writel(DFI_DATA_BYTE_DISABLE_EN, &pctl->dfistcfg0);
> +
> + writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN,
> + &pctl->dfistcfg1);
> + writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2);
> + writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN,
> + &pctl->dfilpcfg0);
> +
> + writel(1, &pctl->dfitphyupdtype0);
> +
> + writel(0x1f, &pctl->dfitphyrdlat);
> + writel(0, &pctl->dfitphywrdata);
> + writel(0, &pctl->dfiupdcfg); /* phyupd and ctrlupd disabled */
> +
> + setbits_le32(&pctl->dfistcfg0, DFI_INIT_START);
> +
> + tmp = get_timer(0);
> + do {
> + if (get_timer(tmp) > timeout_ms) {
> + error("%s: DFI init did not complete within %ld ms\n",
> + __func__, timeout_ms);
> + return -ETIME;
> + }
> + } while ((readl(&pctl->dfiststat0) & 1) == 0);
> +
> + return 0;
> +}
> +
> +static inline u32 ps_to_tCK(const u32 ps, const ulong freq)
> +{
> + const ulong MHz = 1000000;
> + return DIV_ROUND_UP(ps * freq, 1000000 * MHz);
> +}
> +
> +static inline u32 ns_to_tCK(const u32 ns, const ulong freq)
> +{
> + return ps_to_tCK(ns * 1000, freq);
> +}
> +
> +static inline u32 tCK_to_ps(const ulong tCK, const ulong freq)
> +{
> + const ulong MHz = 1000000;
> + return DIV_ROUND_UP(tCK * 1000000 * MHz, freq);
> +}
> +
> +static int pctl_calc_timings(struct rk3368_sdram_params *params,
> + ulong freq)
> +{
> + struct rk3288_sdram_pctl_timing *pctl_timing = ¶ms->pctl_timing;
> + const ulong MHz = 1000000;
> + u32 tccd;
> + u32 tfaw_as_ps;
> +
> + if (params->ddr_speed_bin != DDR3_1600K) {
> + error("%s: unimplemented DDR3 speed bin %d\n",
> + __func__, params->ddr_speed_bin);
> + return -1;
> + }
> +
> + /* PCTL is clocked at 1/2 the DRAM clock; err on the side of caution */
> + pctl_timing->togcnt1u = DIV_ROUND_UP(freq, 2 * MHz);
> + pctl_timing->togcnt100n = DIV_ROUND_UP(freq / 10, 2 * MHz);
> +
> + pctl_timing->tinit = 200; /* 200 usec */
> + pctl_timing->trsth = 500; /* 500 usec */
> + pctl_timing->trefi = 78; /* 7.8usec = 78 * 100ns */
> + params->trefi_mem_ddr3 = ns_to_tCK(pctl_timing->trefi * 100, freq);
> +
> + if (freq <= (400 * MHz)) {
> + pctl_timing->tcl = 6;
> + pctl_timing->tcwl = 10;
> + } else if (freq <= (533 * MHz)) {
> + pctl_timing->tcl = 8;
> + pctl_timing->tcwl = 6;
> + } else if (freq <= (666 * MHz)) {
> + pctl_timing->tcl = 10;
> + pctl_timing->tcwl = 7;
> + } else {
> + pctl_timing->tcl = 11;
> + pctl_timing->tcwl = 8;
> + }
> +
> + pctl_timing->tmrd = 4; /* 4 tCK (all speed bins) */
> + pctl_timing->trfc = ns_to_tCK(350, freq); /* tRFC: 350 (max) @ 8GBit */
> + pctl_timing->trp = max(4u, ps_to_tCK(13750, freq));
> + /*
> + * JESD-79:
> + * READ to WRITE Command Delay = RL + tCCD / 2 + 2tCK - WL
> + */
> + tccd = 4;
> + pctl_timing->trtw = pctl_timing->tcl + tccd/2 + 2 - pctl_timing->tcwl;
> + pctl_timing->tal = 0;
> + pctl_timing->tras = ps_to_tCK(35000, freq);
> + pctl_timing->trc = ps_to_tCK(48750, freq);
> + pctl_timing->trcd = ps_to_tCK(13750, freq);
> + pctl_timing->trrd = max(4u, ps_to_tCK(7500, freq));
> + pctl_timing->trtp = max(4u, ps_to_tCK(7500, freq));
> + pctl_timing->twr = ps_to_tCK(15000, freq);
> + /* The DDR3 mode-register does only support even values for tWR > 8. */
> + if (pctl_timing->twr > 8)
> + pctl_timing->twr = (pctl_timing->twr + 1) & ~1;
> + pctl_timing->twtr = max(4u, ps_to_tCK(7500, freq));
> + pctl_timing->texsr = 512; /* tEXSR(max) is tDLLLK */
> + pctl_timing->txp = max(3u, ps_to_tCK(6000, freq));
> + pctl_timing->txpdll = max(10u, ps_to_tCK(24000, freq));
> + pctl_timing->tzqcs = max(64u, ps_to_tCK(80000, freq));
> + pctl_timing->tzqcsi = 10000; /* as used by Rockchip */
> + pctl_timing->tdqs = 1; /* fixed for DDR3 */
> + pctl_timing->tcksre = max(5u, ps_to_tCK(10000, freq));
> + pctl_timing->tcksrx = max(5u, ps_to_tCK(10000, freq));
> + pctl_timing->tcke = max(3u, ps_to_tCK(5000, freq));
> + pctl_timing->tmod = max(12u, ps_to_tCK(15000, freq));
> + pctl_timing->trstl = ns_to_tCK(100, freq);
> + pctl_timing->tzqcl = max(256u, ps_to_tCK(320000, freq)); /* tZQoper */
> + pctl_timing->tmrr = 0;
> + pctl_timing->tckesr = pctl_timing->tcke + 1; /* JESD-79: tCKE + 1tCK */
> + pctl_timing->tdpd = 0; /* RK3368 TRM: "allowed values for DDR3: 0" */
> +
> +
> + /*
> + * The controller can represent tFAW as 4x, 5x or 6x tRRD only.
> + * We want to use the smallest multiplier that satisfies the tFAW
> + * requirements of the given speed-bin. If necessary, we stretch out
> + * tRRD to allow us to operate on a 6x multiplier for tFAW.
> + */
> + tfaw_as_ps = 40000; /* 40ns: tFAW for DDR3-1600K, 2KB page-size */
> + if (tCK_to_ps(pctl_timing->trrd * 6, freq) < tfaw_as_ps) {
> + /* If tFAW is > 6 x tRRD, we need to stretch tRRD */
> + pctl_timing->trrd = ps_to_tCK(DIV_ROUND_UP(40000, 6), freq);
> + params->tfaw_mult = TFAW_TRRD_MULT6;
> + } else if (tCK_to_ps(pctl_timing->trrd * 5, freq) < tfaw_as_ps) {
> + params->tfaw_mult = TFAW_TRRD_MULT6;
> + } else if (tCK_to_ps(pctl_timing->trrd * 4, freq) < tfaw_as_ps) {
> + params->tfaw_mult = TFAW_TRRD_MULT5;
> + } else {
> + params->tfaw_mult = TFAW_TRRD_MULT4;
> + }
> +
> + return 0;
> +}
> +
> +static void pctl_cfg(struct rk3368_ddr_pctl *pctl,
> + struct rk3368_sdram_params *params,
> + struct rk3368_grf *grf)
> +{
> + /* Configure PCTL timing registers */
> + params->pctl_timing.trefi |= BIT(31); /* see PCTL_TREFI */
> + copy_to_reg(&pctl->togcnt1u, ¶ms->pctl_timing.togcnt1u,
> + sizeof(params->pctl_timing));
> + writel(params->trefi_mem_ddr3, &pctl->trefi_mem_ddr3);
> +
> + /* Set up ODT write selector and ODT write length */
> + writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL), &pctl->dfiodtcfg);
> + writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1);
> +
> + /* Set up the CL/CWL-dependent timings of DFI */
> + writel((params->pctl_timing.tcl - 1) / 2 - 1, &pctl->dfitrddataen);
> + writel((params->pctl_timing.tcwl - 1) / 2 - 1, &pctl->dfitphywrlat);
> +
> + /* DDR3 */
> + writel(params->tfaw_mult | DDR3_EN | DDR2_DDR3_BL_8, &pctl->mcfg);
> + writel(0x001c0004, &grf->ddrc0_con0);
> +
> + setbits_le32(&pctl->scfg, HW_LOW_POWER_EN);
> +}
> +
> +static int ddrphy_data_training(struct rk3368_ddr_pctl *pctl,
> + struct rk3368_ddrphy *ddrphy)
> +{
> + const u32 trefi = readl(&pctl->trefi);
> + const ulong timeout_ms = 500;
> + ulong tmp;
> +
> + /* disable auto-refresh */
> + writel(0 | BIT(31), &pctl->trefi);
> +
> + clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x20);
> + clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x21);
> +
> + tmp = get_timer(0);
> + do {
> + if (get_timer(tmp) > timeout_ms) {
> + error("%s: did not complete within %ld ms\n",
> + __func__, timeout_ms);
> + return -ETIME;
> + }
> + } while ((readl(&ddrphy->reg[0xff]) & 0xf) != 0xf);
> +
> + send_command(pctl, MCMD_RANK0 | MCMD_RANK1, PREA_CMD);
> + clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x20);
> + /* resume auto-refresh */
> + writel(trefi | BIT(31), &pctl->trefi);
> +
> + return 0;
> +}
> +
> +static int sdram_col_row_detect(struct udevice *dev)
> +{
> + struct dram_info *priv = dev_get_priv(dev);
> + struct rk3368_sdram_params *params = dev_get_platdata(dev);
> + struct rk3368_ddr_pctl *pctl = priv->pctl;
> + struct rk3368_msch *msch = priv->msch;
> + const u32 test_pattern = 0x5aa5f00f;
> + int row, col;
> + uintptr_t addr;
> +
> + move_to_config_state(pctl);
> + writel(6, &msch->ddrconf);
> + move_to_access_state(pctl);
> +
> + /* Detect col */
> + for (col = 11; col >= 9; col--) {
> + writel(0, CONFIG_SYS_SDRAM_BASE);
> + addr = CONFIG_SYS_SDRAM_BASE +
> + (1 << (col + params->chan.bw - 1));
> + writel(test_pattern, addr);
> + if ((readl(addr) == test_pattern) &&
> + (readl(CONFIG_SYS_SDRAM_BASE) == 0))
> + break;
> + }
> +
> + if (col == 8) {
> + error("%s: col detect error\n", __func__);
> + return -EINVAL;
> + }
> +
> + move_to_config_state(pctl);
> + writel(15, &msch->ddrconf);
> + move_to_access_state(pctl);
> +
> + /* Detect row*/
> + for (row = 16; row >= 12; row--) {
> + writel(0, CONFIG_SYS_SDRAM_BASE);
> + addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
> + writel(test_pattern, addr);
> + if ((readl(addr) == test_pattern) &&
> + (readl(CONFIG_SYS_SDRAM_BASE) == 0))
> + break;
> + }
> +
> + if (row == 11) {
> + error("%s: row detect error\n", __func__);
> + return -EINVAL;
> + }
> +
> + /* Record results */
> + debug("%s: col %d, row %d\n", __func__, col, row);
> + params->chan.col = col;
> + params->chan.cs0_row = row;
> + params->chan.cs1_row = row;
> + params->chan.row_3_4 = 0;
> +
> + return 0;
> +}
> +
> +static int msch_niu_config(struct rk3368_msch *msch,
> + struct rk3368_sdram_params *params)
> +{
> + int i;
> + const u8 cols = params->chan.col - ((params->chan.bw == 2) ? 0 : 1);
> + const u8 rows = params->chan.cs0_row;
> +
> + /*
> + * The DDR address-translation table always assumes a 32bit
> + * bus and the comparison below takes care of adjusting for
> + * a 16bit bus (i.e. one column-address is consumed).
> + */
> + const struct {
> + u8 rows;
> + u8 columns;
> + u8 type;
> + } ddrconf_table[] = {
> + /*
> + * C-B-R-D patterns are first. For these we require an
> + * exact match for the columns and rows (as there's
> + * one entry per possible configuration).
> + */
> + [0] = { .rows = 13, .columns = 10, .type = DMC_MSCH_CBRD },
> + [1] = { .rows = 14, .columns = 10, .type = DMC_MSCH_CBRD },
> + [2] = { .rows = 15, .columns = 10, .type = DMC_MSCH_CBRD },
> + [3] = { .rows = 16, .columns = 10, .type = DMC_MSCH_CBRD },
> + [4] = { .rows = 14, .columns = 11, .type = DMC_MSCH_CBRD },
> + [5] = { .rows = 15, .columns = 11, .type = DMC_MSCH_CBRD },
> + [6] = { .rows = 16, .columns = 11, .type = DMC_MSCH_CBRD },
> + [7] = { .rows = 13, .columns = 9, .type = DMC_MSCH_CBRD },
> + [8] = { .rows = 14, .columns = 9, .type = DMC_MSCH_CBRD },
> + [9] = { .rows = 15, .columns = 9, .type = DMC_MSCH_CBRD },
> + [10] = { .rows = 16, .columns = 9, .type = DMC_MSCH_CBRD },
> + /*
> + * 11 through 13 are C-R-B-D patterns. These are
> + * matched for an exact number of columns and to
> + * ensure that the hardware uses at least as many rows
> + * as the pattern requires (i.e. we make sure that
> + * there's no gaps up until we hit the device/chip-select;
> + * however, these patterns can accept up to 16 rows,
> + * as the row-address continues right after the CS
> + * switching)
> + */
> + [11] = { .rows = 15, .columns = 10, .type = DMC_MSCH_CRBD },
> + [12] = { .rows = 14, .columns = 11, .type = DMC_MSCH_CRBD },
> + [13] = { .rows = 13, .columns = 10, .type = DMC_MSCH_CRBD },
> + /*
> + * 14 and 15 are catch-all variants using a C-B-D-R
> + * scheme (i.e. alternating the chip-select every time
> + * C-B overflows) and stuffing the remaining C-bits
> + * into the top. Matching needs to make sure that the
> + * number of columns is either an exact match (i.e. we
> + * can use less the the maximum number of rows) -or-
> + * that the columns exceed what is given in this table
> + * and the rows are an exact match (in which case the
> + * remaining C-bits will be stuffed onto the top after
> + * the device/chip-select switches).
> + */
> + [14] = { .rows = 16, .columns = 10, .type = DMC_MSCH_CBDR },
> + [15] = { .rows = 16, .columns = 9, .type = DMC_MSCH_CBDR },
> + };
> +
> + /*
> + * For C-B-R-D, we need an exact match (i.e. both for the number of
> + * columns and rows), while for C-B-D-R, only the the number of
> + * columns needs to match.
> + */
> + for (i = 0; i < ARRAY_SIZE(ddrconf_table); i++) {
> + bool match = false;
> +
> + /* If this entry if for a different matcher, then skip it */
> + if (ddrconf_table[i].type != params->memory_schedule)
> + continue;
> +
> + /*
> + * Match according to the rules (exact/inexact/at-least)
> + * documented in the ddrconf_table above.
> + */
> + switch (params->memory_schedule) {
> + case DMC_MSCH_CBRD:
> + match = (ddrconf_table[i].columns == cols) &&
> + (ddrconf_table[i].rows == rows);
> + break;
> +
> + case DMC_MSCH_CRBD:
> + match = (ddrconf_table[i].columns == cols) &&
> + (ddrconf_table[i].rows <= rows);
> + break;
> +
> + case DMC_MSCH_CBDR:
> + match = (ddrconf_table[i].columns == cols) ||
> + ((ddrconf_table[i].columns <= cols) &&
> + (ddrconf_table[i].rows == rows));
> + break;
> +
> + default:
> + break;
> + }
> +
> + if (match) {
> + debug("%s: setting ddrconf 0x%x\n", __func__, i);
> + writel(i, &msch->ddrconf);
> + return 0;
> + }
> + }
> +
> + error("%s: ddrconf (NIU config) not found\n", __func__);
> + return -EINVAL;
> +}
> +
> +static void dram_all_config(struct udevice *dev)
> +{
> + struct dram_info *priv = dev_get_priv(dev);
> + struct rk3368_pmu_grf *pmugrf = priv->pmugrf;
> + struct rk3368_sdram_params *params = dev_get_platdata(dev);
> + const struct rk3288_sdram_channel *info = ¶ms->chan;
> + u32 sys_reg = 0;
> + const int chan = 0;
> +
> + sys_reg |= DDR3 << SYS_REG_DDRTYPE_SHIFT;
> + sys_reg |= 0 << SYS_REG_NUM_CH_SHIFT;
> +
> + sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan);
> + sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan);
> + sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan);
> + sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan);
> + sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan);
> + sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan);
> + sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan);
> + sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan);
> + sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan);
> +
> + writel(sys_reg, &pmugrf->os_reg[2]);
> +}
> +
> +static int setup_sdram(struct udevice *dev)
> +{
> + struct dram_info *priv = dev_get_priv(dev);
> + struct rk3368_sdram_params *params = dev_get_platdata(dev);
> +
> + struct rk3368_ddr_pctl *pctl = priv->pctl;
> + struct rk3368_ddrphy *ddrphy = priv->phy;
> + struct rk3368_cru *cru = priv->cru;
> + struct rk3368_grf *grf = priv->grf;
> + struct rk3368_msch *msch = priv->msch;
> +
> + int ret;
> +
> + /* The input clock (i.e. DPLL) needs to be 2x the DRAM frequency */
> + ret = clk_set_rate(&priv->ddr_clk, 2 * params->ddr_freq);
> + if (ret < 0) {
> + debug("%s: could not set DDR clock: %d\n", __func__, ret);
> + return ret;
> + }
> +
> + /* Update the read-latency for the RK3368 */
> + writel(0x32, &msch->readlatency);
> +
> + /* Initialise the DDR PCTL and DDR PHY */
> + ddrctl_reset(cru);
> + ddrphy_reset(ddrphy);
> + ddrphy_config_delays(ddrphy, params->ddr_freq);
> + dfi_cfg(pctl);
> + /* Configure relative system information of grf_ddrc0_con0 register */
> + ddr_set_ddr3_mode(grf, true);
> + ddr_set_noc_spr_err_stall(grf, true);
> + /* Calculate timings */
> + pctl_calc_timings(params, params->ddr_freq);
> + /* Initialise the device timings in protocol controller */
> + pctl_cfg(pctl, params, grf);
> + /* Configure AL, CL ... information of PHY registers */
> + ddrphy_config(ddrphy,
> + params->pctl_timing.tcl,
> + params->pctl_timing.tal,
> + params->pctl_timing.tcwl);
> +
> + /* Initialize DRAM and configure with mode-register values */
> + ret = memory_init(pctl, params);
> + if (ret)
> + goto error;
> +
> + move_to_config_state(pctl);
> + /* Perform data-training */
> + ddrphy_data_training(pctl, ddrphy);
> + move_to_access_state(pctl);
> +
> + /* TODO(prt): could detect rank in training... */
> + params->chan.rank = 2;
> + /* TODO(prt): bus width is not auto-detected (yet)... */
> + params->chan.bw = 2; /* 32bit wide bus */
> + params->chan.dbw = params->chan.dbw; /* 32bit wide bus */
> +
> + /* DDR3 is always 8 bank */
> + params->chan.bk = 3;
> + /* Detect col and row number */
> + ret = sdram_col_row_detect(dev);
> + if (ret)
> + goto error;
> +
> + /* Configure NIU DDR configuration */
> + ret = msch_niu_config(msch, params);
> + if (ret)
> + goto error;
> +
> + /* set up OS_REG to communicate w/ next stage and OS */
> + dram_all_config(dev);
> +
> + return 0;
> +
> +error:
> + printf("DRAM init failed!\n");
> + hang();
> +}
> +#endif
> +
> +static int rk3368_dmc_ofdata_to_platdata(struct udevice *dev)
> +{
> + int ret = 0;
> +
> +#if !CONFIG_IS_ENABLED(OF_PLATDATA)
> + struct rk3368_sdram_params *plat = dev_get_platdata(dev);
> +
> + ret = regmap_init_mem(dev, &plat->map);
> + if (ret)
> + return ret;
> +#endif
> +
> + return ret;
> +}
> +
> +#if CONFIG_IS_ENABLED(OF_PLATDATA)
> +static int conv_of_platdata(struct udevice *dev)
> +{
> + struct rk3368_sdram_params *plat = dev_get_platdata(dev);
> + struct dtd_rockchip_rk3368_dmc *of_plat = &plat->of_plat;
> + int ret;
> +
> + plat->ddr_freq = of_plat->rockchip_ddr_frequency;
> + plat->ddr_speed_bin = of_plat->rockchip_ddr_speed_bin;
> + plat->memory_schedule = of_plat->rockchip_memory_schedule;
> +
> + ret = regmap_init_mem_platdata(dev, of_plat->reg,
> + ARRAY_SIZE(of_plat->reg) / 2,
> + &plat->map);
> + if (ret)
> + return ret;
> +
> + return 0;
> +}
> +#endif
> +
> +static int rk3368_dmc_probe(struct udevice *dev)
> +{
> +#ifdef CONFIG_TPL_BUILD
> + struct rk3368_sdram_params *plat = dev_get_platdata(dev);
> + struct rk3368_ddr_pctl *pctl;
> + struct rk3368_ddrphy *ddrphy;
> + struct rk3368_cru *cru;
> + struct rk3368_grf *grf;
> + struct rk3368_msch *msch;
> + int ret;
> + struct udevice *dev_clk;
> +#endif
> + struct dram_info *priv = dev_get_priv(dev);
> +
> +#if CONFIG_IS_ENABLED(OF_PLATDATA)
> + ret = conv_of_platdata(dev);
> + if (ret)
> + return ret;
> +#endif
> +
> + priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
> + debug("%s: pmugrf=%p\n", __func__, priv->pmugrf);
> +
> +#ifdef CONFIG_TPL_BUILD
> + pctl = regmap_get_range(plat->map, 0);
> + ddrphy = regmap_get_range(plat->map, 1);
> + msch = syscon_get_first_range(ROCKCHIP_SYSCON_MSCH);
> + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
> +
> + priv->pctl = pctl;
> + priv->phy = ddrphy;
> + priv->msch = msch;
> + priv->grf = grf;
> +
> + ret = rockchip_get_clk(&dev_clk);
> + if (ret)
> + return ret;
> + priv->ddr_clk.id = CLK_DDR;
> + ret = clk_request(dev_clk, &priv->ddr_clk);
> + if (ret)
> + return ret;
> +
> + cru = rockchip_get_cru();
> + priv->cru = cru;
> + if (IS_ERR(priv->cru))
> + return PTR_ERR(priv->cru);
> +
> + ret = setup_sdram(dev);
> + if (ret)
> + return ret;
> +#endif
> +
> + priv->info.base = 0;
> + priv->info.size =
> + rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg[2]);
> +
> + /*
> + * we use the 0x00000000~0xfdffffff space since 0xff000000~0xffffffff
> + * is SoC register space (i.e. reserved), and 0xfe000000~0xfeffffff is
> + * inaccessible for some IP controller.
> + */
> + priv->info.size = min(priv->info.size, (size_t)0xfe000000);
> +
> + return 0;
> +}
> +
> +static int rk3368_dmc_get_info(struct udevice *dev, struct ram_info *info)
> +{
> + struct dram_info *priv = dev_get_priv(dev);
> +
> + *info = priv->info;
> + return 0;
> +}
> +
> +static struct ram_ops rk3368_dmc_ops = {
> + .get_info = rk3368_dmc_get_info,
> +};
> +
> +
> +static const struct udevice_id rk3368_dmc_ids[] = {
> + { .compatible = "rockchip,rk3368-dmc" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(dmc_rk3368) = {
> + .name = "rockchip_rk3368_dmc",
> + .id = UCLASS_RAM,
> + .of_match = rk3368_dmc_ids,
> + .ops = &rk3368_dmc_ops,
> + .probe = rk3368_dmc_probe,
> + .priv_auto_alloc_size = sizeof(struct dram_info),
> + .ofdata_to_platdata = rk3368_dmc_ofdata_to_platdata,
> + .probe = rk3368_dmc_probe,
> + .priv_auto_alloc_size = sizeof(struct dram_info),
> + .platdata_auto_alloc_size = sizeof(struct rk3368_sdram_params),
> +};
> diff --git a/include/dt-bindings/memory/rk3368-dmc.h b/include/dt-bindings/memory/rk3368-dmc.h
> new file mode 100644
> index 0000000..b06ffde
> --- /dev/null
> +++ b/include/dt-bindings/memory/rk3368-dmc.h
> @@ -0,0 +1,30 @@
> +#ifndef DT_BINDINGS_RK3368_DMC_H
> +#define DT_BINDINGS_RK3368_DMC_H
> +
> +#define DMC_MSCH_CBDR 0x0
> +#define DMC_MSCH_CBRD 0x1
> +#define DMC_MSCH_CRBD 0x2
> +
> +#define DDR3_800D 0
> +#define DDR3_800E 1
> +#define DDR3_1066E 2
> +#define DDR3_1066F 3
> +#define DDR3_1066G 4
> +#define DDR3_1333F 5
> +#define DDR3_1333G 6
> +#define DDR3_1333H 7
> +#define DDR3_1333J 8
> +#define DDR3_1600G 9
> +#define DDR3_1600H 10
> +#define DDR3_1600J 11
> +#define DDR3_1600K 12
> +#define DDR3_1866J 13
> +#define DDR3_1866K 14
> +#define DDR3_1866L 15
> +#define DDR3_1866M 16
> +#define DDR3_2133K 17
> +#define DDR3_2133L 18
> +#define DDR3_2133M 19
> +#define DDR3_2133N 20
> +
> +#endif
^ permalink raw reply related [flat|nested] 95+ messages in thread
* [U-Boot] [PATCH v3 50/66] rockchip: rk3368: add DRAM controller driver with DRAM initialisation
2017-07-28 19:22 ` [U-Boot] [PATCH v3 50/66] rockchip: rk3368: add DRAM controller driver with DRAM initialisation Philipp Tomsich
2017-08-01 1:30 ` Andy Yan
@ 2017-08-02 10:06 ` Andy Yan
2017-08-02 10:59 ` Dr. Philipp Tomsich
1 sibling, 1 reply; 95+ messages in thread
From: Andy Yan @ 2017-08-02 10:06 UTC (permalink / raw)
To: u-boot
Hi Philipp:
On 2017年07月29日 03:22, Philipp Tomsich wrote:
> This adds a DRAM controller driver for the RK3368 and places it in
> drivers/ram/rockchip (where the other DM-enabled DRAM controller
> drivers for rockchip devices should also be moved eventually).
>
> At this stage, only the following feature-set is supported:
> - DDR3
> - 32-bit configuration (i.e. fully populated)
> - dual-rank (i.e. no auto-detection of ranks)
> - DDR3-1600K speed-bin
>
> This driver expects to run from a TPL stage that will later return to
> the RK3368 BROM. It communicates with later stages through the
> os_reg2 in the pmugrf (i.e. using the same mechanism as Rockchip's DDR
> init code).
>
> Unlike other DMC drivers for RK32xx and RK33xx parts, the required
> timings are calculated within the driver based on a target frequency
> and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this
> time).
>
> The RK3368 also has the DDRC0_CON0 (DDR ch. 0, control-register 0)
> register for controlling the operation of its (single-channel) DRAM
> controller in the GRF block. This provides for selecting DDR3, mobile
> DDR modes, and control low-power operation.
> As part of this change, DDRC0_CON0 is also added to the GRF structure
> definition (at offset 0x600).
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v3:
> - correctly states the location of the driver in the commit message
>
> Changes in v2: None
>
> arch/arm/include/asm/arch-rockchip/ddr_rk3368.h | 187 ++++
> arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 3 +
> arch/arm/mach-rockchip/rk3368/Makefile | 1 -
> arch/arm/mach-rockchip/rk3368/sdram_rk3368.c | 60 --
> .../clock/rockchip,rk3368-dmc.txt | 67 ++
> drivers/ram/Makefile | 2 +
> drivers/ram/rockchip/Makefile | 7 +
> drivers/ram/rockchip/dmc-rk3368.c | 990 +++++++++++++++++++++
> include/dt-bindings/memory/rk3368-dmc.h | 30 +
> 9 files changed, 1286 insertions(+), 61 deletions(-)
> create mode 100644 arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
> delete mode 100644 arch/arm/mach-rockchip/rk3368/sdram_rk3368.c
> create mode 100644 doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt
> create mode 100644 drivers/ram/rockchip/Makefile
> create mode 100644 drivers/ram/rockchip/dmc-rk3368.c
> create mode 100644 include/dt-bindings/memory/rk3368-dmc.h
>
> diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h b/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
> new file mode 100644
> index 0000000..4e2b233
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
> @@ -0,0 +1,187 @@
> +/*
> + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + */
> +
> +#ifndef __ASM_ARCH_DDR_RK3368_H__
> +#define __ASM_ARCH_DDR_RK3368_H__
> +
> +/*
> + * The RK3368 DDR PCTL differs from the incarnation in the RK3288 only
> + * in a few details. Most notably, it has an additional field to track
> + * tREFI in controller cycles (i.e. trefi_mem_ddr3).
> + */
> +struct rk3368_ddr_pctl {
> + u32 scfg;
> + u32 sctl;
> + u32 stat;
> + u32 intrstat;
> + u32 reserved0[12];
> + u32 mcmd;
> + u32 powctl;
> + u32 powstat;
> + u32 cmdtstat;
> + u32 cmdtstaten;
> + u32 reserved1[3];
> + u32 mrrcfg0;
> + u32 mrrstat0;
> + u32 mrrstat1;
> + u32 reserved2[4];
> + u32 mcfg1;
> + u32 mcfg;
> + u32 ppcfg;
> + u32 mstat;
> + u32 lpddr2zqcfg;
> + u32 reserved3;
> + u32 dtupdes;
> + u32 dtuna;
> + u32 dtune;
> + u32 dtuprd0;
> + u32 dtuprd1;
> + u32 dtuprd2;
> + u32 dtuprd3;
> + u32 dtuawdt;
> + u32 reserved4[3];
> + u32 togcnt1u;
> + u32 tinit;
> + u32 trsth;
> + u32 togcnt100n;
> + u32 trefi;
> + u32 tmrd;
> + u32 trfc;
> + u32 trp;
> + u32 trtw;
> + u32 tal;
> + u32 tcl;
> + u32 tcwl;
> + u32 tras;
> + u32 trc;
> + u32 trcd;
> + u32 trrd;
> + u32 trtp;
> + u32 twr;
> + u32 twtr;
> + u32 texsr;
> + u32 txp;
> + u32 txpdll;
> + u32 tzqcs;
> + u32 tzqcsi;
> + u32 tdqs;
> + u32 tcksre;
> + u32 tcksrx;
> + u32 tcke;
> + u32 tmod;
> + u32 trstl;
> + u32 tzqcl;
> + u32 tmrr;
> + u32 tckesr;
> + u32 t
>
> Hi Philipp:
>
>
> On 2017年07月29日 03:22, Philipp Tomsich wrote:
>> This adds a DRAM controller driver for the RK3368 and places it in
>> drivers/ram/rockchip (where the other DM-enabled DRAM controller
>> drivers for rockchip devices should also be moved eventually).
>>
>> At this stage, only the following feature-set is supported:
>> - DDR3
>> - 32-bit configuration (i.e. fully populated)
>> - dual-rank (i.e. no auto-detection of ranks)
>> - DDR3-1600K speed-bin
>>
>> This driver expects to run from a TPL stage that will later return to
>> the RK3368 BROM. It communicates with later stages through the
>> os_reg2 in the pmugrf (i.e. using the same mechanism as Rockchip's DDR
>> init code).
>>
>> Unlike other DMC drivers for RK32xx and RK33xx parts, the required
>> timings are calculated within the driver based on a target frequency
>> and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this
>> time).
>>
>> The RK3368 also has the DDRC0_CON0 (DDR ch. 0, control-register 0)
>> register for controlling the operation of its (single-channel) DRAM
>> controller in the GRF block. This provides for selecting DDR3, mobile
>> DDR modes, and control low-power operation.
>> As part of this change, DDRC0_CON0 is also added to the GRF structure
>> definition (at offset 0x600).
>>
>> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>>
>> Reviewed-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> Changes in v3:
>> - correctly states the location of the driver in the commit message
>>
>> Changes in v2: None
>>
>> arch/arm/include/asm/arch-rockchip/ddr_rk3368.h | 187 ++++
>> arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 3 +
>> arch/arm/mach-rockchip/rk3368/Makefile | 1 -
>> arch/arm/mach-rockchip/rk3368/sdram_rk3368.c | 60 --
>> .../clock/rockchip,rk3368-dmc.txt | 67 ++
>> drivers/ram/Makefile | 2 +
>> drivers/ram/rockchip/Makefile | 7 +
>> drivers/ram/rockchip/dmc-rk3368.c | 990 +++++++++++++++++++++
>> include/dt-bindings/memory/rk3368-dmc.h | 30 +
>> 9 files changed, 1286 insertions(+), 61 deletions(-)
>> create mode 100644 arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
>> delete mode 100644 arch/arm/mach-rockchip/rk3368/sdram_rk3368.c
>> create mode 100644 doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt
>> create mode 100644 drivers/ram/rockchip/Makefile
>> create mode 100644 drivers/ram/rockchip/dmc-rk3368.c
>> create mode 100644 include/dt-bindings/memory/rk3368-dmc.h
>>
>> diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h b/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
>> new file mode 100644
>> index 0000000..4e2b233
>> --- /dev/null
>> +++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
>> @@ -0,0 +1,187 @@
>> +/*
>> + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
>> + *
>> + * SPDX-License-Identifier: GPL-2.0
>> + */
>> +
>> +#ifndef __ASM_ARCH_DDR_RK3368_H__
>> +#define __ASM_ARCH_DDR_RK3368_H__
>> +
>> +/*
>> + * The RK3368 DDR PCTL differs from the incarnation in the RK3288 only
>> + * in a few details. Most notably, it has an additional field to track
>> + * tREFI in controller cycles (i.e. trefi_mem_ddr3).
>> + */
>> +struct rk3368_ddr_pctl {
>> + u32 scfg;
>> + u32 sctl;
>> + u32 stat;
>> + u32 intrstat;
>> + u32 reserved0[12];
>> + u32 mcmd;
>> + u32 powctl;
>> + u32 powstat;
>> + u32 cmdtstat;
>> + u32 cmdtstaten;
>> + u32 reserved1[3];
>> + u32 mrrcfg0;
>> + u32 mrrstat0;
>> + u32 mrrstat1;
>> + u32 reserved2[4];
>> + u32 mcfg1;
>> + u32 mcfg;
>> + u32 ppcfg;
>> + u32 mstat;
>> + u32 lpddr2zqcfg;
>> + u32 reserved3;
>> + u32 dtupdes;
>> + u32 dtuna;
>> + u32 dtune;
>> + u32 dtuprd0;
>> + u32 dtuprd1;
>> + u32 dtuprd2;
>> + u32 dtuprd3;
>> + u32 dtuawdt;
>> + u32 reserved4[3];
>> + u32 togcnt1u;
>> + u32 tinit;
>> + u32 trsth;
>> + u32 togcnt100n;
>> + u32 trefi;
>> + u32 tmrd;
>> + u32 trfc;
>> + u32 trp;
>> + u32 trtw;
>> + u32 tal;
>> + u32 tcl;
>> + u32 tcwl;
>> + u32 tras;
>> + u32 trc;
>> + u32 trcd;
>> + u32 trrd;
>> + u32 trtp;
>> + u32 twr;
>> + u32 twtr;
>> + u32 texsr;
>> + u32 txp;
>> + u32 txpdll;
>> + u32 tzqcs;
>> + u32 tzqcsi;
>> + u32 tdqs;
>> + u32 tcksre;
>> + u32 tcksrx;
>> + u32 tcke;
>> + u32 tmod;
>> + u32 trstl;
>> + u32 tzqcl;
>> + u32 tmrr;
>> + u32 tckesr;
>> + u32 tdpd;
>> + u32 trefi_mem_ddr3;
>> + u32 reserved5[45];
>> + u32 dtuwactl;
>> + u32 dturactl;
>> + u32 dtucfg;
>> + u32 dtuectl;
>> + u32 dtuwd0;
>> + u32 dtuwd1;
>> + u32 dtuwd2;
>> + u32 dtuwd3;
>> + u32 dtuwdm;
>> + u32 dturd0;
>> + u32 dturd1;
>> + u32 dturd2;
>> + u32 dturd3;
>> + u32 dtulfsrwd;
>> + u32 dtulfsrrd;
>> + u32 dtueaf;
>> + u32 dfitctrldelay;
>> + u32 dfiodtcfg;
>> + u32 dfiodtcfg1;
>> + u32 dfiodtrankmap;
>> + u32 dfitphywrdata;
>> + u32 dfitphywrlat;
>> + u32 reserved7[2];
>> + u32 dfitrddataen;
>> + u32 dfitphyrdlat;
>> + u32 reserved8[2];
>> + u32 dfitphyupdtype0;
>> + u32 dfitphyupdtype1;
>> + u32 dfitphyupdtype2;
>> + u32 dfitphyupdtype3;
>> + u32 dfitctrlupdmin;
>> + u32 dfitctrlupdmax;
>> + u32 dfitctrlupddly;
>> + u32 reserved9;
>> + u32 dfiupdcfg;
>> + u32 dfitrefmski;
>> + u32 dfitctrlupdi;
>> + u32 reserved10[4];
>> + u32 dfitrcfg0;
>> + u32 dfitrstat0;
>> + u32 dfitrwrlvlen;
>> + u32 dfitrrdlvlen;
>> + u32 dfitrrdlvlgateen;
>> + u32 dfiststat0;
>> + u32 dfistcfg0;
>> + u32 dfistcfg1;
>> + u32 reserved11;
>> + u32 dfitdramclken;
>> + u32 dfitdramclkdis;
>> + u32 dfistcfg2;
>> + u32 dfistparclr;
>> + u32 dfistparlog;
>> + u32 reserved12[3];
>> + u32 dfilpcfg0;
>> + u32 reserved13[3];
>> + u32 dfitrwrlvlresp0;
>> + u32 dfitrwrlvlresp1;
>> + u32 dfitrwrlvlresp2;
>> + u32 dfitrrdlvlresp0;
>> + u32 dfitrrdlvlresp1;
>> + u32 dfitrrdlvlresp2;
>> + u32 dfitrwrlvldelay0;
>> + u32 dfitrwrlvldelay1;
>> + u32 dfitrwrlvldelay2;
>> + u32 dfitrrdlvldelay0;
>> + u32 dfitrrdlvldelay1;
>> + u32 dfitrrdlvldelay2;
>> + u32 dfitrrdlvlgatedelay0;
>> + u32 dfitrrdlvlgatedelay1;
>> + u32 dfitrrdlvlgatedelay2;
>> + u32 dfitrcmd;
>> + u32 reserved14[46];
>> + u32 ipvr;
>> + u32 iptr;
>> +};
>> +check_member(rk3368_ddr_pctl, iptr, 0x03fc);
>> +
>> +struct rk3368_ddrphy {
>> + u32 reg[0x100];
>> +};
>> +check_member(rk3368_ddrphy, reg[0xff], 0x03fc);
>> +
>> +struct rk3368_msch {
>> + u32 coreid;
>> + u32 revisionid;
>> + u32 ddrconf;
>> + u32 ddrtiming;
>> + u32 ddrmode;
>> + u32 readlatency;
>> + u32 reserved1[8];
>> + u32 activate;
>> + u32 devtodev;
>> +};
>> +check_member(rk3368_msch, devtodev, 0x003c);
>> +
>> +/* GRF_SOC_CON0 */
>> +enum {
>> + NOC_RSP_ERR_STALL = BIT(9),
>> + MOBILE_DDR_SEL = BIT(4),
>> + DDR0_16BIT_EN = BIT(3),
>> + MSCH0_MAINDDR3_DDR3 = BIT(2),
>> + MSCH0_MAINPARTIALPOP = BIT(1),
>> + UPCTL_C_ACTIVE = BIT(0),
>> +};
>> +
>> +#endif
>> diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
>> index 1f84ff9..6b6651a 100644
>> --- a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
>> +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
>> @@ -76,8 +76,11 @@ struct rk3368_grf {
>> u32 soc_con15;
>> u32 soc_con16;
>> u32 soc_con17;
>> + u32 reserved5[0x6e];
>> + u32 ddrc0_con0;
>> };
>> check_member(rk3368_grf, soc_con17, 0x444);
>> +check_member(rk3368_grf, ddrc0_con0, 0x600);
>>
>> struct rk3368_pmu_grf {
>> u32 gpio0a_iomux;
>> diff --git a/arch/arm/mach-rockchip/rk3368/Makefile b/arch/arm/mach-rockchip/rk3368/Makefile
>> index 0390716..46798c2 100644
>> --- a/arch/arm/mach-rockchip/rk3368/Makefile
>> +++ b/arch/arm/mach-rockchip/rk3368/Makefile
>> @@ -5,5 +5,4 @@
>> #
>> obj-y += clk_rk3368.o
>> obj-y += rk3368.o
>> -obj-y += sdram_rk3368.o
>> obj-y += syscon_rk3368.o
>
> the current PX5 EVB and Sheep board(they don't use spl now) depend on
> the sdram_rk3368 driver to get the sdram capacity, and so is the
> geekbox.
> They will be broken when this driver removed.
>
> We got the boot failed log on PX5 like bellow:
>
>> diff --git a/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c b/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c
>> deleted file mode 100644
>> index d0d0900..0000000
>> --- a/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c
>> +++ /dev/null
>> @@ -1,60 +0,0 @@
>> -/*
>> - * (C) Copyright 2016 Rockchip Electronics Co., Ltd.
>> - *
>> - * SPDX-License-Identifier: GPL-2.0
>> - */
>> -
>> -#include <common.h>
>> -#include <dm.h>
>> -#include <ram.h>
>> -#include <syscon.h>
>> -#include <asm/arch/clock.h>
>> -#include <asm/arch/grf_rk3368.h>
>> -#include <asm/arch/sdram_common.h>
>> -
>> -DECLARE_GLOBAL_DATA_PTR;
>> -struct dram_info {
>> - struct ram_info info;
>> - struct rk3368_pmu_grf *pmugrf;
>> -};
>> -
>> -static int rk3368_dmc_probe(struct udevice *dev)
>> -{
>> - struct dram_info *priv = dev_get_priv(dev);
>> -
>> - priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
>> - debug("%s: grf=%p\n", __func__, priv->pmugrf);
>> - priv->info.base = CONFIG_SYS_SDRAM_BASE;
>> - priv->info.size = rockchip_sdram_size(
>> - (phys_addr_t)&priv->pmugrf->os_reg[2]);
>> -
>> - return 0;
>> -}
>> -
>> -static int rk3368_dmc_get_info(struct udevice *dev, struct ram_info *info)
>> -{
>> - struct dram_info *priv = dev_get_priv(dev);
>> -
>> - *info = priv->info;
>> -
>> - return 0;
>> -}
>> -
>> -static struct ram_ops rk3368_dmc_ops = {
>> - .get_info = rk3368_dmc_get_info,
>> -};
>> -
>> -
>> -static const struct udevice_id rk3368_dmc_ids[] = {
>> - { .compatible = "rockchip,rk3368-dmc" },
>> - { }
>> -};
>> -
>> -U_BOOT_DRIVER(dmc_rk3368) = {
>> - .name = "rockchip_rk3368_dmc",
>> - .id = UCLASS_RAM,
>> - .of_match = rk3368_dmc_ids,
>> - .ops = &rk3368_dmc_ops,
>> - .probe = rk3368_dmc_probe,
>> - .priv_auto_alloc_size = sizeof(struct dram_info),
>> -};
>> diff --git a/doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt b/doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt
>> new file mode 100644
>> index 0000000..8e7357d
>> --- /dev/null
>> +++ b/doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt
>> @@ -0,0 +1,67 @@
>> +RK3368 dynamic memory controller driver
>> +=======================================
>> +
>> +The RK3368 DMC (dynamic memory controller) driver supports setup/initialisation
>> +during TPL using configuration data from the DTS (i.e. OF_PLATDATA), based on
>> +the following key configuration data:
>> + (a) a target-frequency (i.e. operating point) for the memory operation
>> + (b) a speed-bin (as defined in JESD-79) for the DDR3 used in hardware
>> + (c) a memory-schedule (i.e. mapping from physical addresses to the address
>> + pins of the memory bus)
>> +
>> +Required properties
>> +-------------------
>> +
>> +- compatible: "rockchip,rk3368-dmc"
>> +- reg
>> + protocol controller (PCTL) address and PHY controller (DDRPHY) address
>> +- rockchip,ddr-speed-bin
>> + the DDR3 device's speed-bin (as specified according to JESD-79)
>> + DDR3_800D (5-5-5)
>> + DDR3_800E (6-6-6)
>> + DDR3_1066E (6-6-6)
>> + DDR3_1066F (7-7-7)
>> + DDR3_1066G (8-8-8)
>> + DDR3_1333F (7-7-7)
>> + DDR3_1333G (8-8-8)
>> + DDR3_1333H (9-9-9)
>> + DDR3_1333J (10-10-10)
>> + DDR3_1600G (8-8-8)
>> + DDR3_1600H (9-9-9)
>> + DDR3_1600J (10-10-10)
>> + DDR3_1600K (11-11-11)
>> + DDR3_1866J (10-10-10)
>> + DDR3_1866K (11-11-11)
>> + DDR3_1866L (12-12-12)
>> + DDR3_1866M (13-13-13)
>> + DDR3_2133K (11-11-11)
>> + DDR3_2133L (12-12-12)
>> + DDR3_2133M (13-13-13)
>> + DDR3_2133N (14-14-14)
>> +- rockchip,ddr-frequency:
>> + target DDR clock frequency in Hz (not all frequencies may be supported,
>> + as there's some cooperation from the clock-driver required)
>> +- rockchip,memory-schedule:
>> + controls the decoding of physical addresses to DRAM addressing (i.e. how
>> + the physical address maps onto the address pins/chip-select of the device)
>> + DMC_MSCH_CBDR: column -> bank -> device -> row
>> + DMC_MSCH_CBRD: column -> band -> row -> device
>> + DMC_MSCH_CRBD: column -> row -> band -> device
>> +
>> +Example (for DDR3-1600K and 800MHz)
>> +-----------------------------------
>> +
>> + #include <dt-bindings/memory/rk3368-dmc.h>
>> +
>> + dmc: dmc at ff610000 {
>> + u-boot,dm-pre-reloc;
>> + compatible = "rockchip,rk3368-dmc";
>> + reg = <0 0xff610000 0 0x400
>> + 0 0xff620000 0 0x400>;
>> + };
>> +
>> + &dmc {
>> + rockchip,ddr-speed-bin = <DDR3_1600K>;
>> + rockchip,ddr-frequency = <800000000>;
>> + rockchip,memory-schedule = <DMC_MSCH_CBRD>;
>> + };
>> diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
>> index c409c48..51ae6be 100644
>> --- a/drivers/ram/Makefile
>> +++ b/drivers/ram/Makefile
>> @@ -8,3 +8,5 @@ obj-$(CONFIG_RAM) += ram-uclass.o
>> obj-$(CONFIG_SANDBOX) += sandbox_ram.o
>> obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o
>> obj-$(CONFIG_ARCH_BMIPS) += bmips_ram.o
>> +
>> +obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
>> diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile
>> new file mode 100644
>> index 0000000..b09d03c
>> --- /dev/null
>> +++ b/drivers/ram/rockchip/Makefile
>> @@ -0,0 +1,7 @@
>> +#
>> +# Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
>> +#
>> +# SPDX-License-Identifier: GPL-2.0+
>> +#
>> +
>> +obj-$(CONFIG_ROCKCHIP_RK3368) = dmc-rk3368.o
>> diff --git a/drivers/ram/rockchip/dmc-rk3368.c b/drivers/ram/rockchip/dmc-rk3368.c
>> new file mode 100644
>> index 0000000..fea96a5
>> --- /dev/null
>> +++ b/drivers/ram/rockchip/dmc-rk3368.c
>> @@ -0,0 +1,990 @@
>> +/*
>> + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
>> + *
>> + * SPDX-License-Identifier: GPL-2.0
>> + */
>> +
>> +#include <common.h>
>> +#include <clk.h>
>> +#include <dm.h>
>> +#include <dt-bindings/memory/rk3368-dmc.h>
>> +#include <dt-structs.h>
>> +#include <ram.h>
>> +#include <regmap.h>
>> +#include <syscon.h>
>> +#include <asm/io.h>
>> +#include <asm/arch/clock.h>
>> +#include <asm/arch/cru_rk3368.h>
>> +#include <asm/arch/grf_rk3368.h>
>> +#include <asm/arch/ddr_rk3368.h>
>> +#include <asm/arch/sdram.h>
>> +#include <asm/arch/sdram_common.h>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +struct dram_info {
>> + struct ram_info info;
>> + struct clk ddr_clk;
>> + struct rk3368_cru *cru;
>> + struct rk3368_grf *grf;
>> + struct rk3368_ddr_pctl *pctl;
>> + struct rk3368_ddrphy *phy;
>> + struct rk3368_pmu_grf *pmugrf;
>> + struct rk3368_msch *msch;
>> +};
>> +
>> +struct rk3368_sdram_params {
>> +#if CONFIG_IS_ENABLED(OF_PLATDATA)
>> + struct dtd_rockchip_rk3368_dmc of_plat;
>> +#endif
>> + struct rk3288_sdram_pctl_timing pctl_timing;
>> + u32 trefi_mem_ddr3;
>> + struct rk3288_sdram_channel chan;
>> + struct regmap *map;
>> + u32 ddr_freq;
>> + u32 memory_schedule;
>> + u32 ddr_speed_bin;
>> + u32 tfaw_mult;
>> +};
>> +
>> +/* PTCL bits */
>> +enum {
>> + /* PCTL_DFISTCFG0 */
>> + DFI_INIT_START = BIT(0),
>> + DFI_DATA_BYTE_DISABLE_EN = BIT(2),
>> +
>> + /* PCTL_DFISTCFG1 */
>> + DFI_DRAM_CLK_SR_EN = BIT(0),
>> + DFI_DRAM_CLK_DPD_EN = BIT(1),
>> + ODT_LEN_BL8_W_SHIFT = 16,
>> +
>> + /* PCTL_DFISTCFG2 */
>> + DFI_PARITY_INTR_EN = BIT(0),
>> + DFI_PARITY_EN = BIT(1),
>> +
>> + /* PCTL_DFILPCFG0 */
>> + TLP_RESP_TIME_SHIFT = 16,
>> + LP_SR_EN = BIT(8),
>> + LP_PD_EN = BIT(0),
>> +
>> + /* PCTL_DFIODTCFG */
>> + RANK0_ODT_WRITE_SEL = BIT(3),
>> + RANK1_ODT_WRITE_SEL = BIT(11),
>> +
>> + /* PCTL_SCFG */
>> + HW_LOW_POWER_EN = BIT(0),
>> +
>> + /* PCTL_MCMD */
>> + START_CMD = BIT(31),
>> + MCMD_RANK0 = BIT(20),
>> + MCMD_RANK1 = BIT(21),
>> + DESELECT_CMD = 0,
>> + PREA_CMD,
>> + REF_CMD,
>> + MRS_CMD,
>> + ZQCS_CMD,
>> + ZQCL_CMD,
>> + RSTL_CMD,
>> + MRR_CMD = 8,
>> + DPDE_CMD,
>> +
>> + /* PCTL_POWCTL */
>> + POWER_UP_START = BIT(0),
>> +
>> + /* PCTL_POWSTAT */
>> + POWER_UP_DONE = BIT(0),
>> +
>> + /* PCTL_SCTL */
>> + INIT_STATE = 0,
>> + CFG_STATE,
>> + GO_STATE,
>> + SLEEP_STATE,
>> + WAKEUP_STATE,
>> +
>> + /* PCTL_STAT */
>> + LP_TRIG_SHIFT = 4,
>> + LP_TRIG_MASK = 7,
>> + PCTL_STAT_MSK = 7,
>> + INIT_MEM = 0,
>> + CONFIG,
>> + CONFIG_REQ,
>> + ACCESS,
>> + ACCESS_REQ,
>> + LOW_POWER,
>> + LOW_POWER_ENTRY_REQ,
>> + LOW_POWER_EXIT_REQ,
>> +
>> + /* PCTL_MCFG */
>> + DDR2_DDR3_BL_8 = BIT(0),
>> + DDR3_EN = BIT(5),
>> + TFAW_TRRD_MULT4 = (0 << 18),
>> + TFAW_TRRD_MULT5 = (1 << 18),
>> + TFAW_TRRD_MULT6 = (2 << 18),
>> +};
>> +
>> +#define DDR3_MR0_WR(n) \
>> + ((n <= 8) ? ((n - 4) << 9) : (((n >> 1) & 0x7) << 9))
>> +#define DDR3_MR0_CL(n) \
>> + ((((n - 4) & 0x7) << 4) | (((n - 4) & 0x8) >> 2))
>> +#define DDR3_MR0_BL8 \
>> + (0 << 0)
>> +#define DDR3_MR0_DLL_RESET \
>> + (1 << 8)
>> +#define DDR3_MR1_RTT120OHM \
>> + ((0 << 9) | (1 << 6) | (0 << 2))
>> +#define DDR3_MR2_TWL(n) \
>> + (((n - 5) & 0x7) << 3)
>> +
>> +
>> +#ifdef CONFIG_TPL_BUILD
>> +
>> +static void ddr_set_noc_spr_err_stall(struct rk3368_grf *grf, bool enable)
>> +{
>> + if (enable)
>> + rk_setreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL);
>> + else
>> + rk_clrreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL);
>> +}
>> +
>> +static void ddr_set_ddr3_mode(struct rk3368_grf *grf, bool ddr3_mode)
>> +{
>> + if (ddr3_mode)
>> + rk_setreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3);
>> + else
>> + rk_clrreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3);
>> +}
>> +
>> +static void ddrphy_config(struct rk3368_ddrphy *phy,
>> + u32 tcl, u32 tal, u32 tcwl)
>> +{
>> + int i;
>> +
>> + /* Set to DDR3 mode */
>> + clrsetbits_le32(&phy->reg[1], 0x3, 0x0);
>> +
>> + /* DDRPHY_REGB: CL, AL */
>> + clrsetbits_le32(&phy->reg[0xb], 0xff, tcl << 4 | tal);
>> + /* DDRPHY_REGC: CWL */
>> + clrsetbits_le32(&phy->reg[0xc], 0x0f, tcwl);
>> +
>> + /* Update drive-strength */
>> + writel(0xcc, &phy->reg[0x11]);
>> + writel(0xaa, &phy->reg[0x16]);
>> + /*
>> + * Update NRCOMP/PRCOMP for all 4 channels (for details of all
>> + * affected registers refer to the documentation of DDRPHY_REG20
>> + * and DDRPHY_REG21 in the RK3368 TRM.
>> + */
>> + for (i = 0; i < 4; ++i) {
>> + writel(0xcc, &phy->reg[0x20 + i * 0x10]);
>> + writel(0x44, &phy->reg[0x21 + i * 0x10]);
>> + }
>> +
>> + /* Enable write-leveling calibration bypass */
>> + setbits_le32(&phy->reg[2], BIT(3));
>> +}
>> +
>> +static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
>> +{
>> + int i;
>> +
>> + for (i = 0; i < n / sizeof(u32); i++)
>> + writel(*src++, dest++);
>> +}
>> +
>> +static void send_command(struct rk3368_ddr_pctl *pctl, u32 rank, u32 cmd)
>> +{
>> + u32 mcmd = START_CMD | cmd | rank;
>> +
>> + debug("%s: writing %x to MCMD\n", __func__, mcmd);
>> + writel(mcmd, &pctl->mcmd);
>> + while (readl(&pctl->mcmd) & START_CMD)
>> + /* spin */;
>> +}
>> +
>> +static void send_mrs(struct rk3368_ddr_pctl *pctl,
>> + u32 rank, u32 mr_num, u32 mr_data)
>> +{
>> + u32 mcmd = START_CMD | MRS_CMD | rank | (mr_num << 17) | (mr_data << 4);
>> +
>> + debug("%s: writing %x to MCMD\n", __func__, mcmd);
>> + writel(mcmd, &pctl->mcmd);
>> + while (readl(&pctl->mcmd) & START_CMD)
>> + /* spin */;
>> +}
>> +
>> +static int memory_init(struct rk3368_ddr_pctl *pctl,
>> + struct rk3368_sdram_params *params)
>> +{
>> + u32 mr[4];
>> + const ulong timeout_ms = 500;
>> + ulong tmp;
>> +
>> + /*
>> + * Power up DRAM by DDR_PCTL_POWCTL[0] register of PCTL and
>> + * wait power up DRAM finish with DDR_PCTL_POWSTAT[0] register
>> + * of PCTL.
>> + */
>> + writel(POWER_UP_START, &pctl->powctl);
>> +
>> + tmp = get_timer(0);
>> + do {
>> + if (get_timer(tmp) > timeout_ms) {
>> + error("%s: POWER_UP_START did not complete in %ld ms\n",
>> + __func__, timeout_ms);
>> + return -ETIME;
>> + }
>> + } while (!(readl(&pctl->powstat) & POWER_UP_DONE));
>> +
>> + /* Configure MR0 through MR3 */
>> + mr[0] = DDR3_MR0_WR(params->pctl_timing.twr) |
>> + DDR3_MR0_CL(params->pctl_timing.tcl) |
>> + DDR3_MR0_DLL_RESET;
>> + mr[1] = DDR3_MR1_RTT120OHM;
>> + mr[2] = DDR3_MR2_TWL(params->pctl_timing.tcwl);
>> + mr[3] = 0;
>> +
>> + /*
>> + * Also see RK3368 Technical Reference Manual:
>> + * "16.6.2 Initialization (DDR3 Initialization Sequence)"
>> + */
>> + send_command(pctl, MCMD_RANK0 | MCMD_RANK1, DESELECT_CMD);
>> + udelay(1);
>> + send_command(pctl, MCMD_RANK0 | MCMD_RANK1, PREA_CMD);
>> + send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 2, mr[2]);
>> + send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 3, mr[3]);
>> + send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 1, mr[1]);
>> + send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 0, mr[0]);
>> + send_command(pctl, MCMD_RANK0 | MCMD_RANK1, ZQCL_CMD);
>> +
>> + return 0;
>> +}
>> +
>> +static void move_to_config_state(struct rk3368_ddr_pctl *pctl)
>> +{
>> + /*
>> + * Also see RK3368 Technical Reference Manual:
>> + * "16.6.1 State transition of PCTL (Moving to Config State)"
>> + */
>> + u32 state = readl(&pctl->stat) & PCTL_STAT_MSK;
>> +
>> + switch (state) {
>> + case LOW_POWER:
>> + writel(WAKEUP_STATE, &pctl->sctl);
>> + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
>> + /* spin */;
>> +
>> + /* fall-through */
>> + case ACCESS:
>> + case INIT_MEM:
>> + writel(CFG_STATE, &pctl->sctl);
>> + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
>> + /* spin */;
>> + break;
>> +
>> + case CONFIG:
>> + return;
>> +
>> + default:
>> + break;
>> + }
>> +}
>> +
>> +static void move_to_access_state(struct rk3368_ddr_pctl *pctl)
>> +{
>> + /*
>> + * Also see RK3368 Technical Reference Manual:
>> + * "16.6.1 State transition of PCTL (Moving to Access State)"
>> + */
>> + u32 state = readl(&pctl->stat) & PCTL_STAT_MSK;
>> +
>> + switch (state) {
>> + case LOW_POWER:
>> + if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) &
>> + LP_TRIG_MASK) == 1)
>> + return;
>> +
>> + writel(WAKEUP_STATE, &pctl->sctl);
>> + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
>> + /* spin */;
>> +
>> + /* fall-through */
>> + case INIT_MEM:
>> + writel(CFG_STATE, &pctl->sctl);
>> + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
>> + /* spin */;
>> +
>> + /* fall-through */
>> + case CONFIG:
>> + writel(GO_STATE, &pctl->sctl);
>> + while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG)
>> + /* spin */;
>> + break;
>> +
>> + case ACCESS:
>> + return;
>> +
>> + default:
>> + break;
>> + }
>> +}
>> +
>> +static void ddrctl_reset(struct rk3368_cru *cru)
>> +{
>> + const u32 ctl_reset = BIT(3) | BIT(2);
>> + const u32 phy_reset = BIT(1) | BIT(0);
>> +
>> + rk_setreg(&cru->softrst_con[10], ctl_reset | phy_reset);
>> + udelay(1);
>> + rk_clrreg(&cru->softrst_con[10], ctl_reset | phy_reset);
>> +}
>> +
>> +static void ddrphy_reset(struct rk3368_ddrphy *ddrphy)
>> +{
>> + clrbits_le32(&ddrphy->reg[0], BIT(3) | BIT(2));
>> + udelay(1);
>> + setbits_le32(&ddrphy->reg[0], BIT(3) | BIT(2));
>> +}
>> +
>> +static void ddrphy_config_delays(struct rk3368_ddrphy *ddrphy, u32 freq)
>> +{
>> + u32 dqs_dll_delay;
>> +
>> + setbits_le32(&ddrphy->reg[0x13], BIT(4));
>> + clrbits_le32(&ddrphy->reg[0x14], BIT(3));
>> +
>> + setbits_le32(&ddrphy->reg[0x26], BIT(4));
>> + clrbits_le32(&ddrphy->reg[0x27], BIT(3));
>> +
>> + setbits_le32(&ddrphy->reg[0x36], BIT(4));
>> + clrbits_le32(&ddrphy->reg[0x37], BIT(3));
>> +
>> + setbits_le32(&ddrphy->reg[0x46], BIT(4));
>> + clrbits_le32(&ddrphy->reg[0x47], BIT(3));
>> +
>> + setbits_le32(&ddrphy->reg[0x56], BIT(4));
>> + clrbits_le32(&ddrphy->reg[0x57], BIT(3));
>> +
>> + if (freq <= 400000000)
>> + setbits_le32(&ddrphy->reg[0xa4], 0x1f);
>> + else
>> + clrbits_le32(&ddrphy->reg[0xa4], 0x1f);
>> +
>> + if (freq < 681000000)
>> + dqs_dll_delay = 3; /* 67.5 degree delay */
>> + else
>> + dqs_dll_delay = 2; /* 45 degree delay */
>> +
>> + writel(dqs_dll_delay, &ddrphy->reg[0x28]);
>> + writel(dqs_dll_delay, &ddrphy->reg[0x38]);
>> + writel(dqs_dll_delay, &ddrphy->reg[0x48]);
>> + writel(dqs_dll_delay, &ddrphy->reg[0x58]);
>> +}
>> +
>> +static int dfi_cfg(struct rk3368_ddr_pctl *pctl)
>> +{
>> + const ulong timeout_ms = 200;
>> + ulong tmp;
>> +
>> + writel(DFI_DATA_BYTE_DISABLE_EN, &pctl->dfistcfg0);
>> +
>> + writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN,
>> + &pctl->dfistcfg1);
>> + writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2);
>> + writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN,
>> + &pctl->dfilpcfg0);
>> +
>> + writel(1, &pctl->dfitphyupdtype0);
>> +
>> + writel(0x1f, &pctl->dfitphyrdlat);
>> + writel(0, &pctl->dfitphywrdata);
>> + writel(0, &pctl->dfiupdcfg); /* phyupd and ctrlupd disabled */
>> +
>> + setbits_le32(&pctl->dfistcfg0, DFI_INIT_START);
>> +
>> + tmp = get_timer(0);
>> + do {
>> + if (get_timer(tmp) > timeout_ms) {
>> + error("%s: DFI init did not complete within %ld ms\n",
>> + __func__, timeout_ms);
>> + return -ETIME;
>> + }
>> + } while ((readl(&pctl->dfiststat0) & 1) == 0);
>> +
>> + return 0;
>> +}
>> +
>> +static inline u32 ps_to_tCK(const u32 ps, const ulong freq)
>> +{
>> + const ulong MHz = 1000000;
>> + return DIV_ROUND_UP(ps * freq, 1000000 * MHz);
>> +}
>> +
>> +static inline u32 ns_to_tCK(const u32 ns, const ulong freq)
>> +{
>> + return ps_to_tCK(ns * 1000, freq);
>> +}
>> +
>> +static inline u32 tCK_to_ps(const ulong tCK, const ulong freq)
>> +{
>> + const ulong MHz = 1000000;
>> + return DIV_ROUND_UP(tCK * 1000000 * MHz, freq);
>> +}
>> +
>> +static int pctl_calc_timings(struct rk3368_sdram_params *params,
>> + ulong freq)
>> +{
>> + struct rk3288_sdram_pctl_timing *pctl_timing = ¶ms->pctl_timing;
>> + const ulong MHz = 1000000;
>> + u32 tccd;
>> + u32 tfaw_as_ps;
>> +
>> + if (params->ddr_speed_bin != DDR3_1600K) {
>> + error("%s: unimplemented DDR3 speed bin %d\n",
>> + __func__, params->ddr_speed_bin);
>> + return -1;
>> + }
>> +
>> + /* PCTL is clocked at 1/2 the DRAM clock; err on the side of caution */
>> + pctl_timing->togcnt1u = DIV_ROUND_UP(freq, 2 * MHz);
>> + pctl_timing->togcnt100n = DIV_ROUND_UP(freq / 10, 2 * MHz);
>> +
>> + pctl_timing->tinit = 200; /* 200 usec */
>> + pctl_timing->trsth = 500; /* 500 usec */
>> + pctl_timing->trefi = 78; /* 7.8usec = 78 * 100ns */
>> + params->trefi_mem_ddr3 = ns_to_tCK(pctl_timing->trefi * 100, freq);
>> +
>> + if (freq <= (400 * MHz)) {
>> + pctl_timing->tcl = 6;
>> + pctl_timing->tcwl = 10;
>> + } else if (freq <= (533 * MHz)) {
>> + pctl_timing->tcl = 8;
>> + pctl_timing->tcwl = 6;
>> + } else if (freq <= (666 * MHz)) {
>> + pctl_timing->tcl = 10;
>> + pctl_timing->tcwl = 7;
>> + } else {
>> + pctl_timing->tcl = 11;
>> + pctl_timing->tcwl = 8;
>> + }
>> +
>> + pctl_timing->tmrd = 4; /* 4 tCK (all speed bins) */
>> + pctl_timing->trfc = ns_to_tCK(350, freq); /* tRFC: 350 (max) @ 8GBit */
>> + pctl_timing->trp = max(4u, ps_to_tCK(13750, freq));
>> + /*
>> + * JESD-79:
>> + * READ to WRITE Command Delay = RL + tCCD / 2 + 2tCK - WL
>> + */
>> + tccd = 4;
>> + pctl_timing->trtw = pctl_timing->tcl + tccd/2 + 2 - pctl_timing->tcwl;
>> + pctl_timing->tal = 0;
>> + pctl_timing->tras = ps_to_tCK(35000, freq);
>> + pctl_timing->trc = ps_to_tCK(48750, freq);
>> + pctl_timing->trcd = ps_to_tCK(13750, freq);
>> + pctl_timing->trrd = max(4u, ps_to_tCK(7500, freq));
>> + pctl_timing->trtp = max(4u, ps_to_tCK(7500, freq));
>> + pctl_timing->twr = ps_to_tCK(15000, freq);
>> + /* The DDR3 mode-register does only support even values for tWR > 8. */
>> + if (pctl_timing->twr > 8)
>> + pctl_timing->twr = (pctl_timing->twr + 1) & ~1;
>> + pctl_timing->twtr = max(4u, ps_to_tCK(7500, freq));
>> + pctl_timing->texsr = 512; /* tEXSR(max) is tDLLLK */
>> + pctl_timing->txp = max(3u, ps_to_tCK(6000, freq));
>> + pctl_timing->txpdll = max(10u, ps_to_tCK(24000, freq));
>> + pctl_timing->tzqcs = max(64u, ps_to_tCK(80000, freq));
>> + pctl_timing->tzqcsi = 10000; /* as used by Rockchip */
>> + pctl_timing->tdqs = 1; /* fixed for DDR3 */
>> + pctl_timing->tcksre = max(5u, ps_to_tCK(10000, freq));
>> + pctl_timing->tcksrx = max(5u, ps_to_tCK(10000, freq));
>> + pctl_timing->tcke = max(3u, ps_to_tCK(5000, freq));
>> + pctl_timing->tmod = max(12u, ps_to_tCK(15000, freq));
>> + pctl_timing->trstl = ns_to_tCK(100, freq);
>> + pctl_timing->tzqcl = max(256u, ps_to_tCK(320000, freq)); /* tZQoper */
>> + pctl_timing->tmrr = 0;
>> + pctl_timing->tckesr = pctl_timing->tcke + 1; /* JESD-79: tCKE + 1tCK */
>> + pctl_timing->tdpd = 0; /* RK3368 TRM: "allowed values for DDR3: 0" */
>> +
>> +
>> + /*
>> + * The controller can represent tFAW as 4x, 5x or 6x tRRD only.
>> + * We want to use the smallest multiplier that satisfies the tFAW
>> + * requirements of the given speed-bin. If necessary, we stretch out
>> + * tRRD to allow us to operate on a 6x multiplier for tFAW.
>> + */
>> + tfaw_as_ps = 40000; /* 40ns: tFAW for DDR3-1600K, 2KB page-size */
>> + if (tCK_to_ps(pctl_timing->trrd * 6, freq) < tfaw_as_ps) {
>> + /* If tFAW is > 6 x tRRD, we need to stretch tRRD */
>> + pctl_timing->trrd = ps_to_tCK(DIV_ROUND_UP(40000, 6), freq);
>> + params->tfaw_mult = TFAW_TRRD_MULT6;
>> + } else if (tCK_to_ps(pctl_timing->trrd * 5, freq) < tfaw_as_ps) {
>> + params->tfaw_mult = TFAW_TRRD_MULT6;
>> + } else if (tCK_to_ps(pctl_timing->trrd * 4, freq) < tfaw_as_ps) {
>> + params->tfaw_mult = TFAW_TRRD_MULT5;
>> + } else {
>> + params->tfaw_mult = TFAW_TRRD_MULT4;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static void pctl_cfg(struct rk3368_ddr_pctl *pctl,
>> + struct rk3368_sdram_params *params,
>> + struct rk3368_grf *grf)
>> +{
>> + /* Configure PCTL timing registers */
>> + params->pctl_timing.trefi |= BIT(31); /* see PCTL_TREFI */
>> + copy_to_reg(&pctl->togcnt1u, ¶ms->pctl_timing.togcnt1u,
>> + sizeof(params->pctl_timing));
>> + writel(params->trefi_mem_ddr3, &pctl->trefi_mem_ddr3);
>> +
>> + /* Set up ODT write selector and ODT write length */
>> + writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL), &pctl->dfiodtcfg);
>> + writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1);
>> +
>> + /* Set up the CL/CWL-dependent timings of DFI */
>> + writel((params->pctl_timing.tcl - 1) / 2 - 1, &pctl->dfitrddataen);
>> + writel((params->pctl_timing.tcwl - 1) / 2 - 1, &pctl->dfitphywrlat);
>> +
>> + /* DDR3 */
>> + writel(params->tfaw_mult | DDR3_EN | DDR2_DDR3_BL_8, &pctl->mcfg);
>> + writel(0x001c0004, &grf->ddrc0_con0);
>> +
>> + setbits_le32(&pctl->scfg, HW_LOW_POWER_EN);
>> +}
>> +
>> +static int ddrphy_data_training(struct rk3368_ddr_pctl *pctl,
>> + struct rk3368_ddrphy *ddrphy)
>> +{
>> + const u32 trefi = readl(&pctl->trefi);
>> + const ulong timeout_ms = 500;
>> + ulong tmp;
>> +
>> + /* disable auto-refresh */
>> + writel(0 | BIT(31), &pctl->trefi);
>> +
>> + clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x20);
>> + clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x21);
>> +
>> + tmp = get_timer(0);
>> + do {
>> + if (get_timer(tmp) > timeout_ms) {
>> + error("%s: did not complete within %ld ms\n",
>> + __func__, timeout_ms);
>> + return -ETIME;
>> + }
>> + } while ((readl(&ddrphy->reg[0xff]) & 0xf) != 0xf);
>> +
>> + send_command(pctl, MCMD_RANK0 | MCMD_RANK1, PREA_CMD);
>> + clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x20);
>> + /* resume auto-refresh */
>> + writel(trefi | BIT(31), &pctl->trefi);
>> +
>> + return 0;
>> +}
>> +
>> +static int sdram_col_row_detect(struct udevice *dev)
>> +{
>> + struct dram_info *priv = dev_get_priv(dev);
>> + struct rk3368_sdram_params *params = dev_get_platdata(dev);
>> + struct rk3368_ddr_pctl *pctl = priv->pctl;
>> + struct rk3368_msch *msch = priv->msch;
>> + const u32 test_pattern = 0x5aa5f00f;
>> + int row, col;
>> + uintptr_t addr;
>> +
>> + move_to_config_state(pctl);
>> + writel(6, &msch->ddrconf);
>> + move_to_access_state(pctl);
>> +
>> + /* Detect col */
>> + for (col = 11; col >= 9; col--) {
>> + writel(0, CONFIG_SYS_SDRAM_BASE);
>> + addr = CONFIG_SYS_SDRAM_BASE +
>> + (1 << (col + params->chan.bw - 1));
>> + writel(test_pattern, addr);
>> + if ((readl(addr) == test_pattern) &&
>> + (readl(CONFIG_SYS_SDRAM_BASE) == 0))
>> + break;
>> + }
>> +
>> + if (col == 8) {
>> + error("%s: col detect error\n", __func__);
>> + return -EINVAL;
>> + }
>> +
>> + move_to_config_state(pctl);
>> + writel(15, &msch->ddrconf);
>> + move_to_access_state(pctl);
>> +
>> + /* Detect row*/
>> + for (row = 16; row >= 12; row--) {
>> + writel(0, CONFIG_SYS_SDRAM_BASE);
>> + addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
>> + writel(test_pattern, addr);
>> + if ((readl(addr) == test_pattern) &&
>> + (readl(CONFIG_SYS_SDRAM_BASE) == 0))
>> + break;
>> + }
>> +
>> + if (row == 11) {
>> + error("%s: row detect error\n", __func__);
>> + return -EINVAL;
>> + }
>> +
>> + /* Record results */
>> + debug("%s: col %d, row %d\n", __func__, col, row);
>> + params->chan.col = col;
>> + params->chan.cs0_row = row;
>> + params->chan.cs1_row = row;
>> + params->chan.row_3_4 = 0;
>> +
>> + return 0;
>> +}
>> +
>> +static int msch_niu_config(struct rk3368_msch *msch,
>> + struct rk3368_sdram_params *params)
>> +{
>> + int i;
>> + const u8 cols = params->chan.col - ((params->chan.bw == 2) ? 0 : 1);
>> + const u8 rows = params->chan.cs0_row;
>> +
>> + /*
>> + * The DDR address-translation table always assumes a 32bit
>> + * bus and the comparison below takes care of adjusting for
>> + * a 16bit bus (i.e. one column-address is consumed).
>> + */
>> + const struct {
>> + u8 rows;
>> + u8 columns;
>> + u8 type;
>> + } ddrconf_table[] = {
>> + /*
>> + * C-B-R-D patterns are first. For these we require an
>> + * exact match for the columns and rows (as there's
>> + * one entry per possible configuration).
>> + */
>> + [0] = { .rows = 13, .columns = 10, .type = DMC_MSCH_CBRD },
>> + [1] = { .rows = 14, .columns = 10, .type = DMC_MSCH_CBRD },
>> + [2] = { .rows = 15, .columns = 10, .type = DMC_MSCH_CBRD },
>> + [3] = { .rows = 16, .columns = 10, .type = DMC_MSCH_CBRD },
>> + [4] = { .rows = 14, .columns = 11, .type = DMC_MSCH_CBRD },
>> + [5] = { .rows = 15, .columns = 11, .type = DMC_MSCH_CBRD },
>> + [6] = { .rows = 16, .columns = 11, .type = DMC_MSCH_CBRD },
>> + [7] = { .rows = 13, .columns = 9, .type = DMC_MSCH_CBRD },
>> + [8] = { .rows = 14, .columns = 9, .type = DMC_MSCH_CBRD },
>> + [9] = { .rows = 15, .columns = 9, .type = DMC_MSCH_CBRD },
>> + [10] = { .rows = 16, .columns = 9, .type = DMC_MSCH_CBRD },
>> + /*
>> + * 11 through 13 are C-R-B-D patterns. These are
>> + * matched for an exact number of columns and to
>> + * ensure that the hardware uses at least as many rows
>> + * as the pattern requires (i.e. we make sure that
>> + * there's no gaps up until we hit the device/chip-select;
>> + * however, these patterns can accept up to 16 rows,
>> + * as the row-address continues right after the CS
>> + * switching)
>> + */
>> + [11] = { .rows = 15, .columns = 10, .type = DMC_MSCH_CRBD },
>> + [12] = { .rows = 14, .columns = 11, .type = DMC_MSCH_CRBD },
>> + [13] = { .rows = 13, .columns = 10, .type = DMC_MSCH_CRBD },
>> + /*
>> + * 14 and 15 are catch-all variants using a C-B-D-R
>> + * scheme (i.e. alternating the chip-select every time
>> + * C-B overflows) and stuffing the remaining C-bits
>> + * into the top. Matching needs to make sure that the
>> + * number of columns is either an exact match (i.e. we
>> + * can use less the the maximum number of rows) -or-
>> + * that the columns exceed what is given in this table
>> + * and the rows are an exact match (in which case the
>> + * remaining C-bits will be stuffed onto the top after
>> + * the device/chip-select switches).
>> + */
>> + [14] = { .rows = 16, .columns = 10, .type = DMC_MSCH_CBDR },
>> + [15] = { .rows = 16, .columns = 9, .type = DMC_MSCH_CBDR },
>> + };
>> +
>> + /*
>> + * For C-B-R-D, we need an exact match (i.e. both for the number of
>> + * columns and rows), while for C-B-D-R, only the the number of
>> + * columns needs to match.
>> + */
>> + for (i = 0; i < ARRAY_SIZE(ddrconf_table); i++) {
>> + bool match = false;
>> +
>> + /* If this entry if for a different matcher, then skip it */
>> + if (ddrconf_table[i].type != params->memory_schedule)
>> + continue;
>> +
>> + /*
>> + * Match according to the rules (exact/inexact/at-least)
>> + * documented in the ddrconf_table above.
>> + */
>> + switch (params->memory_schedule) {
>> + case DMC_MSCH_CBRD:
>> + match = (ddrconf_table[i].columns == cols) &&
>> + (ddrconf_table[i].rows == rows);
>> + break;
>> +
>> + case DMC_MSCH_CRBD:
>> + match = (ddrconf_table[i].columns == cols) &&
>> + (ddrconf_table[i].rows <= rows);
>> + break;
>> +
>> + case DMC_MSCH_CBDR:
>> + match = (ddrconf_table[i].columns == cols) ||
>> + ((ddrconf_table[i].columns <= cols) &&
>> + (ddrconf_table[i].rows == rows));
>> + break;
>> +
>> + default:
>> + break;
>> + }
>> +
>> + if (match) {
>> + debug("%s: setting ddrconf 0x%x\n", __func__, i);
>> + writel(i, &msch->ddrconf);
>> + return 0;
>> + }
>> + }
>> +
>> + error("%s: ddrconf (NIU config) not found\n", __func__);
>> + return -EINVAL;
>> +}
>> +
>> +static void dram_all_config(struct udevice *dev)
>> +{
>> + struct dram_info *priv = dev_get_priv(dev);
>> + struct rk3368_pmu_grf *pmugrf = priv->pmugrf;
>> + struct rk3368_sdram_params *params = dev_get_platdata(dev);
>> + const struct rk3288_sdram_channel *info = ¶ms->chan;
>> + u32 sys_reg = 0;
>> + const int chan = 0;
>> +
>> + sys_reg |= DDR3 << SYS_REG_DDRTYPE_SHIFT;
>> + sys_reg |= 0 << SYS_REG_NUM_CH_SHIFT;
>> +
>> + sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan);
>> + sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan);
>> + sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan);
>> + sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan);
>> + sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan);
>> + sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan);
>> + sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan);
>> + sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan);
>> + sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan);
>> +
>> + writel(sys_reg, &pmugrf->os_reg[2]);
>> +}
>> +
>> +static int setup_sdram(struct udevice *dev)
>> +{
>> + struct dram_info *priv = dev_get_priv(dev);
>> + struct rk3368_sdram_params *params = dev_get_platdata(dev);
>> +
>> + struct rk3368_ddr_pctl *pctl = priv->pctl;
>> + struct rk3368_ddrphy *ddrphy = priv->phy;
>> + struct rk3368_cru *cru = priv->cru;
>> + struct rk3368_grf *grf = priv->grf;
>> + struct rk3368_msch *msch = priv->msch;
>> +
>> + int ret;
>> +
>> + /* The input clock (i.e. DPLL) needs to be 2x the DRAM frequency */
>> + ret = clk_set_rate(&priv->ddr_clk, 2 * params->ddr_freq);
>> + if (ret < 0) {
>> + debug("%s: could not set DDR clock: %d\n", __func__, ret);
>> + return ret;
>> + }
>> +
>> + /* Update the read-latency for the RK3368 */
>> + writel(0x32, &msch->readlatency);
>> +
>> + /* Initialise the DDR PCTL and DDR PHY */
>> + ddrctl_reset(cru);
>> + ddrphy_reset(ddrphy);
>> + ddrphy_config_delays(ddrphy, params->ddr_freq);
>> + dfi_cfg(pctl);
>> + /* Configure relative system information of grf_ddrc0_con0 register */
>> + ddr_set_ddr3_mode(grf, true);
>> + ddr_set_noc_spr_err_stall(grf, true);
>> + /* Calculate timings */
>> + pctl_calc_timings(params, params->ddr_freq);
>> + /* Initialise the device timings in protocol controller */
>> + pctl_cfg(pctl, params, grf);
>> + /* Configure AL, CL ... information of PHY registers */
>> + ddrphy_config(ddrphy,
>> + params->pctl_timing.tcl,
>> + params->pctl_timing.tal,
>> + params->pctl_timing.tcwl);
>> +
>> + /* Initialize DRAM and configure with mode-register values */
>> + ret = memory_init(pctl, params);
>> + if (ret)
>> + goto error;
>> +
>> + move_to_config_state(pctl);
>> + /* Perform data-training */
>> + ddrphy_data_training(pctl, ddrphy);
>> + move_to_access_state(pctl);
>> +
>> + /* TODO(prt): could detect rank in training... */
>> + params->chan.rank = 2;
>> + /* TODO(prt): bus width is not auto-detected (yet)... */
>> + params->chan.bw = 2; /* 32bit wide bus */
>> + params->chan.dbw = params->chan.dbw; /* 32bit wide bus */
>> +
>> + /* DDR3 is always 8 bank */
>> + params->chan.bk = 3;
>> + /* Detect col and row number */
>> + ret = sdram_col_row_detect(dev);
>> + if (ret)
>> + goto error;
>> +
>> + /* Configure NIU DDR configuration */
>> + ret = msch_niu_config(msch, params);
>> + if (ret)
>> + goto error;
>> +
>> + /* set up OS_REG to communicate w/ next stage and OS */
>> + dram_all_config(dev);
>> +
>> + return 0;
>> +
>> +error:
>> + printf("DRAM init failed!\n");
>> + hang();
>> +}
>> +#endif
>> +
>> +static int rk3368_dmc_ofdata_to_platdata(struct udevice *dev)
>> +{
>> + int ret = 0;
>> +
>> +#if !CONFIG_IS_ENABLED(OF_PLATDATA)
>> + struct rk3368_sdram_params *plat = dev_get_platdata(dev);
>> +
>> + ret = regmap_init_mem(dev, &plat->map);
>> + if (ret)
>> + return ret;
>> +#endif
>> +
>> + return ret;
>> +}
>> +
>> +#if CONFIG_IS_ENABLED(OF_PLATDATA)
>> +static int conv_of_platdata(struct udevice *dev)
>> +{
>> + struct rk3368_sdram_params *plat = dev_get_platdata(dev);
>> + struct dtd_rockchip_rk3368_dmc *of_plat = &plat->of_plat;
>> + int ret;
>> +
>> + plat->ddr_freq = of_plat->rockchip_ddr_frequency;
>> + plat->ddr_speed_bin = of_plat->rockchip_ddr_speed_bin;
>> + plat->memory_schedule = of_plat->rockchip_memory_schedule;
>> +
>> + ret = regmap_init_mem_platdata(dev, of_plat->reg,
>> + ARRAY_SIZE(of_plat->reg) / 2,
>> + &plat->map);
>> + if (ret)
>> + return ret;
>> +
>> + return 0;
>> +}
>> +#endif
>> +
>> +static int rk3368_dmc_probe(struct udevice *dev)
>> +{
>> +#ifdef CONFIG_TPL_BUILD
>> + struct rk3368_sdram_params *plat = dev_get_platdata(dev);
>> + struct rk3368_ddr_pctl *pctl;
>> + struct rk3368_ddrphy *ddrphy;
>> + struct rk3368_cru *cru;
>> + struct rk3368_grf *grf;
>> + struct rk3368_msch *msch;
>> + int ret;
>> + struct udevice *dev_clk;
>> +#endif
>> + struct dram_info *priv = dev_get_priv(dev);
>> +
>> +#if CONFIG_IS_ENABLED(OF_PLATDATA)
>> + ret = conv_of_platdata(dev);
>> + if (ret)
>> + return ret;
>> +#endif
>> +
>> + priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
>> + debug("%s: pmugrf=%p\n", __func__, priv->pmugrf);
>> +
>> +#ifdef CONFIG_TPL_BUILD
>> + pctl = regmap_get_range(plat->map, 0);
>> + ddrphy = regmap_get_range(plat->map, 1);
>> + msch = syscon_get_first_range(ROCKCHIP_SYSCON_MSCH);
>> + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
>> +
>> + priv->pctl = pctl;
>> + priv->phy = ddrphy;
>> + priv->msch = msch;
>> + priv->grf = grf;
>> +
>> + ret = rockchip_get_clk(&dev_clk);
>> + if (ret)
>> + return ret;
>> + priv->ddr_clk.id = CLK_DDR;
>> + ret = clk_request(dev_clk, &priv->ddr_clk);
>> + if (ret)
>> + return ret;
>> +
>> + cru = rockchip_get_cru();
>> + priv->cru = cru;
>> + if (IS_ERR(priv->cru))
>> + return PTR_ERR(priv->cru);
>> +
>> + ret = setup_sdram(dev);
>> + if (ret)
>> + return ret;
>> +#endif
>> +
>> + priv->info.base = 0;
>> + priv->info.size =
>> + rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg[2]);
>> +
>> + /*
>> + * we use the 0x00000000~0xfdffffff space since 0xff000000~0xffffffff
>> + * is SoC register space (i.e. reserved), and 0xfe000000~0xfeffffff is
>> + * inaccessible for some IP controller.
>> + */
>> + priv->info.size = min(priv->info.size, (size_t)0xfe000000);
>> +
>> + return 0;
>> +}
>> +
>> +static int rk3368_dmc_get_info(struct udevice *dev, struct ram_info *info)
>> +{
>> + struct dram_info *priv = dev_get_priv(dev);
>> +
>> + *info = priv->info;
>> + return 0;
>> +}
>> +
>> +static struct ram_ops rk3368_dmc_ops = {
>> + .get_info = rk3368_dmc_get_info,
>> +};
>> +
>> +
>> +static const struct udevice_id rk3368_dmc_ids[] = {
>> + { .compatible = "rockchip,rk3368-dmc" },
>> + { }
>> +};
>> +
>> +U_BOOT_DRIVER(dmc_rk3368) = {
>> + .name = "rockchip_rk3368_dmc",
>> + .id = UCLASS_RAM,
>> + .of_match = rk3368_dmc_ids,
>> + .ops = &rk3368_dmc_ops,
>> + .probe = rk3368_dmc_probe,
>> + .priv_auto_alloc_size = sizeof(struct dram_info),
>> + .ofdata_to_platdata = rk3368_dmc_ofdata_to_platdata,
>> + .probe = rk3368_dmc_probe,
>> + .priv_auto_alloc_size = sizeof(struct dram_info),
>> + .platdata_auto_alloc_size = sizeof(struct rk3368_sdram_params),
>> +};
>> diff --git a/include/dt-bindings/memory/rk3368-dmc.h b/include/dt-bindings/memory/rk3368-dmc.h
>> new file mode 100644
>> index 0000000..b06ffde
>> --- /dev/null
>> +++ b/include/dt-bindings/memory/rk3368-dmc.h
>> @@ -0,0 +1,30 @@
>> +#ifndef DT_BINDINGS_RK3368_DMC_H
>> +#define DT_BINDINGS_RK3368_DMC_H
>> +
>> +#define DMC_MSCH_CBDR 0x0
>> +#define DMC_MSCH_CBRD 0x1
>> +#define DMC_MSCH_CRBD 0x2
>> +
>> +#define DDR3_800D 0
>> +#define DDR3_800E 1
>> +#define DDR3_1066E 2
>> +#define DDR3_1066F 3
>> +#define DDR3_1066G 4
>> +#define DDR3_1333F 5
>> +#define DDR3_1333G 6
>> +#define DDR3_1333H 7
>> +#define DDR3_1333J 8
>> +#define DDR3_1600G 9
>> +#define DDR3_1600H 10
>> +#define DDR3_1600J 11
>> +#define DDR3_1600K 12
>> +#define DDR3_1866J 13
>> +#define DDR3_1866K 14
>> +#define DDR3_1866L 15
>> +#define DDR3_1866M 16
>> +#define DDR3_2133K 17
>> +#define DDR3_2133L 18
>> +#define DDR3_2133M 19
>> +#define DDR3_2133N 20
>> +
>> +#endif
>
> dpd;
> + u32 trefi_mem_ddr3;
> + u32 reserved5[45];
> + u32 dtuwactl;
> + u32 dturactl;
> + u32 dtucfg;
> + u32 dtuectl;
> + u32 dtuwd0;
> + u32 dtuwd1;
> + u32 dtuwd2;
> + u32 dtuwd3;
> + u32 dtuwdm;
> + u32 dturd0;
> + u32 dturd1;
> + u32 dturd2;
> + u32 dturd3;
> + u32 dtulfsrwd;
> + u32 dtulfsrrd;
> + u32 dtueaf;
> + u32 dfitctrldelay;
> + u32 dfiodtcfg;
> + u32 dfiodtcfg1;
> + u32 dfiodtrankmap;
> + u32 dfitphywrdata;
> + u32 dfitphywrlat;
> + u32 reserved7[2];
> + u32 dfitrddataen;
> + u32 dfitphyrdlat;
> + u32 reserved8[2];
> + u32 dfitphyupdtype0;
> + u32 dfitphyupdtype1;
> + u32 dfitphyupdtype2;
> + u32 dfitphyupdtype3;
> + u32 dfitctrlupdmin;
> + u32 dfitctrlupdmax;
> + u32 dfitctrlupddly;
> + u32 reserved9;
> + u32 dfiupdcfg;
> + u32 dfitrefmski;
> + u32 dfitctrlupdi;
> + u32 reserved10[4];
> + u32 dfitrcfg0;
> + u32 dfitrstat0;
> + u32 dfitrwrlvlen;
> + u32 dfitrrdlvlen;
> + u32 dfitrrdlvlgateen;
> + u32 dfiststat0;
> + u32 dfistcfg0;
> + u32 dfistcfg1;
> + u32 reserved11;
> + u32 dfitdramclken;
> + u32 dfitdramclkdis;
> + u32 dfistcfg2;
> + u32 dfistparclr;
> + u32 dfistparlog;
> + u32 reserved12[3];
> + u32 dfilpcfg0;
> + u32 reserved13[3];
> + u32 dfitrwrlvlresp0;
> + u32 dfitrwrlvlresp1;
> + u32 dfitrwrlvlresp2;
> + u32 dfitrrdlvlresp0;
> + u32 dfitrrdlvlresp1;
> + u32 dfitrrdlvlresp2;
> + u32 dfitrwrlvldelay0;
> + u32 dfitrwrlvldelay1;
> + u32 dfitrwrlvldelay2;
> + u32 dfitrrdlvldelay0;
> + u32 dfitrrdlvldelay1;
> + u32 dfitrrdlvldelay2;
> + u32 dfitrrdlvlgatedelay0;
> + u32 dfitrrdlvlgatedelay1;
> + u32 dfitrrdlvlgatedelay2;
> + u32 dfitrcmd;
> + u32 reserved14[46];
> + u32 ipvr;
> + u32 iptr;
> +};
> +check_member(rk3368_ddr_pctl, iptr, 0x03fc);
> +
> +struct rk3368_ddrphy {
> + u32 reg[0x100];
> +};
> +check_member(rk3368_ddrphy, reg[0xff], 0x03fc);
> +
> +struct rk3368_msch {
> + u32 coreid;
> + u32 revisionid;
> + u32 ddrconf;
> + u32 ddrtiming;
> + u32 ddrmode;
> + u32 readlatency;
> + u32 reserved1[8];
> + u32 activate;
> + u32 devtodev;
> +};
> +check_member(rk3368_msch, devtodev, 0x003c);
> +
> +/* GRF_SOC_CON0 */
> +enum {
> + NOC_RSP_ERR_STALL = BIT(9),
> + MOBILE_DDR_SEL = BIT(4),
> + DDR0_16BIT_EN = BIT(3),
> + MSCH0_MAINDDR3_DDR3 = BIT(2),
> + MSCH0_MAINPARTIALPOP = BIT(1),
> + UPCTL_C_ACTIVE = BIT(0),
> +};
> +
> +#endif
> diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
> index 1f84ff9..6b6651a 100644
> --- a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
> +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
> @@ -76,8 +76,11 @@ struct rk3368_grf {
> u32 soc_con15;
> u32 soc_con16;
> u32 soc_con17;
> + u32 reserved5[0x6e];
> + u32 ddrc0_con0;
> };
> check_member(rk3368_grf, soc_con17, 0x444);
> +check_member(rk3368_grf, ddrc0_con0, 0x600);
>
> struct rk3368_pmu_grf {
> u32 gpio0a_iomux;
> diff --git a/arch/arm/mach-rockchip/rk3368/Makefile b/arch/arm/mach-rockchip/rk3368/Makefile
> index 0390716..46798c2 100644
> --- a/arch/arm/mach-rockchip/rk3368/Makefile
> +++ b/arch/arm/mach-rockchip/rk3368/Makefile
> @@ -5,5 +5,4 @@
> #
> obj-y += clk_rk3368.o
> obj-y += rk3368.o
> -obj-y += sdram_rk3368.o
> obj-y += syscon_rk3368.o
The current PX5 EVB and Sheep board(they have no spl now) depend on
this sdram_rk3368.c
to get the sdram capacity, and so is the geekbox board.
These boards will be broken when this driver removed.
We got the failed log like this on PX5 EVB:
DRAM: DRAM init failed: -19
initcall sequence 000000002d=378208 failed at call 02023f0 (err=-19)
### ERROR ### Please RESET the board ###
> diff --git a/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c b/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c
> deleted file mode 100644
> index d0d0900..0000000
> --- a/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c
> +++ /dev/null
> @@ -1,60 +0,0 @@
> -/*
> - * (C) Copyright 2016 Rockchip Electronics Co., Ltd.
> - *
> - * SPDX-License-Identifier: GPL-2.0
> - */
> -
> -#include <common.h>
> -#include <dm.h>
> -#include <ram.h>
> -#include <syscon.h>
> -#include <asm/arch/clock.h>
> -#include <asm/arch/grf_rk3368.h>
> -#include <asm/arch/sdram_common.h>
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -struct dram_info {
> - struct ram_info info;
> - struct rk3368_pmu_grf *pmugrf;
> -};
> -
> -static int rk3368_dmc_probe(struct udevice *dev)
> -{
> - struct dram_info *priv = dev_get_priv(dev);
> -
> - priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
> - debug("%s: grf=%p\n", __func__, priv->pmugrf);
> - priv->info.base = CONFIG_SYS_SDRAM_BASE;
> - priv->info.size = rockchip_sdram_size(
> - (phys_addr_t)&priv->pmugrf->os_reg[2]);
> -
> - return 0;
> -}
> -
> -static int rk3368_dmc_get_info(struct udevice *dev, struct ram_info *info)
> -{
> - struct dram_info *priv = dev_get_priv(dev);
> -
> - *info = priv->info;
> -
> - return 0;
> -}
> -
> -static struct ram_ops rk3368_dmc_ops = {
> - .get_info = rk3368_dmc_get_info,
> -};
> -
> -
> -static const struct udevice_id rk3368_dmc_ids[] = {
> - { .compatible = "rockchip,rk3368-dmc" },
> - { }
> -};
> -
> -U_BOOT_DRIVER(dmc_rk3368) = {
> - .name = "rockchip_rk3368_dmc",
> - .id = UCLASS_RAM,
> - .of_match = rk3368_dmc_ids,
> - .ops = &rk3368_dmc_ops,
> - .probe = rk3368_dmc_probe,
> - .priv_auto_alloc_size = sizeof(struct dram_info),
> -};
> diff --git a/doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt b/doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt
> new file mode 100644
> index 0000000..8e7357d
> --- /dev/null
> +++ b/doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt
> @@ -0,0 +1,67 @@
> +RK3368 dynamic memory controller driver
> +=======================================
> +
> +The RK3368 DMC (dynamic memory controller) driver supports setup/initialisation
> +during TPL using configuration data from the DTS (i.e. OF_PLATDATA), based on
> +the following key configuration data:
> + (a) a target-frequency (i.e. operating point) for the memory operation
> + (b) a speed-bin (as defined in JESD-79) for the DDR3 used in hardware
> + (c) a memory-schedule (i.e. mapping from physical addresses to the address
> + pins of the memory bus)
> +
> +Required properties
> +-------------------
> +
> +- compatible: "rockchip,rk3368-dmc"
> +- reg
> + protocol controller (PCTL) address and PHY controller (DDRPHY) address
> +- rockchip,ddr-speed-bin
> + the DDR3 device's speed-bin (as specified according to JESD-79)
> + DDR3_800D (5-5-5)
> + DDR3_800E (6-6-6)
> + DDR3_1066E (6-6-6)
> + DDR3_1066F (7-7-7)
> + DDR3_1066G (8-8-8)
> + DDR3_1333F (7-7-7)
> + DDR3_1333G (8-8-8)
> + DDR3_1333H (9-9-9)
> + DDR3_1333J (10-10-10)
> + DDR3_1600G (8-8-8)
> + DDR3_1600H (9-9-9)
> + DDR3_1600J (10-10-10)
> + DDR3_1600K (11-11-11)
> + DDR3_1866J (10-10-10)
> + DDR3_1866K (11-11-11)
> + DDR3_1866L (12-12-12)
> + DDR3_1866M (13-13-13)
> + DDR3_2133K (11-11-11)
> + DDR3_2133L (12-12-12)
> + DDR3_2133M (13-13-13)
> + DDR3_2133N (14-14-14)
> +- rockchip,ddr-frequency:
> + target DDR clock frequency in Hz (not all frequencies may be supported,
> + as there's some cooperation from the clock-driver required)
> +- rockchip,memory-schedule:
> + controls the decoding of physical addresses to DRAM addressing (i.e. how
> + the physical address maps onto the address pins/chip-select of the device)
> + DMC_MSCH_CBDR: column -> bank -> device -> row
> + DMC_MSCH_CBRD: column -> band -> row -> device
> + DMC_MSCH_CRBD: column -> row -> band -> device
> +
> +Example (for DDR3-1600K and 800MHz)
> +-----------------------------------
> +
> + #include <dt-bindings/memory/rk3368-dmc.h>
> +
> + dmc: dmc at ff610000 {
> + u-boot,dm-pre-reloc;
> + compatible = "rockchip,rk3368-dmc";
> + reg = <0 0xff610000 0 0x400
> + 0 0xff620000 0 0x400>;
> + };
> +
> + &dmc {
> + rockchip,ddr-speed-bin = <DDR3_1600K>;
> + rockchip,ddr-frequency = <800000000>;
> + rockchip,memory-schedule = <DMC_MSCH_CBRD>;
> + };
> diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
> index c409c48..51ae6be 100644
> --- a/drivers/ram/Makefile
> +++ b/drivers/ram/Makefile
> @@ -8,3 +8,5 @@ obj-$(CONFIG_RAM) += ram-uclass.o
> obj-$(CONFIG_SANDBOX) += sandbox_ram.o
> obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o
> obj-$(CONFIG_ARCH_BMIPS) += bmips_ram.o
> +
> +obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
> diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile
> new file mode 100644
> index 0000000..b09d03c
> --- /dev/null
> +++ b/drivers/ram/rockchip/Makefile
> @@ -0,0 +1,7 @@
> +#
> +# Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +
> +obj-$(CONFIG_ROCKCHIP_RK3368) = dmc-rk3368.o
> diff --git a/drivers/ram/rockchip/dmc-rk3368.c b/drivers/ram/rockchip/dmc-rk3368.c
> new file mode 100644
> index 0000000..fea96a5
> --- /dev/null
> +++ b/drivers/ram/rockchip/dmc-rk3368.c
> @@ -0,0 +1,990 @@
> +/*
> + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + */
> +
> +#include <common.h>
> +#include <clk.h>
> +#include <dm.h>
> +#include <dt-bindings/memory/rk3368-dmc.h>
> +#include <dt-structs.h>
> +#include <ram.h>
> +#include <regmap.h>
> +#include <syscon.h>
> +#include <asm/io.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/cru_rk3368.h>
> +#include <asm/arch/grf_rk3368.h>
> +#include <asm/arch/ddr_rk3368.h>
> +#include <asm/arch/sdram.h>
> +#include <asm/arch/sdram_common.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct dram_info {
> + struct ram_info info;
> + struct clk ddr_clk;
> + struct rk3368_cru *cru;
> + struct rk3368_grf *grf;
> + struct rk3368_ddr_pctl *pctl;
> + struct rk3368_ddrphy *phy;
> + struct rk3368_pmu_grf *pmugrf;
> + struct rk3368_msch *msch;
> +};
> +
> +struct rk3368_sdram_params {
> +#if CONFIG_IS_ENABLED(OF_PLATDATA)
> + struct dtd_rockchip_rk3368_dmc of_plat;
> +#endif
> + struct rk3288_sdram_pctl_timing pctl_timing;
> + u32 trefi_mem_ddr3;
> + struct rk3288_sdram_channel chan;
> + struct regmap *map;
> + u32 ddr_freq;
> + u32 memory_schedule;
> + u32 ddr_speed_bin;
> + u32 tfaw_mult;
> +};
> +
> +/* PTCL bits */
> +enum {
> + /* PCTL_DFISTCFG0 */
> + DFI_INIT_START = BIT(0),
> + DFI_DATA_BYTE_DISABLE_EN = BIT(2),
> +
> + /* PCTL_DFISTCFG1 */
> + DFI_DRAM_CLK_SR_EN = BIT(0),
> + DFI_DRAM_CLK_DPD_EN = BIT(1),
> + ODT_LEN_BL8_W_SHIFT = 16,
> +
> + /* PCTL_DFISTCFG2 */
> + DFI_PARITY_INTR_EN = BIT(0),
> + DFI_PARITY_EN = BIT(1),
> +
> + /* PCTL_DFILPCFG0 */
> + TLP_RESP_TIME_SHIFT = 16,
> + LP_SR_EN = BIT(8),
> + LP_PD_EN = BIT(0),
> +
> + /* PCTL_DFIODTCFG */
> + RANK0_ODT_WRITE_SEL = BIT(3),
> + RANK1_ODT_WRITE_SEL = BIT(11),
> +
> + /* PCTL_SCFG */
> + HW_LOW_POWER_EN = BIT(0),
> +
> + /* PCTL_MCMD */
> + START_CMD = BIT(31),
> + MCMD_RANK0 = BIT(20),
> + MCMD_RANK1 = BIT(21),
> + DESELECT_CMD = 0,
> + PREA_CMD,
> + REF_CMD,
> + MRS_CMD,
> + ZQCS_CMD,
> + ZQCL_CMD,
> + RSTL_CMD,
> + MRR_CMD = 8,
> + DPDE_CMD,
> +
> + /* PCTL_POWCTL */
> + POWER_UP_START = BIT(0),
> +
> + /* PCTL_POWSTAT */
> + POWER_UP_DONE = BIT(0),
> +
> + /* PCTL_SCTL */
> + INIT_STATE = 0,
> + CFG_STATE,
> + GO_STATE,
> + SLEEP_STATE,
> + WAKEUP_STATE,
> +
> + /* PCTL_STAT */
> + LP_TRIG_SHIFT = 4,
> + LP_TRIG_MASK = 7,
> + PCTL_STAT_MSK = 7,
> + INIT_MEM = 0,
> + CONFIG,
> + CONFIG_REQ,
> + ACCESS,
> + ACCESS_REQ,
> + LOW_POWER,
> + LOW_POWER_ENTRY_REQ,
> + LOW_POWER_EXIT_REQ,
> +
> + /* PCTL_MCFG */
> + DDR2_DDR3_BL_8 = BIT(0),
> + DDR3_EN = BIT(5),
> + TFAW_TRRD_MULT4 = (0 << 18),
> + TFAW_TRRD_MULT5 = (1 << 18),
> + TFAW_TRRD_MULT6 = (2 << 18),
> +};
> +
> +#define DDR3_MR0_WR(n) \
> + ((n <= 8) ? ((n - 4) << 9) : (((n >> 1) & 0x7) << 9))
> +#define DDR3_MR0_CL(n) \
> + ((((n - 4) & 0x7) << 4) | (((n - 4) & 0x8) >> 2))
> +#define DDR3_MR0_BL8 \
> + (0 << 0)
> +#define DDR3_MR0_DLL_RESET \
> + (1 << 8)
> +#define DDR3_MR1_RTT120OHM \
> + ((0 << 9) | (1 << 6) | (0 << 2))
> +#define DDR3_MR2_TWL(n) \
> + (((n - 5) & 0x7) << 3)
> +
> +
> +#ifdef CONFIG_TPL_BUILD
> +
> +static void ddr_set_noc_spr_err_stall(struct rk3368_grf *grf, bool enable)
> +{
> + if (enable)
> + rk_setreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL);
> + else
> + rk_clrreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL);
> +}
> +
> +static void ddr_set_ddr3_mode(struct rk3368_grf *grf, bool ddr3_mode)
> +{
> + if (ddr3_mode)
> + rk_setreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3);
> + else
> + rk_clrreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3);
> +}
> +
> +static void ddrphy_config(struct rk3368_ddrphy *phy,
> + u32 tcl, u32 tal, u32 tcwl)
> +{
> + int i;
> +
> + /* Set to DDR3 mode */
> + clrsetbits_le32(&phy->reg[1], 0x3, 0x0);
> +
> + /* DDRPHY_REGB: CL, AL */
> + clrsetbits_le32(&phy->reg[0xb], 0xff, tcl << 4 | tal);
> + /* DDRPHY_REGC: CWL */
> + clrsetbits_le32(&phy->reg[0xc], 0x0f, tcwl);
> +
> + /* Update drive-strength */
> + writel(0xcc, &phy->reg[0x11]);
> + writel(0xaa, &phy->reg[0x16]);
> + /*
> + * Update NRCOMP/PRCOMP for all 4 channels (for details of all
> + * affected registers refer to the documentation of DDRPHY_REG20
> + * and DDRPHY_REG21 in the RK3368 TRM.
> + */
> + for (i = 0; i < 4; ++i) {
> + writel(0xcc, &phy->reg[0x20 + i * 0x10]);
> + writel(0x44, &phy->reg[0x21 + i * 0x10]);
> + }
> +
> + /* Enable write-leveling calibration bypass */
> + setbits_le32(&phy->reg[2], BIT(3));
> +}
> +
> +static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
> +{
> + int i;
> +
> + for (i = 0; i < n / sizeof(u32); i++)
> + writel(*src++, dest++);
> +}
> +
> +static void send_command(struct rk3368_ddr_pctl *pctl, u32 rank, u32 cmd)
> +{
> + u32 mcmd = START_CMD | cmd | rank;
> +
> + debug("%s: writing %x to MCMD\n", __func__, mcmd);
> + writel(mcmd, &pctl->mcmd);
> + while (readl(&pctl->mcmd) & START_CMD)
> + /* spin */;
> +}
> +
> +static void send_mrs(struct rk3368_ddr_pctl *pctl,
> + u32 rank, u32 mr_num, u32 mr_data)
> +{
> + u32 mcmd = START_CMD | MRS_CMD | rank | (mr_num << 17) | (mr_data << 4);
> +
> + debug("%s: writing %x to MCMD\n", __func__, mcmd);
> + writel(mcmd, &pctl->mcmd);
> + while (readl(&pctl->mcmd) & START_CMD)
> + /* spin */;
> +}
> +
> +static int memory_init(struct rk3368_ddr_pctl *pctl,
> + struct rk3368_sdram_params *params)
> +{
> + u32 mr[4];
> + const ulong timeout_ms = 500;
> + ulong tmp;
> +
> + /*
> + * Power up DRAM by DDR_PCTL_POWCTL[0] register of PCTL and
> + * wait power up DRAM finish with DDR_PCTL_POWSTAT[0] register
> + * of PCTL.
> + */
> + writel(POWER_UP_START, &pctl->powctl);
> +
> + tmp = get_timer(0);
> + do {
> + if (get_timer(tmp) > timeout_ms) {
> + error("%s: POWER_UP_START did not complete in %ld ms\n",
> + __func__, timeout_ms);
> + return -ETIME;
> + }
> + } while (!(readl(&pctl->powstat) & POWER_UP_DONE));
> +
> + /* Configure MR0 through MR3 */
> + mr[0] = DDR3_MR0_WR(params->pctl_timing.twr) |
> + DDR3_MR0_CL(params->pctl_timing.tcl) |
> + DDR3_MR0_DLL_RESET;
> + mr[1] = DDR3_MR1_RTT120OHM;
> + mr[2] = DDR3_MR2_TWL(params->pctl_timing.tcwl);
> + mr[3] = 0;
> +
> + /*
> + * Also see RK3368 Technical Reference Manual:
> + * "16.6.2 Initialization (DDR3 Initialization Sequence)"
> + */
> + send_command(pctl, MCMD_RANK0 | MCMD_RANK1, DESELECT_CMD);
> + udelay(1);
> + send_command(pctl, MCMD_RANK0 | MCMD_RANK1, PREA_CMD);
> + send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 2, mr[2]);
> + send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 3, mr[3]);
> + send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 1, mr[1]);
> + send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 0, mr[0]);
> + send_command(pctl, MCMD_RANK0 | MCMD_RANK1, ZQCL_CMD);
> +
> + return 0;
> +}
> +
> +static void move_to_config_state(struct rk3368_ddr_pctl *pctl)
> +{
> + /*
> + * Also see RK3368 Technical Reference Manual:
> + * "16.6.1 State transition of PCTL (Moving to Config State)"
> + */
> + u32 state = readl(&pctl->stat) & PCTL_STAT_MSK;
> +
> + switch (state) {
> + case LOW_POWER:
> + writel(WAKEUP_STATE, &pctl->sctl);
> + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
> + /* spin */;
> +
> + /* fall-through */
> + case ACCESS:
> + case INIT_MEM:
> + writel(CFG_STATE, &pctl->sctl);
> + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
> + /* spin */;
> + break;
> +
> + case CONFIG:
> + return;
> +
> + default:
> + break;
> + }
> +}
> +
> +static void move_to_access_state(struct rk3368_ddr_pctl *pctl)
> +{
> + /*
> + * Also see RK3368 Technical Reference Manual:
> + * "16.6.1 State transition of PCTL (Moving to Access State)"
> + */
> + u32 state = readl(&pctl->stat) & PCTL_STAT_MSK;
> +
> + switch (state) {
> + case LOW_POWER:
> + if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) &
> + LP_TRIG_MASK) == 1)
> + return;
> +
> + writel(WAKEUP_STATE, &pctl->sctl);
> + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
> + /* spin */;
> +
> + /* fall-through */
> + case INIT_MEM:
> + writel(CFG_STATE, &pctl->sctl);
> + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
> + /* spin */;
> +
> + /* fall-through */
> + case CONFIG:
> + writel(GO_STATE, &pctl->sctl);
> + while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG)
> + /* spin */;
> + break;
> +
> + case ACCESS:
> + return;
> +
> + default:
> + break;
> + }
> +}
> +
> +static void ddrctl_reset(struct rk3368_cru *cru)
> +{
> + const u32 ctl_reset = BIT(3) | BIT(2);
> + const u32 phy_reset = BIT(1) | BIT(0);
> +
> + rk_setreg(&cru->softrst_con[10], ctl_reset | phy_reset);
> + udelay(1);
> + rk_clrreg(&cru->softrst_con[10], ctl_reset | phy_reset);
> +}
> +
> +static void ddrphy_reset(struct rk3368_ddrphy *ddrphy)
> +{
> + clrbits_le32(&ddrphy->reg[0], BIT(3) | BIT(2));
> + udelay(1);
> + setbits_le32(&ddrphy->reg[0], BIT(3) | BIT(2));
> +}
> +
> +static void ddrphy_config_delays(struct rk3368_ddrphy *ddrphy, u32 freq)
> +{
> + u32 dqs_dll_delay;
> +
> + setbits_le32(&ddrphy->reg[0x13], BIT(4));
> + clrbits_le32(&ddrphy->reg[0x14], BIT(3));
> +
> + setbits_le32(&ddrphy->reg[0x26], BIT(4));
> + clrbits_le32(&ddrphy->reg[0x27], BIT(3));
> +
> + setbits_le32(&ddrphy->reg[0x36], BIT(4));
> + clrbits_le32(&ddrphy->reg[0x37], BIT(3));
> +
> + setbits_le32(&ddrphy->reg[0x46], BIT(4));
> + clrbits_le32(&ddrphy->reg[0x47], BIT(3));
> +
> + setbits_le32(&ddrphy->reg[0x56], BIT(4));
> + clrbits_le32(&ddrphy->reg[0x57], BIT(3));
> +
> + if (freq <= 400000000)
> + setbits_le32(&ddrphy->reg[0xa4], 0x1f);
> + else
> + clrbits_le32(&ddrphy->reg[0xa4], 0x1f);
> +
> + if (freq < 681000000)
> + dqs_dll_delay = 3; /* 67.5 degree delay */
> + else
> + dqs_dll_delay = 2; /* 45 degree delay */
> +
> + writel(dqs_dll_delay, &ddrphy->reg[0x28]);
> + writel(dqs_dll_delay, &ddrphy->reg[0x38]);
> + writel(dqs_dll_delay, &ddrphy->reg[0x48]);
> + writel(dqs_dll_delay, &ddrphy->reg[0x58]);
> +}
> +
> +static int dfi_cfg(struct rk3368_ddr_pctl *pctl)
> +{
> + const ulong timeout_ms = 200;
> + ulong tmp;
> +
> + writel(DFI_DATA_BYTE_DISABLE_EN, &pctl->dfistcfg0);
> +
> + writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN,
> + &pctl->dfistcfg1);
> + writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2);
> + writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN,
> + &pctl->dfilpcfg0);
> +
> + writel(1, &pctl->dfitphyupdtype0);
> +
> + writel(0x1f, &pctl->dfitphyrdlat);
> + writel(0, &pctl->dfitphywrdata);
> + writel(0, &pctl->dfiupdcfg); /* phyupd and ctrlupd disabled */
> +
> + setbits_le32(&pctl->dfistcfg0, DFI_INIT_START);
> +
> + tmp = get_timer(0);
> + do {
> + if (get_timer(tmp) > timeout_ms) {
> + error("%s: DFI init did not complete within %ld ms\n",
> + __func__, timeout_ms);
> + return -ETIME;
> + }
> + } while ((readl(&pctl->dfiststat0) & 1) == 0);
> +
> + return 0;
> +}
> +
> +static inline u32 ps_to_tCK(const u32 ps, const ulong freq)
> +{
> + const ulong MHz = 1000000;
> + return DIV_ROUND_UP(ps * freq, 1000000 * MHz);
> +}
> +
> +static inline u32 ns_to_tCK(const u32 ns, const ulong freq)
> +{
> + return ps_to_tCK(ns * 1000, freq);
> +}
> +
> +static inline u32 tCK_to_ps(const ulong tCK, const ulong freq)
> +{
> + const ulong MHz = 1000000;
> + return DIV_ROUND_UP(tCK * 1000000 * MHz, freq);
> +}
> +
> +static int pctl_calc_timings(struct rk3368_sdram_params *params,
> + ulong freq)
> +{
> + struct rk3288_sdram_pctl_timing *pctl_timing = ¶ms->pctl_timing;
> + const ulong MHz = 1000000;
> + u32 tccd;
> + u32 tfaw_as_ps;
> +
> + if (params->ddr_speed_bin != DDR3_1600K) {
> + error("%s: unimplemented DDR3 speed bin %d\n",
> + __func__, params->ddr_speed_bin);
> + return -1;
> + }
> +
> + /* PCTL is clocked at 1/2 the DRAM clock; err on the side of caution */
> + pctl_timing->togcnt1u = DIV_ROUND_UP(freq, 2 * MHz);
> + pctl_timing->togcnt100n = DIV_ROUND_UP(freq / 10, 2 * MHz);
> +
> + pctl_timing->tinit = 200; /* 200 usec */
> + pctl_timing->trsth = 500; /* 500 usec */
> + pctl_timing->trefi = 78; /* 7.8usec = 78 * 100ns */
> + params->trefi_mem_ddr3 = ns_to_tCK(pctl_timing->trefi * 100, freq);
> +
> + if (freq <= (400 * MHz)) {
> + pctl_timing->tcl = 6;
> + pctl_timing->tcwl = 10;
> + } else if (freq <= (533 * MHz)) {
> + pctl_timing->tcl = 8;
> + pctl_timing->tcwl = 6;
> + } else if (freq <= (666 * MHz)) {
> + pctl_timing->tcl = 10;
> + pctl_timing->tcwl = 7;
> + } else {
> + pctl_timing->tcl = 11;
> + pctl_timing->tcwl = 8;
> + }
> +
> + pctl_timing->tmrd = 4; /* 4 tCK (all speed bins) */
> + pctl_timing->trfc = ns_to_tCK(350, freq); /* tRFC: 350 (max) @ 8GBit */
> + pctl_timing->trp = max(4u, ps_to_tCK(13750, freq));
> + /*
> + * JESD-79:
> + * READ to WRITE Command Delay = RL + tCCD / 2 + 2tCK - WL
> + */
> + tccd = 4;
> + pctl_timing->trtw = pctl_timing->tcl + tccd/2 + 2 - pctl_timing->tcwl;
> + pctl_timing->tal = 0;
> + pctl_timing->tras = ps_to_tCK(35000, freq);
> + pctl_timing->trc = ps_to_tCK(48750, freq);
> + pctl_timing->trcd = ps_to_tCK(13750, freq);
> + pctl_timing->trrd = max(4u, ps_to_tCK(7500, freq));
> + pctl_timing->trtp = max(4u, ps_to_tCK(7500, freq));
> + pctl_timing->twr = ps_to_tCK(15000, freq);
> + /* The DDR3 mode-register does only support even values for tWR > 8. */
> + if (pctl_timing->twr > 8)
> + pctl_timing->twr = (pctl_timing->twr + 1) & ~1;
> + pctl_timing->twtr = max(4u, ps_to_tCK(7500, freq));
> + pctl_timing->texsr = 512; /* tEXSR(max) is tDLLLK */
> + pctl_timing->txp = max(3u, ps_to_tCK(6000, freq));
> + pctl_timing->txpdll = max(10u, ps_to_tCK(24000, freq));
> + pctl_timing->tzqcs = max(64u, ps_to_tCK(80000, freq));
> + pctl_timing->tzqcsi = 10000; /* as used by Rockchip */
> + pctl_timing->tdqs = 1; /* fixed for DDR3 */
> + pctl_timing->tcksre = max(5u, ps_to_tCK(10000, freq));
> + pctl_timing->tcksrx = max(5u, ps_to_tCK(10000, freq));
> + pctl_timing->tcke = max(3u, ps_to_tCK(5000, freq));
> + pctl_timing->tmod = max(12u, ps_to_tCK(15000, freq));
> + pctl_timing->trstl = ns_to_tCK(100, freq);
> + pctl_timing->tzqcl = max(256u, ps_to_tCK(320000, freq)); /* tZQoper */
> + pctl_timing->tmrr = 0;
> + pctl_timing->tckesr = pctl_timing->tcke + 1; /* JESD-79: tCKE + 1tCK */
> + pctl_timing->tdpd = 0; /* RK3368 TRM: "allowed values for DDR3: 0" */
> +
> +
> + /*
> + * The controller can represent tFAW as 4x, 5x or 6x tRRD only.
> + * We want to use the smallest multiplier that satisfies the tFAW
> + * requirements of the given speed-bin. If necessary, we stretch out
> + * tRRD to allow us to operate on a 6x multiplier for tFAW.
> + */
> + tfaw_as_ps = 40000; /* 40ns: tFAW for DDR3-1600K, 2KB page-size */
> + if (tCK_to_ps(pctl_timing->trrd * 6, freq) < tfaw_as_ps) {
> + /* If tFAW is > 6 x tRRD, we need to stretch tRRD */
> + pctl_timing->trrd = ps_to_tCK(DIV_ROUND_UP(40000, 6), freq);
> + params->tfaw_mult = TFAW_TRRD_MULT6;
> + } else if (tCK_to_ps(pctl_timing->trrd * 5, freq) < tfaw_as_ps) {
> + params->tfaw_mult = TFAW_TRRD_MULT6;
> + } else if (tCK_to_ps(pctl_timing->trrd * 4, freq) < tfaw_as_ps) {
> + params->tfaw_mult = TFAW_TRRD_MULT5;
> + } else {
> + params->tfaw_mult = TFAW_TRRD_MULT4;
> + }
> +
> + return 0;
> +}
> +
> +static void pctl_cfg(struct rk3368_ddr_pctl *pctl,
> + struct rk3368_sdram_params *params,
> + struct rk3368_grf *grf)
> +{
> + /* Configure PCTL timing registers */
> + params->pctl_timing.trefi |= BIT(31); /* see PCTL_TREFI */
> + copy_to_reg(&pctl->togcnt1u, ¶ms->pctl_timing.togcnt1u,
> + sizeof(params->pctl_timing));
> + writel(params->trefi_mem_ddr3, &pctl->trefi_mem_ddr3);
> +
> + /* Set up ODT write selector and ODT write length */
> + writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL), &pctl->dfiodtcfg);
> + writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1);
> +
> + /* Set up the CL/CWL-dependent timings of DFI */
> + writel((params->pctl_timing.tcl - 1) / 2 - 1, &pctl->dfitrddataen);
> + writel((params->pctl_timing.tcwl - 1) / 2 - 1, &pctl->dfitphywrlat);
> +
> + /* DDR3 */
> + writel(params->tfaw_mult | DDR3_EN | DDR2_DDR3_BL_8, &pctl->mcfg);
> + writel(0x001c0004, &grf->ddrc0_con0);
> +
> + setbits_le32(&pctl->scfg, HW_LOW_POWER_EN);
> +}
> +
> +static int ddrphy_data_training(struct rk3368_ddr_pctl *pctl,
> + struct rk3368_ddrphy *ddrphy)
> +{
> + const u32 trefi = readl(&pctl->trefi);
> + const ulong timeout_ms = 500;
> + ulong tmp;
> +
> + /* disable auto-refresh */
> + writel(0 | BIT(31), &pctl->trefi);
> +
> + clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x20);
> + clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x21);
> +
> + tmp = get_timer(0);
> + do {
> + if (get_timer(tmp) > timeout_ms) {
> + error("%s: did not complete within %ld ms\n",
> + __func__, timeout_ms);
> + return -ETIME;
> + }
> + } while ((readl(&ddrphy->reg[0xff]) & 0xf) != 0xf);
> +
> + send_command(pctl, MCMD_RANK0 | MCMD_RANK1, PREA_CMD);
> + clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x20);
> + /* resume auto-refresh */
> + writel(trefi | BIT(31), &pctl->trefi);
> +
> + return 0;
> +}
> +
> +static int sdram_col_row_detect(struct udevice *dev)
> +{
> + struct dram_info *priv = dev_get_priv(dev);
> + struct rk3368_sdram_params *params = dev_get_platdata(dev);
> + struct rk3368_ddr_pctl *pctl = priv->pctl;
> + struct rk3368_msch *msch = priv->msch;
> + const u32 test_pattern = 0x5aa5f00f;
> + int row, col;
> + uintptr_t addr;
> +
> + move_to_config_state(pctl);
> + writel(6, &msch->ddrconf);
> + move_to_access_state(pctl);
> +
> + /* Detect col */
> + for (col = 11; col >= 9; col--) {
> + writel(0, CONFIG_SYS_SDRAM_BASE);
> + addr = CONFIG_SYS_SDRAM_BASE +
> + (1 << (col + params->chan.bw - 1));
> + writel(test_pattern, addr);
> + if ((readl(addr) == test_pattern) &&
> + (readl(CONFIG_SYS_SDRAM_BASE) == 0))
> + break;
> + }
> +
> + if (col == 8) {
> + error("%s: col detect error\n", __func__);
> + return -EINVAL;
> + }
> +
> + move_to_config_state(pctl);
> + writel(15, &msch->ddrconf);
> + move_to_access_state(pctl);
> +
> + /* Detect row*/
> + for (row = 16; row >= 12; row--) {
> + writel(0, CONFIG_SYS_SDRAM_BASE);
> + addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
> + writel(test_pattern, addr);
> + if ((readl(addr) == test_pattern) &&
> + (readl(CONFIG_SYS_SDRAM_BASE) == 0))
> + break;
> + }
> +
> + if (row == 11) {
> + error("%s: row detect error\n", __func__);
> + return -EINVAL;
> + }
> +
> + /* Record results */
> + debug("%s: col %d, row %d\n", __func__, col, row);
> + params->chan.col = col;
> + params->chan.cs0_row = row;
> + params->chan.cs1_row = row;
> + params->chan.row_3_4 = 0;
> +
> + return 0;
> +}
> +
> +static int msch_niu_config(struct rk3368_msch *msch,
> + struct rk3368_sdram_params *params)
> +{
> + int i;
> + const u8 cols = params->chan.col - ((params->chan.bw == 2) ? 0 : 1);
> + const u8 rows = params->chan.cs0_row;
> +
> + /*
> + * The DDR address-translation table always assumes a 32bit
> + * bus and the comparison below takes care of adjusting for
> + * a 16bit bus (i.e. one column-address is consumed).
> + */
> + const struct {
> + u8 rows;
> + u8 columns;
> + u8 type;
> + } ddrconf_table[] = {
> + /*
> + * C-B-R-D patterns are first. For these we require an
> + * exact match for the columns and rows (as there's
> + * one entry per possible configuration).
> + */
> + [0] = { .rows = 13, .columns = 10, .type = DMC_MSCH_CBRD },
> + [1] = { .rows = 14, .columns = 10, .type = DMC_MSCH_CBRD },
> + [2] = { .rows = 15, .columns = 10, .type = DMC_MSCH_CBRD },
> + [3] = { .rows = 16, .columns = 10, .type = DMC_MSCH_CBRD },
> + [4] = { .rows = 14, .columns = 11, .type = DMC_MSCH_CBRD },
> + [5] = { .rows = 15, .columns = 11, .type = DMC_MSCH_CBRD },
> + [6] = { .rows = 16, .columns = 11, .type = DMC_MSCH_CBRD },
> + [7] = { .rows = 13, .columns = 9, .type = DMC_MSCH_CBRD },
> + [8] = { .rows = 14, .columns = 9, .type = DMC_MSCH_CBRD },
> + [9] = { .rows = 15, .columns = 9, .type = DMC_MSCH_CBRD },
> + [10] = { .rows = 16, .columns = 9, .type = DMC_MSCH_CBRD },
> + /*
> + * 11 through 13 are C-R-B-D patterns. These are
> + * matched for an exact number of columns and to
> + * ensure that the hardware uses at least as many rows
> + * as the pattern requires (i.e. we make sure that
> + * there's no gaps up until we hit the device/chip-select;
> + * however, these patterns can accept up to 16 rows,
> + * as the row-address continues right after the CS
> + * switching)
> + */
> + [11] = { .rows = 15, .columns = 10, .type = DMC_MSCH_CRBD },
> + [12] = { .rows = 14, .columns = 11, .type = DMC_MSCH_CRBD },
> + [13] = { .rows = 13, .columns = 10, .type = DMC_MSCH_CRBD },
> + /*
> + * 14 and 15 are catch-all variants using a C-B-D-R
> + * scheme (i.e. alternating the chip-select every time
> + * C-B overflows) and stuffing the remaining C-bits
> + * into the top. Matching needs to make sure that the
> + * number of columns is either an exact match (i.e. we
> + * can use less the the maximum number of rows) -or-
> + * that the columns exceed what is given in this table
> + * and the rows are an exact match (in which case the
> + * remaining C-bits will be stuffed onto the top after
> + * the device/chip-select switches).
> + */
> + [14] = { .rows = 16, .columns = 10, .type = DMC_MSCH_CBDR },
> + [15] = { .rows = 16, .columns = 9, .type = DMC_MSCH_CBDR },
> + };
> +
> + /*
> + * For C-B-R-D, we need an exact match (i.e. both for the number of
> + * columns and rows), while for C-B-D-R, only the the number of
> + * columns needs to match.
> + */
> + for (i = 0; i < ARRAY_SIZE(ddrconf_table); i++) {
> + bool match = false;
> +
> + /* If this entry if for a different matcher, then skip it */
> + if (ddrconf_table[i].type != params->memory_schedule)
> + continue;
> +
> + /*
> + * Match according to the rules (exact/inexact/at-least)
> + * documented in the ddrconf_table above.
> + */
> + switch (params->memory_schedule) {
> + case DMC_MSCH_CBRD:
> + match = (ddrconf_table[i].columns == cols) &&
> + (ddrconf_table[i].rows == rows);
> + break;
> +
> + case DMC_MSCH_CRBD:
> + match = (ddrconf_table[i].columns == cols) &&
> + (ddrconf_table[i].rows <= rows);
> + break;
> +
> + case DMC_MSCH_CBDR:
> + match = (ddrconf_table[i].columns == cols) ||
> + ((ddrconf_table[i].columns <= cols) &&
> + (ddrconf_table[i].rows == rows));
> + break;
> +
> + default:
> + break;
> + }
> +
> + if (match) {
> + debug("%s: setting ddrconf 0x%x\n", __func__, i);
> + writel(i, &msch->ddrconf);
> + return 0;
> + }
> + }
> +
> + error("%s: ddrconf (NIU config) not found\n", __func__);
> + return -EINVAL;
> +}
> +
> +static void dram_all_config(struct udevice *dev)
> +{
> + struct dram_info *priv = dev_get_priv(dev);
> + struct rk3368_pmu_grf *pmugrf = priv->pmugrf;
> + struct rk3368_sdram_params *params = dev_get_platdata(dev);
> + const struct rk3288_sdram_channel *info = ¶ms->chan;
> + u32 sys_reg = 0;
> + const int chan = 0;
> +
> + sys_reg |= DDR3 << SYS_REG_DDRTYPE_SHIFT;
> + sys_reg |= 0 << SYS_REG_NUM_CH_SHIFT;
> +
> + sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan);
> + sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan);
> + sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan);
> + sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan);
> + sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan);
> + sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan);
> + sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan);
> + sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan);
> + sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan);
> +
> + writel(sys_reg, &pmugrf->os_reg[2]);
> +}
> +
> +static int setup_sdram(struct udevice *dev)
> +{
> + struct dram_info *priv = dev_get_priv(dev);
> + struct rk3368_sdram_params *params = dev_get_platdata(dev);
> +
> + struct rk3368_ddr_pctl *pctl = priv->pctl;
> + struct rk3368_ddrphy *ddrphy = priv->phy;
> + struct rk3368_cru *cru = priv->cru;
> + struct rk3368_grf *grf = priv->grf;
> + struct rk3368_msch *msch = priv->msch;
> +
> + int ret;
> +
> + /* The input clock (i.e. DPLL) needs to be 2x the DRAM frequency */
> + ret = clk_set_rate(&priv->ddr_clk, 2 * params->ddr_freq);
> + if (ret < 0) {
> + debug("%s: could not set DDR clock: %d\n", __func__, ret);
> + return ret;
> + }
> +
> + /* Update the read-latency for the RK3368 */
> + writel(0x32, &msch->readlatency);
> +
> + /* Initialise the DDR PCTL and DDR PHY */
> + ddrctl_reset(cru);
> + ddrphy_reset(ddrphy);
> + ddrphy_config_delays(ddrphy, params->ddr_freq);
> + dfi_cfg(pctl);
> + /* Configure relative system information of grf_ddrc0_con0 register */
> + ddr_set_ddr3_mode(grf, true);
> + ddr_set_noc_spr_err_stall(grf, true);
> + /* Calculate timings */
> + pctl_calc_timings(params, params->ddr_freq);
> + /* Initialise the device timings in protocol controller */
> + pctl_cfg(pctl, params, grf);
> + /* Configure AL, CL ... information of PHY registers */
> + ddrphy_config(ddrphy,
> + params->pctl_timing.tcl,
> + params->pctl_timing.tal,
> + params->pctl_timing.tcwl);
> +
> + /* Initialize DRAM and configure with mode-register values */
> + ret = memory_init(pctl, params);
> + if (ret)
> + goto error;
> +
> + move_to_config_state(pctl);
> + /* Perform data-training */
> + ddrphy_data_training(pctl, ddrphy);
> + move_to_access_state(pctl);
> +
> + /* TODO(prt): could detect rank in training... */
> + params->chan.rank = 2;
> + /* TODO(prt): bus width is not auto-detected (yet)... */
> + params->chan.bw = 2; /* 32bit wide bus */
> + params->chan.dbw = params->chan.dbw; /* 32bit wide bus */
> +
> + /* DDR3 is always 8 bank */
> + params->chan.bk = 3;
> + /* Detect col and row number */
> + ret = sdram_col_row_detect(dev);
> + if (ret)
> + goto error;
> +
> + /* Configure NIU DDR configuration */
> + ret = msch_niu_config(msch, params);
> + if (ret)
> + goto error;
> +
> + /* set up OS_REG to communicate w/ next stage and OS */
> + dram_all_config(dev);
> +
> + return 0;
> +
> +error:
> + printf("DRAM init failed!\n");
> + hang();
> +}
> +#endif
> +
> +static int rk3368_dmc_ofdata_to_platdata(struct udevice *dev)
> +{
> + int ret = 0;
> +
> +#if !CONFIG_IS_ENABLED(OF_PLATDATA)
> + struct rk3368_sdram_params *plat = dev_get_platdata(dev);
> +
> + ret = regmap_init_mem(dev, &plat->map);
> + if (ret)
> + return ret;
> +#endif
> +
> + return ret;
> +}
> +
> +#if CONFIG_IS_ENABLED(OF_PLATDATA)
> +static int conv_of_platdata(struct udevice *dev)
> +{
> + struct rk3368_sdram_params *plat = dev_get_platdata(dev);
> + struct dtd_rockchip_rk3368_dmc *of_plat = &plat->of_plat;
> + int ret;
> +
> + plat->ddr_freq = of_plat->rockchip_ddr_frequency;
> + plat->ddr_speed_bin = of_plat->rockchip_ddr_speed_bin;
> + plat->memory_schedule = of_plat->rockchip_memory_schedule;
> +
> + ret = regmap_init_mem_platdata(dev, of_plat->reg,
> + ARRAY_SIZE(of_plat->reg) / 2,
> + &plat->map);
> + if (ret)
> + return ret;
> +
> + return 0;
> +}
> +#endif
> +
> +static int rk3368_dmc_probe(struct udevice *dev)
> +{
> +#ifdef CONFIG_TPL_BUILD
> + struct rk3368_sdram_params *plat = dev_get_platdata(dev);
> + struct rk3368_ddr_pctl *pctl;
> + struct rk3368_ddrphy *ddrphy;
> + struct rk3368_cru *cru;
> + struct rk3368_grf *grf;
> + struct rk3368_msch *msch;
> + int ret;
> + struct udevice *dev_clk;
> +#endif
> + struct dram_info *priv = dev_get_priv(dev);
> +
> +#if CONFIG_IS_ENABLED(OF_PLATDATA)
> + ret = conv_of_platdata(dev);
> + if (ret)
> + return ret;
> +#endif
> +
> + priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
> + debug("%s: pmugrf=%p\n", __func__, priv->pmugrf);
> +
> +#ifdef CONFIG_TPL_BUILD
> + pctl = regmap_get_range(plat->map, 0);
> + ddrphy = regmap_get_range(plat->map, 1);
> + msch = syscon_get_first_range(ROCKCHIP_SYSCON_MSCH);
> + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
> +
> + priv->pctl = pctl;
> + priv->phy = ddrphy;
> + priv->msch = msch;
> + priv->grf = grf;
> +
> + ret = rockchip_get_clk(&dev_clk);
> + if (ret)
> + return ret;
> + priv->ddr_clk.id = CLK_DDR;
> + ret = clk_request(dev_clk, &priv->ddr_clk);
> + if (ret)
> + return ret;
> +
> + cru = rockchip_get_cru();
> + priv->cru = cru;
> + if (IS_ERR(priv->cru))
> + return PTR_ERR(priv->cru);
> +
> + ret = setup_sdram(dev);
> + if (ret)
> + return ret;
> +#endif
> +
> + priv->info.base = 0;
> + priv->info.size =
> + rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg[2]);
> +
> + /*
> + * we use the 0x00000000~0xfdffffff space since 0xff000000~0xffffffff
> + * is SoC register space (i.e. reserved), and 0xfe000000~0xfeffffff is
> + * inaccessible for some IP controller.
> + */
> + priv->info.size = min(priv->info.size, (size_t)0xfe000000);
> +
> + return 0;
> +}
> +
> +static int rk3368_dmc_get_info(struct udevice *dev, struct ram_info *info)
> +{
> + struct dram_info *priv = dev_get_priv(dev);
> +
> + *info = priv->info;
> + return 0;
> +}
> +
> +static struct ram_ops rk3368_dmc_ops = {
> + .get_info = rk3368_dmc_get_info,
> +};
> +
> +
> +static const struct udevice_id rk3368_dmc_ids[] = {
> + { .compatible = "rockchip,rk3368-dmc" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(dmc_rk3368) = {
> + .name = "rockchip_rk3368_dmc",
> + .id = UCLASS_RAM,
> + .of_match = rk3368_dmc_ids,
> + .ops = &rk3368_dmc_ops,
> + .probe = rk3368_dmc_probe,
> + .priv_auto_alloc_size = sizeof(struct dram_info),
> + .ofdata_to_platdata = rk3368_dmc_ofdata_to_platdata,
> + .probe = rk3368_dmc_probe,
> + .priv_auto_alloc_size = sizeof(struct dram_info),
> + .platdata_auto_alloc_size = sizeof(struct rk3368_sdram_params),
> +};
> diff --git a/include/dt-bindings/memory/rk3368-dmc.h b/include/dt-bindings/memory/rk3368-dmc.h
> new file mode 100644
> index 0000000..b06ffde
> --- /dev/null
> +++ b/include/dt-bindings/memory/rk3368-dmc.h
> @@ -0,0 +1,30 @@
> +#ifndef DT_BINDINGS_RK3368_DMC_H
> +#define DT_BINDINGS_RK3368_DMC_H
> +
> +#define DMC_MSCH_CBDR 0x0
> +#define DMC_MSCH_CBRD 0x1
> +#define DMC_MSCH_CRBD 0x2
> +
> +#define DDR3_800D 0
> +#define DDR3_800E 1
> +#define DDR3_1066E 2
> +#define DDR3_1066F 3
> +#define DDR3_1066G 4
> +#define DDR3_1333F 5
> +#define DDR3_1333G 6
> +#define DDR3_1333H 7
> +#define DDR3_1333J 8
> +#define DDR3_1600G 9
> +#define DDR3_1600H 10
> +#define DDR3_1600J 11
> +#define DDR3_1600K 12
> +#define DDR3_1866J 13
> +#define DDR3_1866K 14
> +#define DDR3_1866L 15
> +#define DDR3_1866M 16
> +#define DDR3_2133K 17
> +#define DDR3_2133L 18
> +#define DDR3_2133M 19
> +#define DDR3_2133N 20
> +
> +#endif
^ permalink raw reply [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 50/66] rockchip: rk3368: add DRAM controller driver with DRAM initialisation
2017-08-02 10:06 ` Andy Yan
@ 2017-08-02 10:59 ` Dr. Philipp Tomsich
2017-08-02 12:09 ` Andy Yan
0 siblings, 1 reply; 95+ messages in thread
From: Dr. Philipp Tomsich @ 2017-08-02 10:59 UTC (permalink / raw)
To: u-boot
Andy,
The functionality of the new driver should be equivalent for the non-TPL case.
All the code from the original driver is still present in the new driver for non-TPL
(see rk3368_dmc_probe).
Seeing that -19 is -ENODEV, I suspect that something went wrong in the DM
binding/probing: did you set 'status = “okay”’ for the DMC?
Regards,
Phil.
> On 02 Aug 2017, at 12:06, Andy Yan <andy.yan@rock-chips.com> wrote:
>
> Hi Philipp:
>
>
> On 2017年07月29日 03:22, Philipp Tomsich wrote:
>> This adds a DRAM controller driver for the RK3368 and places it in
>> drivers/ram/rockchip (where the other DM-enabled DRAM controller
>> drivers for rockchip devices should also be moved eventually).
>>
>> At this stage, only the following feature-set is supported:
>> - DDR3
>> - 32-bit configuration (i.e. fully populated)
>> - dual-rank (i.e. no auto-detection of ranks)
>> - DDR3-1600K speed-bin
>>
>> This driver expects to run from a TPL stage that will later return to
>> the RK3368 BROM. It communicates with later stages through the
>> os_reg2 in the pmugrf (i.e. using the same mechanism as Rockchip's DDR
>> init code).
>>
>> Unlike other DMC drivers for RK32xx and RK33xx parts, the required
>> timings are calculated within the driver based on a target frequency
>> and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this
>> time).
>>
>> The RK3368 also has the DDRC0_CON0 (DDR ch. 0, control-register 0)
>> register for controlling the operation of its (single-channel) DRAM
>> controller in the GRF block. This provides for selecting DDR3, mobile
>> DDR modes, and control low-power operation.
>> As part of this change, DDRC0_CON0 is also added to the GRF structure
>> definition (at offset 0x600).
>>
>> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>>
>> Reviewed-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> Changes in v3:
>> - correctly states the location of the driver in the commit message
>>
>> Changes in v2: None
>>
>> arch/arm/include/asm/arch-rockchip/ddr_rk3368.h | 187 ++++
>> arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 3 +
>> arch/arm/mach-rockchip/rk3368/Makefile | 1 -
>> arch/arm/mach-rockchip/rk3368/sdram_rk3368.c | 60 --
>> .../clock/rockchip,rk3368-dmc.txt | 67 ++
>> drivers/ram/Makefile | 2 +
>> drivers/ram/rockchip/Makefile | 7 +
>> drivers/ram/rockchip/dmc-rk3368.c | 990 +++++++++++++++++++++
>> include/dt-bindings/memory/rk3368-dmc.h | 30 +
>> 9 files changed, 1286 insertions(+), 61 deletions(-)
>> create mode 100644 arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
>> delete mode 100644 arch/arm/mach-rockchip/rk3368/sdram_rk3368.c
>> create mode 100644 doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt
>> create mode 100644 drivers/ram/rockchip/Makefile
>> create mode 100644 drivers/ram/rockchip/dmc-rk3368.c
>> create mode 100644 include/dt-bindings/memory/rk3368-dmc.h
>>
>> diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h b/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
>> new file mode 100644
>> index 0000000..4e2b233
>> --- /dev/null
>> +++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
>> @@ -0,0 +1,187 @@
>> +/*
>> + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
>> + *
>> + * SPDX-License-Identifier: GPL-2.0
>> + */
>> +
>> +#ifndef __ASM_ARCH_DDR_RK3368_H__
>> +#define __ASM_ARCH_DDR_RK3368_H__
>> +
>> +/*
>> + * The RK3368 DDR PCTL differs from the incarnation in the RK3288 only
>> + * in a few details. Most notably, it has an additional field to track
>> + * tREFI in controller cycles (i.e. trefi_mem_ddr3).
>> + */
>> +struct rk3368_ddr_pctl {
>> + u32 scfg;
>> + u32 sctl;
>> + u32 stat;
>> + u32 intrstat;
>> + u32 reserved0[12];
>> + u32 mcmd;
>> + u32 powctl;
>> + u32 powstat;
>> + u32 cmdtstat;
>> + u32 cmdtstaten;
>> + u32 reserved1[3];
>> + u32 mrrcfg0;
>> + u32 mrrstat0;
>> + u32 mrrstat1;
>> + u32 reserved2[4];
>> + u32 mcfg1;
>> + u32 mcfg;
>> + u32 ppcfg;
>> + u32 mstat;
>> + u32 lpddr2zqcfg;
>> + u32 reserved3;
>> + u32 dtupdes;
>> + u32 dtuna;
>> + u32 dtune;
>> + u32 dtuprd0;
>> + u32 dtuprd1;
>> + u32 dtuprd2;
>> + u32 dtuprd3;
>> + u32 dtuawdt;
>> + u32 reserved4[3];
>> + u32 togcnt1u;
>> + u32 tinit;
>> + u32 trsth;
>> + u32 togcnt100n;
>> + u32 trefi;
>> + u32 tmrd;
>> + u32 trfc;
>> + u32 trp;
>> + u32 trtw;
>> + u32 tal;
>> + u32 tcl;
>> + u32 tcwl;
>> + u32 tras;
>> + u32 trc;
>> + u32 trcd;
>> + u32 trrd;
>> + u32 trtp;
>> + u32 twr;
>> + u32 twtr;
>> + u32 texsr;
>> + u32 txp;
>> + u32 txpdll;
>> + u32 tzqcs;
>> + u32 tzqcsi;
>> + u32 tdqs;
>> + u32 tcksre;
>> + u32 tcksrx;
>> + u32 tcke;
>> + u32 tmod;
>> + u32 trstl;
>> + u32 tzqcl;
>> + u32 tmrr;
>> + u32 tckesr;
>> + u32 t
>>
>> Hi Philipp:
>>
>>
>> On 2017年07月29日 03:22, Philipp Tomsich wrote:
>>> This adds a DRAM controller driver for the RK3368 and places it in
>>> drivers/ram/rockchip (where the other DM-enabled DRAM controller
>>> drivers for rockchip devices should also be moved eventually).
>>>
>>> At this stage, only the following feature-set is supported:
>>> - DDR3
>>> - 32-bit configuration (i.e. fully populated)
>>> - dual-rank (i.e. no auto-detection of ranks)
>>> - DDR3-1600K speed-bin
>>>
>>> This driver expects to run from a TPL stage that will later return to
>>> the RK3368 BROM. It communicates with later stages through the
>>> os_reg2 in the pmugrf (i.e. using the same mechanism as Rockchip's DDR
>>> init code).
>>>
>>> Unlike other DMC drivers for RK32xx and RK33xx parts, the required
>>> timings are calculated within the driver based on a target frequency
>>> and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this
>>> time).
>>>
>>> The RK3368 also has the DDRC0_CON0 (DDR ch. 0, control-register 0)
>>> register for controlling the operation of its (single-channel) DRAM
>>> controller in the GRF block. This provides for selecting DDR3, mobile
>>> DDR modes, and control low-power operation.
>>> As part of this change, DDRC0_CON0 is also added to the GRF structure
>>> definition (at offset 0x600).
>>>
>>> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>>>
>>> Reviewed-by: Simon Glass <sjg@chromium.org>
>>> ---
>>>
>>> Changes in v3:
>>> - correctly states the location of the driver in the commit message
>>>
>>> Changes in v2: None
>>>
>>> arch/arm/include/asm/arch-rockchip/ddr_rk3368.h | 187 ++++
>>> arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 3 +
>>> arch/arm/mach-rockchip/rk3368/Makefile | 1 -
>>> arch/arm/mach-rockchip/rk3368/sdram_rk3368.c | 60 --
>>> .../clock/rockchip,rk3368-dmc.txt | 67 ++
>>> drivers/ram/Makefile | 2 +
>>> drivers/ram/rockchip/Makefile | 7 +
>>> drivers/ram/rockchip/dmc-rk3368.c | 990 +++++++++++++++++++++
>>> include/dt-bindings/memory/rk3368-dmc.h | 30 +
>>> 9 files changed, 1286 insertions(+), 61 deletions(-)
>>> create mode 100644 arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
>>> delete mode 100644 arch/arm/mach-rockchip/rk3368/sdram_rk3368.c
>>> create mode 100644 doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt
>>> create mode 100644 drivers/ram/rockchip/Makefile
>>> create mode 100644 drivers/ram/rockchip/dmc-rk3368.c
>>> create mode 100644 include/dt-bindings/memory/rk3368-dmc.h
>>>
>>> diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h b/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
>>> new file mode 100644
>>> index 0000000..4e2b233
>>> --- /dev/null
>>> +++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
>>> @@ -0,0 +1,187 @@
>>> +/*
>>> + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
>>> + *
>>> + * SPDX-License-Identifier: GPL-2.0
>>> + */
>>> +
>>> +#ifndef __ASM_ARCH_DDR_RK3368_H__
>>> +#define __ASM_ARCH_DDR_RK3368_H__
>>> +
>>> +/*
>>> + * The RK3368 DDR PCTL differs from the incarnation in the RK3288 only
>>> + * in a few details. Most notably, it has an additional field to track
>>> + * tREFI in controller cycles (i.e. trefi_mem_ddr3).
>>> + */
>>> +struct rk3368_ddr_pctl {
>>> + u32 scfg;
>>> + u32 sctl;
>>> + u32 stat;
>>> + u32 intrstat;
>>> + u32 reserved0[12];
>>> + u32 mcmd;
>>> + u32 powctl;
>>> + u32 powstat;
>>> + u32 cmdtstat;
>>> + u32 cmdtstaten;
>>> + u32 reserved1[3];
>>> + u32 mrrcfg0;
>>> + u32 mrrstat0;
>>> + u32 mrrstat1;
>>> + u32 reserved2[4];
>>> + u32 mcfg1;
>>> + u32 mcfg;
>>> + u32 ppcfg;
>>> + u32 mstat;
>>> + u32 lpddr2zqcfg;
>>> + u32 reserved3;
>>> + u32 dtupdes;
>>> + u32 dtuna;
>>> + u32 dtune;
>>> + u32 dtuprd0;
>>> + u32 dtuprd1;
>>> + u32 dtuprd2;
>>> + u32 dtuprd3;
>>> + u32 dtuawdt;
>>> + u32 reserved4[3];
>>> + u32 togcnt1u;
>>> + u32 tinit;
>>> + u32 trsth;
>>> + u32 togcnt100n;
>>> + u32 trefi;
>>> + u32 tmrd;
>>> + u32 trfc;
>>> + u32 trp;
>>> + u32 trtw;
>>> + u32 tal;
>>> + u32 tcl;
>>> + u32 tcwl;
>>> + u32 tras;
>>> + u32 trc;
>>> + u32 trcd;
>>> + u32 trrd;
>>> + u32 trtp;
>>> + u32 twr;
>>> + u32 twtr;
>>> + u32 texsr;
>>> + u32 txp;
>>> + u32 txpdll;
>>> + u32 tzqcs;
>>> + u32 tzqcsi;
>>> + u32 tdqs;
>>> + u32 tcksre;
>>> + u32 tcksrx;
>>> + u32 tcke;
>>> + u32 tmod;
>>> + u32 trstl;
>>> + u32 tzqcl;
>>> + u32 tmrr;
>>> + u32 tckesr;
>>> + u32 tdpd;
>>> + u32 trefi_mem_ddr3;
>>> + u32 reserved5[45];
>>> + u32 dtuwactl;
>>> + u32 dturactl;
>>> + u32 dtucfg;
>>> + u32 dtuectl;
>>> + u32 dtuwd0;
>>> + u32 dtuwd1;
>>> + u32 dtuwd2;
>>> + u32 dtuwd3;
>>> + u32 dtuwdm;
>>> + u32 dturd0;
>>> + u32 dturd1;
>>> + u32 dturd2;
>>> + u32 dturd3;
>>> + u32 dtulfsrwd;
>>> + u32 dtulfsrrd;
>>> + u32 dtueaf;
>>> + u32 dfitctrldelay;
>>> + u32 dfiodtcfg;
>>> + u32 dfiodtcfg1;
>>> + u32 dfiodtrankmap;
>>> + u32 dfitphywrdata;
>>> + u32 dfitphywrlat;
>>> + u32 reserved7[2];
>>> + u32 dfitrddataen;
>>> + u32 dfitphyrdlat;
>>> + u32 reserved8[2];
>>> + u32 dfitphyupdtype0;
>>> + u32 dfitphyupdtype1;
>>> + u32 dfitphyupdtype2;
>>> + u32 dfitphyupdtype3;
>>> + u32 dfitctrlupdmin;
>>> + u32 dfitctrlupdmax;
>>> + u32 dfitctrlupddly;
>>> + u32 reserved9;
>>> + u32 dfiupdcfg;
>>> + u32 dfitrefmski;
>>> + u32 dfitctrlupdi;
>>> + u32 reserved10[4];
>>> + u32 dfitrcfg0;
>>> + u32 dfitrstat0;
>>> + u32 dfitrwrlvlen;
>>> + u32 dfitrrdlvlen;
>>> + u32 dfitrrdlvlgateen;
>>> + u32 dfiststat0;
>>> + u32 dfistcfg0;
>>> + u32 dfistcfg1;
>>> + u32 reserved11;
>>> + u32 dfitdramclken;
>>> + u32 dfitdramclkdis;
>>> + u32 dfistcfg2;
>>> + u32 dfistparclr;
>>> + u32 dfistparlog;
>>> + u32 reserved12[3];
>>> + u32 dfilpcfg0;
>>> + u32 reserved13[3];
>>> + u32 dfitrwrlvlresp0;
>>> + u32 dfitrwrlvlresp1;
>>> + u32 dfitrwrlvlresp2;
>>> + u32 dfitrrdlvlresp0;
>>> + u32 dfitrrdlvlresp1;
>>> + u32 dfitrrdlvlresp2;
>>> + u32 dfitrwrlvldelay0;
>>> + u32 dfitrwrlvldelay1;
>>> + u32 dfitrwrlvldelay2;
>>> + u32 dfitrrdlvldelay0;
>>> + u32 dfitrrdlvldelay1;
>>> + u32 dfitrrdlvldelay2;
>>> + u32 dfitrrdlvlgatedelay0;
>>> + u32 dfitrrdlvlgatedelay1;
>>> + u32 dfitrrdlvlgatedelay2;
>>> + u32 dfitrcmd;
>>> + u32 reserved14[46];
>>> + u32 ipvr;
>>> + u32 iptr;
>>> +};
>>> +check_member(rk3368_ddr_pctl, iptr, 0x03fc);
>>> +
>>> +struct rk3368_ddrphy {
>>> + u32 reg[0x100];
>>> +};
>>> +check_member(rk3368_ddrphy, reg[0xff], 0x03fc);
>>> +
>>> +struct rk3368_msch {
>>> + u32 coreid;
>>> + u32 revisionid;
>>> + u32 ddrconf;
>>> + u32 ddrtiming;
>>> + u32 ddrmode;
>>> + u32 readlatency;
>>> + u32 reserved1[8];
>>> + u32 activate;
>>> + u32 devtodev;
>>> +};
>>> +check_member(rk3368_msch, devtodev, 0x003c);
>>> +
>>> +/* GRF_SOC_CON0 */
>>> +enum {
>>> + NOC_RSP_ERR_STALL = BIT(9),
>>> + MOBILE_DDR_SEL = BIT(4),
>>> + DDR0_16BIT_EN = BIT(3),
>>> + MSCH0_MAINDDR3_DDR3 = BIT(2),
>>> + MSCH0_MAINPARTIALPOP = BIT(1),
>>> + UPCTL_C_ACTIVE = BIT(0),
>>> +};
>>> +
>>> +#endif
>>> diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
>>> index 1f84ff9..6b6651a 100644
>>> --- a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
>>> +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
>>> @@ -76,8 +76,11 @@ struct rk3368_grf {
>>> u32 soc_con15;
>>> u32 soc_con16;
>>> u32 soc_con17;
>>> + u32 reserved5[0x6e];
>>> + u32 ddrc0_con0;
>>> };
>>> check_member(rk3368_grf, soc_con17, 0x444);
>>> +check_member(rk3368_grf, ddrc0_con0, 0x600);
>>> struct rk3368_pmu_grf {
>>> u32 gpio0a_iomux;
>>> diff --git a/arch/arm/mach-rockchip/rk3368/Makefile b/arch/arm/mach-rockchip/rk3368/Makefile
>>> index 0390716..46798c2 100644
>>> --- a/arch/arm/mach-rockchip/rk3368/Makefile
>>> +++ b/arch/arm/mach-rockchip/rk3368/Makefile
>>> @@ -5,5 +5,4 @@
>>> #
>>> obj-y += clk_rk3368.o
>>> obj-y += rk3368.o
>>> -obj-y += sdram_rk3368.o
>>> obj-y += syscon_rk3368.o
>>
>> the current PX5 EVB and Sheep board(they don't use spl now) depend on
>> the sdram_rk3368 driver to get the sdram capacity, and so is the geekbox.
>> They will be broken when this driver removed.
>>
>> We got the boot failed log on PX5 like bellow:
>>
>>> diff --git a/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c b/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c
>>> deleted file mode 100644
>>> index d0d0900..0000000
>>> --- a/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c
>>> +++ /dev/null
>>> @@ -1,60 +0,0 @@
>>> -/*
>>> - * (C) Copyright 2016 Rockchip Electronics Co., Ltd.
>>> - *
>>> - * SPDX-License-Identifier: GPL-2.0
>>> - */
>>> -
>>> -#include <common.h>
>>> -#include <dm.h>
>>> -#include <ram.h>
>>> -#include <syscon.h>
>>> -#include <asm/arch/clock.h>
>>> -#include <asm/arch/grf_rk3368.h>
>>> -#include <asm/arch/sdram_common.h>
>>> -
>>> -DECLARE_GLOBAL_DATA_PTR;
>>> -struct dram_info {
>>> - struct ram_info info;
>>> - struct rk3368_pmu_grf *pmugrf;
>>> -};
>>> -
>>> -static int rk3368_dmc_probe(struct udevice *dev)
>>> -{
>>> - struct dram_info *priv = dev_get_priv(dev);
>>> -
>>> - priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
>>> - debug("%s: grf=%p\n", __func__, priv->pmugrf);
>>> - priv->info.base = CONFIG_SYS_SDRAM_BASE;
>>> - priv->info.size = rockchip_sdram_size(
>>> - (phys_addr_t)&priv->pmugrf->os_reg[2]);
>>> -
>>> - return 0;
>>> -}
>>> -
>>> -static int rk3368_dmc_get_info(struct udevice *dev, struct ram_info *info)
>>> -{
>>> - struct dram_info *priv = dev_get_priv(dev);
>>> -
>>> - *info = priv->info;
>>> -
>>> - return 0;
>>> -}
>>> -
>>> -static struct ram_ops rk3368_dmc_ops = {
>>> - .get_info = rk3368_dmc_get_info,
>>> -};
>>> -
>>> -
>>> -static const struct udevice_id rk3368_dmc_ids[] = {
>>> - { .compatible = "rockchip,rk3368-dmc" },
>>> - { }
>>> -};
>>> -
>>> -U_BOOT_DRIVER(dmc_rk3368) = {
>>> - .name = "rockchip_rk3368_dmc",
>>> - .id = UCLASS_RAM,
>>> - .of_match = rk3368_dmc_ids,
>>> - .ops = &rk3368_dmc_ops,
>>> - .probe = rk3368_dmc_probe,
>>> - .priv_auto_alloc_size = sizeof(struct dram_info),
>>> -};
>>> diff --git a/doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt b/doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt
>>> new file mode 100644
>>> index 0000000..8e7357d
>>> --- /dev/null
>>> +++ b/doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt
>>> @@ -0,0 +1,67 @@
>>> +RK3368 dynamic memory controller driver
>>> +=======================================
>>> +
>>> +The RK3368 DMC (dynamic memory controller) driver supports setup/initialisation
>>> +during TPL using configuration data from the DTS (i.e. OF_PLATDATA), based on
>>> +the following key configuration data:
>>> + (a) a target-frequency (i.e. operating point) for the memory operation
>>> + (b) a speed-bin (as defined in JESD-79) for the DDR3 used in hardware
>>> + (c) a memory-schedule (i.e. mapping from physical addresses to the address
>>> + pins of the memory bus)
>>> +
>>> +Required properties
>>> +-------------------
>>> +
>>> +- compatible: "rockchip,rk3368-dmc"
>>> +- reg
>>> + protocol controller (PCTL) address and PHY controller (DDRPHY) address
>>> +- rockchip,ddr-speed-bin
>>> + the DDR3 device's speed-bin (as specified according to JESD-79)
>>> + DDR3_800D (5-5-5)
>>> + DDR3_800E (6-6-6)
>>> + DDR3_1066E (6-6-6)
>>> + DDR3_1066F (7-7-7)
>>> + DDR3_1066G (8-8-8)
>>> + DDR3_1333F (7-7-7)
>>> + DDR3_1333G (8-8-8)
>>> + DDR3_1333H (9-9-9)
>>> + DDR3_1333J (10-10-10)
>>> + DDR3_1600G (8-8-8)
>>> + DDR3_1600H (9-9-9)
>>> + DDR3_1600J (10-10-10)
>>> + DDR3_1600K (11-11-11)
>>> + DDR3_1866J (10-10-10)
>>> + DDR3_1866K (11-11-11)
>>> + DDR3_1866L (12-12-12)
>>> + DDR3_1866M (13-13-13)
>>> + DDR3_2133K (11-11-11)
>>> + DDR3_2133L (12-12-12)
>>> + DDR3_2133M (13-13-13)
>>> + DDR3_2133N (14-14-14)
>>> +- rockchip,ddr-frequency:
>>> + target DDR clock frequency in Hz (not all frequencies may be supported,
>>> + as there's some cooperation from the clock-driver required)
>>> +- rockchip,memory-schedule:
>>> + controls the decoding of physical addresses to DRAM addressing (i.e. how
>>> + the physical address maps onto the address pins/chip-select of the device)
>>> + DMC_MSCH_CBDR: column -> bank -> device -> row
>>> + DMC_MSCH_CBRD: column -> band -> row -> device
>>> + DMC_MSCH_CRBD: column -> row -> band -> device
>>> +
>>> +Example (for DDR3-1600K and 800MHz)
>>> +-----------------------------------
>>> +
>>> + #include <dt-bindings/memory/rk3368-dmc.h>
>>> +
>>> + dmc: dmc at ff610000 {
>>> + u-boot,dm-pre-reloc;
>>> + compatible = "rockchip,rk3368-dmc";
>>> + reg = <0 0xff610000 0 0x400
>>> + 0 0xff620000 0 0x400>;
>>> + };
>>> +
>>> + &dmc {
>>> + rockchip,ddr-speed-bin = <DDR3_1600K>;
>>> + rockchip,ddr-frequency = <800000000>;
>>> + rockchip,memory-schedule = <DMC_MSCH_CBRD>;
>>> + };
>>> diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
>>> index c409c48..51ae6be 100644
>>> --- a/drivers/ram/Makefile
>>> +++ b/drivers/ram/Makefile
>>> @@ -8,3 +8,5 @@ obj-$(CONFIG_RAM) += ram-uclass.o
>>> obj-$(CONFIG_SANDBOX) += sandbox_ram.o
>>> obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o
>>> obj-$(CONFIG_ARCH_BMIPS) += bmips_ram.o
>>> +
>>> +obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
>>> diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile
>>> new file mode 100644
>>> index 0000000..b09d03c
>>> --- /dev/null
>>> +++ b/drivers/ram/rockchip/Makefile
>>> @@ -0,0 +1,7 @@
>>> +#
>>> +# Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
>>> +#
>>> +# SPDX-License-Identifier: GPL-2.0+
>>> +#
>>> +
>>> +obj-$(CONFIG_ROCKCHIP_RK3368) = dmc-rk3368.o
>>> diff --git a/drivers/ram/rockchip/dmc-rk3368.c b/drivers/ram/rockchip/dmc-rk3368.c
>>> new file mode 100644
>>> index 0000000..fea96a5
>>> --- /dev/null
>>> +++ b/drivers/ram/rockchip/dmc-rk3368.c
>>> @@ -0,0 +1,990 @@
>>> +/*
>>> + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
>>> + *
>>> + * SPDX-License-Identifier: GPL-2.0
>>> + */
>>> +
>>> +#include <common.h>
>>> +#include <clk.h>
>>> +#include <dm.h>
>>> +#include <dt-bindings/memory/rk3368-dmc.h>
>>> +#include <dt-structs.h>
>>> +#include <ram.h>
>>> +#include <regmap.h>
>>> +#include <syscon.h>
>>> +#include <asm/io.h>
>>> +#include <asm/arch/clock.h>
>>> +#include <asm/arch/cru_rk3368.h>
>>> +#include <asm/arch/grf_rk3368.h>
>>> +#include <asm/arch/ddr_rk3368.h>
>>> +#include <asm/arch/sdram.h>
>>> +#include <asm/arch/sdram_common.h>
>>> +
>>> +DECLARE_GLOBAL_DATA_PTR;
>>> +
>>> +struct dram_info {
>>> + struct ram_info info;
>>> + struct clk ddr_clk;
>>> + struct rk3368_cru *cru;
>>> + struct rk3368_grf *grf;
>>> + struct rk3368_ddr_pctl *pctl;
>>> + struct rk3368_ddrphy *phy;
>>> + struct rk3368_pmu_grf *pmugrf;
>>> + struct rk3368_msch *msch;
>>> +};
>>> +
>>> +struct rk3368_sdram_params {
>>> +#if CONFIG_IS_ENABLED(OF_PLATDATA)
>>> + struct dtd_rockchip_rk3368_dmc of_plat;
>>> +#endif
>>> + struct rk3288_sdram_pctl_timing pctl_timing;
>>> + u32 trefi_mem_ddr3;
>>> + struct rk3288_sdram_channel chan;
>>> + struct regmap *map;
>>> + u32 ddr_freq;
>>> + u32 memory_schedule;
>>> + u32 ddr_speed_bin;
>>> + u32 tfaw_mult;
>>> +};
>>> +
>>> +/* PTCL bits */
>>> +enum {
>>> + /* PCTL_DFISTCFG0 */
>>> + DFI_INIT_START = BIT(0),
>>> + DFI_DATA_BYTE_DISABLE_EN = BIT(2),
>>> +
>>> + /* PCTL_DFISTCFG1 */
>>> + DFI_DRAM_CLK_SR_EN = BIT(0),
>>> + DFI_DRAM_CLK_DPD_EN = BIT(1),
>>> + ODT_LEN_BL8_W_SHIFT = 16,
>>> +
>>> + /* PCTL_DFISTCFG2 */
>>> + DFI_PARITY_INTR_EN = BIT(0),
>>> + DFI_PARITY_EN = BIT(1),
>>> +
>>> + /* PCTL_DFILPCFG0 */
>>> + TLP_RESP_TIME_SHIFT = 16,
>>> + LP_SR_EN = BIT(8),
>>> + LP_PD_EN = BIT(0),
>>> +
>>> + /* PCTL_DFIODTCFG */
>>> + RANK0_ODT_WRITE_SEL = BIT(3),
>>> + RANK1_ODT_WRITE_SEL = BIT(11),
>>> +
>>> + /* PCTL_SCFG */
>>> + HW_LOW_POWER_EN = BIT(0),
>>> +
>>> + /* PCTL_MCMD */
>>> + START_CMD = BIT(31),
>>> + MCMD_RANK0 = BIT(20),
>>> + MCMD_RANK1 = BIT(21),
>>> + DESELECT_CMD = 0,
>>> + PREA_CMD,
>>> + REF_CMD,
>>> + MRS_CMD,
>>> + ZQCS_CMD,
>>> + ZQCL_CMD,
>>> + RSTL_CMD,
>>> + MRR_CMD = 8,
>>> + DPDE_CMD,
>>> +
>>> + /* PCTL_POWCTL */
>>> + POWER_UP_START = BIT(0),
>>> +
>>> + /* PCTL_POWSTAT */
>>> + POWER_UP_DONE = BIT(0),
>>> +
>>> + /* PCTL_SCTL */
>>> + INIT_STATE = 0,
>>> + CFG_STATE,
>>> + GO_STATE,
>>> + SLEEP_STATE,
>>> + WAKEUP_STATE,
>>> +
>>> + /* PCTL_STAT */
>>> + LP_TRIG_SHIFT = 4,
>>> + LP_TRIG_MASK = 7,
>>> + PCTL_STAT_MSK = 7,
>>> + INIT_MEM = 0,
>>> + CONFIG,
>>> + CONFIG_REQ,
>>> + ACCESS,
>>> + ACCESS_REQ,
>>> + LOW_POWER,
>>> + LOW_POWER_ENTRY_REQ,
>>> + LOW_POWER_EXIT_REQ,
>>> +
>>> + /* PCTL_MCFG */
>>> + DDR2_DDR3_BL_8 = BIT(0),
>>> + DDR3_EN = BIT(5),
>>> + TFAW_TRRD_MULT4 = (0 << 18),
>>> + TFAW_TRRD_MULT5 = (1 << 18),
>>> + TFAW_TRRD_MULT6 = (2 << 18),
>>> +};
>>> +
>>> +#define DDR3_MR0_WR(n) \
>>> + ((n <= 8) ? ((n - 4) << 9) : (((n >> 1) & 0x7) << 9))
>>> +#define DDR3_MR0_CL(n) \
>>> + ((((n - 4) & 0x7) << 4) | (((n - 4) & 0x8) >> 2))
>>> +#define DDR3_MR0_BL8 \
>>> + (0 << 0)
>>> +#define DDR3_MR0_DLL_RESET \
>>> + (1 << 8)
>>> +#define DDR3_MR1_RTT120OHM \
>>> + ((0 << 9) | (1 << 6) | (0 << 2))
>>> +#define DDR3_MR2_TWL(n) \
>>> + (((n - 5) & 0x7) << 3)
>>> +
>>> +
>>> +#ifdef CONFIG_TPL_BUILD
>>> +
>>> +static void ddr_set_noc_spr_err_stall(struct rk3368_grf *grf, bool enable)
>>> +{
>>> + if (enable)
>>> + rk_setreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL);
>>> + else
>>> + rk_clrreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL);
>>> +}
>>> +
>>> +static void ddr_set_ddr3_mode(struct rk3368_grf *grf, bool ddr3_mode)
>>> +{
>>> + if (ddr3_mode)
>>> + rk_setreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3);
>>> + else
>>> + rk_clrreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3);
>>> +}
>>> +
>>> +static void ddrphy_config(struct rk3368_ddrphy *phy,
>>> + u32 tcl, u32 tal, u32 tcwl)
>>> +{
>>> + int i;
>>> +
>>> + /* Set to DDR3 mode */
>>> + clrsetbits_le32(&phy->reg[1], 0x3, 0x0);
>>> +
>>> + /* DDRPHY_REGB: CL, AL */
>>> + clrsetbits_le32(&phy->reg[0xb], 0xff, tcl << 4 | tal);
>>> + /* DDRPHY_REGC: CWL */
>>> + clrsetbits_le32(&phy->reg[0xc], 0x0f, tcwl);
>>> +
>>> + /* Update drive-strength */
>>> + writel(0xcc, &phy->reg[0x11]);
>>> + writel(0xaa, &phy->reg[0x16]);
>>> + /*
>>> + * Update NRCOMP/PRCOMP for all 4 channels (for details of all
>>> + * affected registers refer to the documentation of DDRPHY_REG20
>>> + * and DDRPHY_REG21 in the RK3368 TRM.
>>> + */
>>> + for (i = 0; i < 4; ++i) {
>>> + writel(0xcc, &phy->reg[0x20 + i * 0x10]);
>>> + writel(0x44, &phy->reg[0x21 + i * 0x10]);
>>> + }
>>> +
>>> + /* Enable write-leveling calibration bypass */
>>> + setbits_le32(&phy->reg[2], BIT(3));
>>> +}
>>> +
>>> +static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
>>> +{
>>> + int i;
>>> +
>>> + for (i = 0; i < n / sizeof(u32); i++)
>>> + writel(*src++, dest++);
>>> +}
>>> +
>>> +static void send_command(struct rk3368_ddr_pctl *pctl, u32 rank, u32 cmd)
>>> +{
>>> + u32 mcmd = START_CMD | cmd | rank;
>>> +
>>> + debug("%s: writing %x to MCMD\n", __func__, mcmd);
>>> + writel(mcmd, &pctl->mcmd);
>>> + while (readl(&pctl->mcmd) & START_CMD)
>>> + /* spin */;
>>> +}
>>> +
>>> +static void send_mrs(struct rk3368_ddr_pctl *pctl,
>>> + u32 rank, u32 mr_num, u32 mr_data)
>>> +{
>>> + u32 mcmd = START_CMD | MRS_CMD | rank | (mr_num << 17) | (mr_data << 4);
>>> +
>>> + debug("%s: writing %x to MCMD\n", __func__, mcmd);
>>> + writel(mcmd, &pctl->mcmd);
>>> + while (readl(&pctl->mcmd) & START_CMD)
>>> + /* spin */;
>>> +}
>>> +
>>> +static int memory_init(struct rk3368_ddr_pctl *pctl,
>>> + struct rk3368_sdram_params *params)
>>> +{
>>> + u32 mr[4];
>>> + const ulong timeout_ms = 500;
>>> + ulong tmp;
>>> +
>>> + /*
>>> + * Power up DRAM by DDR_PCTL_POWCTL[0] register of PCTL and
>>> + * wait power up DRAM finish with DDR_PCTL_POWSTAT[0] register
>>> + * of PCTL.
>>> + */
>>> + writel(POWER_UP_START, &pctl->powctl);
>>> +
>>> + tmp = get_timer(0);
>>> + do {
>>> + if (get_timer(tmp) > timeout_ms) {
>>> + error("%s: POWER_UP_START did not complete in %ld ms\n",
>>> + __func__, timeout_ms);
>>> + return -ETIME;
>>> + }
>>> + } while (!(readl(&pctl->powstat) & POWER_UP_DONE));
>>> +
>>> + /* Configure MR0 through MR3 */
>>> + mr[0] = DDR3_MR0_WR(params->pctl_timing.twr) |
>>> + DDR3_MR0_CL(params->pctl_timing.tcl) |
>>> + DDR3_MR0_DLL_RESET;
>>> + mr[1] = DDR3_MR1_RTT120OHM;
>>> + mr[2] = DDR3_MR2_TWL(params->pctl_timing.tcwl);
>>> + mr[3] = 0;
>>> +
>>> + /*
>>> + * Also see RK3368 Technical Reference Manual:
>>> + * "16.6.2 Initialization (DDR3 Initialization Sequence)"
>>> + */
>>> + send_command(pctl, MCMD_RANK0 | MCMD_RANK1, DESELECT_CMD);
>>> + udelay(1);
>>> + send_command(pctl, MCMD_RANK0 | MCMD_RANK1, PREA_CMD);
>>> + send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 2, mr[2]);
>>> + send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 3, mr[3]);
>>> + send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 1, mr[1]);
>>> + send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 0, mr[0]);
>>> + send_command(pctl, MCMD_RANK0 | MCMD_RANK1, ZQCL_CMD);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static void move_to_config_state(struct rk3368_ddr_pctl *pctl)
>>> +{
>>> + /*
>>> + * Also see RK3368 Technical Reference Manual:
>>> + * "16.6.1 State transition of PCTL (Moving to Config State)"
>>> + */
>>> + u32 state = readl(&pctl->stat) & PCTL_STAT_MSK;
>>> +
>>> + switch (state) {
>>> + case LOW_POWER:
>>> + writel(WAKEUP_STATE, &pctl->sctl);
>>> + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
>>> + /* spin */;
>>> +
>>> + /* fall-through */
>>> + case ACCESS:
>>> + case INIT_MEM:
>>> + writel(CFG_STATE, &pctl->sctl);
>>> + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
>>> + /* spin */;
>>> + break;
>>> +
>>> + case CONFIG:
>>> + return;
>>> +
>>> + default:
>>> + break;
>>> + }
>>> +}
>>> +
>>> +static void move_to_access_state(struct rk3368_ddr_pctl *pctl)
>>> +{
>>> + /*
>>> + * Also see RK3368 Technical Reference Manual:
>>> + * "16.6.1 State transition of PCTL (Moving to Access State)"
>>> + */
>>> + u32 state = readl(&pctl->stat) & PCTL_STAT_MSK;
>>> +
>>> + switch (state) {
>>> + case LOW_POWER:
>>> + if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) &
>>> + LP_TRIG_MASK) == 1)
>>> + return;
>>> +
>>> + writel(WAKEUP_STATE, &pctl->sctl);
>>> + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
>>> + /* spin */;
>>> +
>>> + /* fall-through */
>>> + case INIT_MEM:
>>> + writel(CFG_STATE, &pctl->sctl);
>>> + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
>>> + /* spin */;
>>> +
>>> + /* fall-through */
>>> + case CONFIG:
>>> + writel(GO_STATE, &pctl->sctl);
>>> + while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG)
>>> + /* spin */;
>>> + break;
>>> +
>>> + case ACCESS:
>>> + return;
>>> +
>>> + default:
>>> + break;
>>> + }
>>> +}
>>> +
>>> +static void ddrctl_reset(struct rk3368_cru *cru)
>>> +{
>>> + const u32 ctl_reset = BIT(3) | BIT(2);
>>> + const u32 phy_reset = BIT(1) | BIT(0);
>>> +
>>> + rk_setreg(&cru->softrst_con[10], ctl_reset | phy_reset);
>>> + udelay(1);
>>> + rk_clrreg(&cru->softrst_con[10], ctl_reset | phy_reset);
>>> +}
>>> +
>>> +static void ddrphy_reset(struct rk3368_ddrphy *ddrphy)
>>> +{
>>> + clrbits_le32(&ddrphy->reg[0], BIT(3) | BIT(2));
>>> + udelay(1);
>>> + setbits_le32(&ddrphy->reg[0], BIT(3) | BIT(2));
>>> +}
>>> +
>>> +static void ddrphy_config_delays(struct rk3368_ddrphy *ddrphy, u32 freq)
>>> +{
>>> + u32 dqs_dll_delay;
>>> +
>>> + setbits_le32(&ddrphy->reg[0x13], BIT(4));
>>> + clrbits_le32(&ddrphy->reg[0x14], BIT(3));
>>> +
>>> + setbits_le32(&ddrphy->reg[0x26], BIT(4));
>>> + clrbits_le32(&ddrphy->reg[0x27], BIT(3));
>>> +
>>> + setbits_le32(&ddrphy->reg[0x36], BIT(4));
>>> + clrbits_le32(&ddrphy->reg[0x37], BIT(3));
>>> +
>>> + setbits_le32(&ddrphy->reg[0x46], BIT(4));
>>> + clrbits_le32(&ddrphy->reg[0x47], BIT(3));
>>> +
>>> + setbits_le32(&ddrphy->reg[0x56], BIT(4));
>>> + clrbits_le32(&ddrphy->reg[0x57], BIT(3));
>>> +
>>> + if (freq <= 400000000)
>>> + setbits_le32(&ddrphy->reg[0xa4], 0x1f);
>>> + else
>>> + clrbits_le32(&ddrphy->reg[0xa4], 0x1f);
>>> +
>>> + if (freq < 681000000)
>>> + dqs_dll_delay = 3; /* 67.5 degree delay */
>>> + else
>>> + dqs_dll_delay = 2; /* 45 degree delay */
>>> +
>>> + writel(dqs_dll_delay, &ddrphy->reg[0x28]);
>>> + writel(dqs_dll_delay, &ddrphy->reg[0x38]);
>>> + writel(dqs_dll_delay, &ddrphy->reg[0x48]);
>>> + writel(dqs_dll_delay, &ddrphy->reg[0x58]);
>>> +}
>>> +
>>> +static int dfi_cfg(struct rk3368_ddr_pctl *pctl)
>>> +{
>>> + const ulong timeout_ms = 200;
>>> + ulong tmp;
>>> +
>>> + writel(DFI_DATA_BYTE_DISABLE_EN, &pctl->dfistcfg0);
>>> +
>>> + writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN,
>>> + &pctl->dfistcfg1);
>>> + writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2);
>>> + writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN,
>>> + &pctl->dfilpcfg0);
>>> +
>>> + writel(1, &pctl->dfitphyupdtype0);
>>> +
>>> + writel(0x1f, &pctl->dfitphyrdlat);
>>> + writel(0, &pctl->dfitphywrdata);
>>> + writel(0, &pctl->dfiupdcfg); /* phyupd and ctrlupd disabled */
>>> +
>>> + setbits_le32(&pctl->dfistcfg0, DFI_INIT_START);
>>> +
>>> + tmp = get_timer(0);
>>> + do {
>>> + if (get_timer(tmp) > timeout_ms) {
>>> + error("%s: DFI init did not complete within %ld ms\n",
>>> + __func__, timeout_ms);
>>> + return -ETIME;
>>> + }
>>> + } while ((readl(&pctl->dfiststat0) & 1) == 0);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static inline u32 ps_to_tCK(const u32 ps, const ulong freq)
>>> +{
>>> + const ulong MHz = 1000000;
>>> + return DIV_ROUND_UP(ps * freq, 1000000 * MHz);
>>> +}
>>> +
>>> +static inline u32 ns_to_tCK(const u32 ns, const ulong freq)
>>> +{
>>> + return ps_to_tCK(ns * 1000, freq);
>>> +}
>>> +
>>> +static inline u32 tCK_to_ps(const ulong tCK, const ulong freq)
>>> +{
>>> + const ulong MHz = 1000000;
>>> + return DIV_ROUND_UP(tCK * 1000000 * MHz, freq);
>>> +}
>>> +
>>> +static int pctl_calc_timings(struct rk3368_sdram_params *params,
>>> + ulong freq)
>>> +{
>>> + struct rk3288_sdram_pctl_timing *pctl_timing = ¶ms->pctl_timing;
>>> + const ulong MHz = 1000000;
>>> + u32 tccd;
>>> + u32 tfaw_as_ps;
>>> +
>>> + if (params->ddr_speed_bin != DDR3_1600K) {
>>> + error("%s: unimplemented DDR3 speed bin %d\n",
>>> + __func__, params->ddr_speed_bin);
>>> + return -1;
>>> + }
>>> +
>>> + /* PCTL is clocked at 1/2 the DRAM clock; err on the side of caution */
>>> + pctl_timing->togcnt1u = DIV_ROUND_UP(freq, 2 * MHz);
>>> + pctl_timing->togcnt100n = DIV_ROUND_UP(freq / 10, 2 * MHz);
>>> +
>>> + pctl_timing->tinit = 200; /* 200 usec */
>>> + pctl_timing->trsth = 500; /* 500 usec */
>>> + pctl_timing->trefi = 78; /* 7.8usec = 78 * 100ns */
>>> + params->trefi_mem_ddr3 = ns_to_tCK(pctl_timing->trefi * 100, freq);
>>> +
>>> + if (freq <= (400 * MHz)) {
>>> + pctl_timing->tcl = 6;
>>> + pctl_timing->tcwl = 10;
>>> + } else if (freq <= (533 * MHz)) {
>>> + pctl_timing->tcl = 8;
>>> + pctl_timing->tcwl = 6;
>>> + } else if (freq <= (666 * MHz)) {
>>> + pctl_timing->tcl = 10;
>>> + pctl_timing->tcwl = 7;
>>> + } else {
>>> + pctl_timing->tcl = 11;
>>> + pctl_timing->tcwl = 8;
>>> + }
>>> +
>>> + pctl_timing->tmrd = 4; /* 4 tCK (all speed bins) */
>>> + pctl_timing->trfc = ns_to_tCK(350, freq); /* tRFC: 350 (max) @ 8GBit */
>>> + pctl_timing->trp = max(4u, ps_to_tCK(13750, freq));
>>> + /*
>>> + * JESD-79:
>>> + * READ to WRITE Command Delay = RL + tCCD / 2 + 2tCK - WL
>>> + */
>>> + tccd = 4;
>>> + pctl_timing->trtw = pctl_timing->tcl + tccd/2 + 2 - pctl_timing->tcwl;
>>> + pctl_timing->tal = 0;
>>> + pctl_timing->tras = ps_to_tCK(35000, freq);
>>> + pctl_timing->trc = ps_to_tCK(48750, freq);
>>> + pctl_timing->trcd = ps_to_tCK(13750, freq);
>>> + pctl_timing->trrd = max(4u, ps_to_tCK(7500, freq));
>>> + pctl_timing->trtp = max(4u, ps_to_tCK(7500, freq));
>>> + pctl_timing->twr = ps_to_tCK(15000, freq);
>>> + /* The DDR3 mode-register does only support even values for tWR > 8. */
>>> + if (pctl_timing->twr > 8)
>>> + pctl_timing->twr = (pctl_timing->twr + 1) & ~1;
>>> + pctl_timing->twtr = max(4u, ps_to_tCK(7500, freq));
>>> + pctl_timing->texsr = 512; /* tEXSR(max) is tDLLLK */
>>> + pctl_timing->txp = max(3u, ps_to_tCK(6000, freq));
>>> + pctl_timing->txpdll = max(10u, ps_to_tCK(24000, freq));
>>> + pctl_timing->tzqcs = max(64u, ps_to_tCK(80000, freq));
>>> + pctl_timing->tzqcsi = 10000; /* as used by Rockchip */
>>> + pctl_timing->tdqs = 1; /* fixed for DDR3 */
>>> + pctl_timing->tcksre = max(5u, ps_to_tCK(10000, freq));
>>> + pctl_timing->tcksrx = max(5u, ps_to_tCK(10000, freq));
>>> + pctl_timing->tcke = max(3u, ps_to_tCK(5000, freq));
>>> + pctl_timing->tmod = max(12u, ps_to_tCK(15000, freq));
>>> + pctl_timing->trstl = ns_to_tCK(100, freq);
>>> + pctl_timing->tzqcl = max(256u, ps_to_tCK(320000, freq)); /* tZQoper */
>>> + pctl_timing->tmrr = 0;
>>> + pctl_timing->tckesr = pctl_timing->tcke + 1; /* JESD-79: tCKE + 1tCK */
>>> + pctl_timing->tdpd = 0; /* RK3368 TRM: "allowed values for DDR3: 0" */
>>> +
>>> +
>>> + /*
>>> + * The controller can represent tFAW as 4x, 5x or 6x tRRD only.
>>> + * We want to use the smallest multiplier that satisfies the tFAW
>>> + * requirements of the given speed-bin. If necessary, we stretch out
>>> + * tRRD to allow us to operate on a 6x multiplier for tFAW.
>>> + */
>>> + tfaw_as_ps = 40000; /* 40ns: tFAW for DDR3-1600K, 2KB page-size */
>>> + if (tCK_to_ps(pctl_timing->trrd * 6, freq) < tfaw_as_ps) {
>>> + /* If tFAW is > 6 x tRRD, we need to stretch tRRD */
>>> + pctl_timing->trrd = ps_to_tCK(DIV_ROUND_UP(40000, 6), freq);
>>> + params->tfaw_mult = TFAW_TRRD_MULT6;
>>> + } else if (tCK_to_ps(pctl_timing->trrd * 5, freq) < tfaw_as_ps) {
>>> + params->tfaw_mult = TFAW_TRRD_MULT6;
>>> + } else if (tCK_to_ps(pctl_timing->trrd * 4, freq) < tfaw_as_ps) {
>>> + params->tfaw_mult = TFAW_TRRD_MULT5;
>>> + } else {
>>> + params->tfaw_mult = TFAW_TRRD_MULT4;
>>> + }
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static void pctl_cfg(struct rk3368_ddr_pctl *pctl,
>>> + struct rk3368_sdram_params *params,
>>> + struct rk3368_grf *grf)
>>> +{
>>> + /* Configure PCTL timing registers */
>>> + params->pctl_timing.trefi |= BIT(31); /* see PCTL_TREFI */
>>> + copy_to_reg(&pctl->togcnt1u, ¶ms->pctl_timing.togcnt1u,
>>> + sizeof(params->pctl_timing));
>>> + writel(params->trefi_mem_ddr3, &pctl->trefi_mem_ddr3);
>>> +
>>> + /* Set up ODT write selector and ODT write length */
>>> + writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL), &pctl->dfiodtcfg);
>>> + writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1);
>>> +
>>> + /* Set up the CL/CWL-dependent timings of DFI */
>>> + writel((params->pctl_timing.tcl - 1) / 2 - 1, &pctl->dfitrddataen);
>>> + writel((params->pctl_timing.tcwl - 1) / 2 - 1, &pctl->dfitphywrlat);
>>> +
>>> + /* DDR3 */
>>> + writel(params->tfaw_mult | DDR3_EN | DDR2_DDR3_BL_8, &pctl->mcfg);
>>> + writel(0x001c0004, &grf->ddrc0_con0);
>>> +
>>> + setbits_le32(&pctl->scfg, HW_LOW_POWER_EN);
>>> +}
>>> +
>>> +static int ddrphy_data_training(struct rk3368_ddr_pctl *pctl,
>>> + struct rk3368_ddrphy *ddrphy)
>>> +{
>>> + const u32 trefi = readl(&pctl->trefi);
>>> + const ulong timeout_ms = 500;
>>> + ulong tmp;
>>> +
>>> + /* disable auto-refresh */
>>> + writel(0 | BIT(31), &pctl->trefi);
>>> +
>>> + clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x20);
>>> + clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x21);
>>> +
>>> + tmp = get_timer(0);
>>> + do {
>>> + if (get_timer(tmp) > timeout_ms) {
>>> + error("%s: did not complete within %ld ms\n",
>>> + __func__, timeout_ms);
>>> + return -ETIME;
>>> + }
>>> + } while ((readl(&ddrphy->reg[0xff]) & 0xf) != 0xf);
>>> +
>>> + send_command(pctl, MCMD_RANK0 | MCMD_RANK1, PREA_CMD);
>>> + clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x20);
>>> + /* resume auto-refresh */
>>> + writel(trefi | BIT(31), &pctl->trefi);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int sdram_col_row_detect(struct udevice *dev)
>>> +{
>>> + struct dram_info *priv = dev_get_priv(dev);
>>> + struct rk3368_sdram_params *params = dev_get_platdata(dev);
>>> + struct rk3368_ddr_pctl *pctl = priv->pctl;
>>> + struct rk3368_msch *msch = priv->msch;
>>> + const u32 test_pattern = 0x5aa5f00f;
>>> + int row, col;
>>> + uintptr_t addr;
>>> +
>>> + move_to_config_state(pctl);
>>> + writel(6, &msch->ddrconf);
>>> + move_to_access_state(pctl);
>>> +
>>> + /* Detect col */
>>> + for (col = 11; col >= 9; col--) {
>>> + writel(0, CONFIG_SYS_SDRAM_BASE);
>>> + addr = CONFIG_SYS_SDRAM_BASE +
>>> + (1 << (col + params->chan.bw - 1));
>>> + writel(test_pattern, addr);
>>> + if ((readl(addr) == test_pattern) &&
>>> + (readl(CONFIG_SYS_SDRAM_BASE) == 0))
>>> + break;
>>> + }
>>> +
>>> + if (col == 8) {
>>> + error("%s: col detect error\n", __func__);
>>> + return -EINVAL;
>>> + }
>>> +
>>> + move_to_config_state(pctl);
>>> + writel(15, &msch->ddrconf);
>>> + move_to_access_state(pctl);
>>> +
>>> + /* Detect row*/
>>> + for (row = 16; row >= 12; row--) {
>>> + writel(0, CONFIG_SYS_SDRAM_BASE);
>>> + addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
>>> + writel(test_pattern, addr);
>>> + if ((readl(addr) == test_pattern) &&
>>> + (readl(CONFIG_SYS_SDRAM_BASE) == 0))
>>> + break;
>>> + }
>>> +
>>> + if (row == 11) {
>>> + error("%s: row detect error\n", __func__);
>>> + return -EINVAL;
>>> + }
>>> +
>>> + /* Record results */
>>> + debug("%s: col %d, row %d\n", __func__, col, row);
>>> + params->chan.col = col;
>>> + params->chan.cs0_row = row;
>>> + params->chan.cs1_row = row;
>>> + params->chan.row_3_4 = 0;
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int msch_niu_config(struct rk3368_msch *msch,
>>> + struct rk3368_sdram_params *params)
>>> +{
>>> + int i;
>>> + const u8 cols = params->chan.col - ((params->chan.bw == 2) ? 0 : 1);
>>> + const u8 rows = params->chan.cs0_row;
>>> +
>>> + /*
>>> + * The DDR address-translation table always assumes a 32bit
>>> + * bus and the comparison below takes care of adjusting for
>>> + * a 16bit bus (i.e. one column-address is consumed).
>>> + */
>>> + const struct {
>>> + u8 rows;
>>> + u8 columns;
>>> + u8 type;
>>> + } ddrconf_table[] = {
>>> + /*
>>> + * C-B-R-D patterns are first. For these we require an
>>> + * exact match for the columns and rows (as there's
>>> + * one entry per possible configuration).
>>> + */
>>> + [0] = { .rows = 13, .columns = 10, .type = DMC_MSCH_CBRD },
>>> + [1] = { .rows = 14, .columns = 10, .type = DMC_MSCH_CBRD },
>>> + [2] = { .rows = 15, .columns = 10, .type = DMC_MSCH_CBRD },
>>> + [3] = { .rows = 16, .columns = 10, .type = DMC_MSCH_CBRD },
>>> + [4] = { .rows = 14, .columns = 11, .type = DMC_MSCH_CBRD },
>>> + [5] = { .rows = 15, .columns = 11, .type = DMC_MSCH_CBRD },
>>> + [6] = { .rows = 16, .columns = 11, .type = DMC_MSCH_CBRD },
>>> + [7] = { .rows = 13, .columns = 9, .type = DMC_MSCH_CBRD },
>>> + [8] = { .rows = 14, .columns = 9, .type = DMC_MSCH_CBRD },
>>> + [9] = { .rows = 15, .columns = 9, .type = DMC_MSCH_CBRD },
>>> + [10] = { .rows = 16, .columns = 9, .type = DMC_MSCH_CBRD },
>>> + /*
>>> + * 11 through 13 are C-R-B-D patterns. These are
>>> + * matched for an exact number of columns and to
>>> + * ensure that the hardware uses at least as many rows
>>> + * as the pattern requires (i.e. we make sure that
>>> + * there's no gaps up until we hit the device/chip-select;
>>> + * however, these patterns can accept up to 16 rows,
>>> + * as the row-address continues right after the CS
>>> + * switching)
>>> + */
>>> + [11] = { .rows = 15, .columns = 10, .type = DMC_MSCH_CRBD },
>>> + [12] = { .rows = 14, .columns = 11, .type = DMC_MSCH_CRBD },
>>> + [13] = { .rows = 13, .columns = 10, .type = DMC_MSCH_CRBD },
>>> + /*
>>> + * 14 and 15 are catch-all variants using a C-B-D-R
>>> + * scheme (i.e. alternating the chip-select every time
>>> + * C-B overflows) and stuffing the remaining C-bits
>>> + * into the top. Matching needs to make sure that the
>>> + * number of columns is either an exact match (i.e. we
>>> + * can use less the the maximum number of rows) -or-
>>> + * that the columns exceed what is given in this table
>>> + * and the rows are an exact match (in which case the
>>> + * remaining C-bits will be stuffed onto the top after
>>> + * the device/chip-select switches).
>>> + */
>>> + [14] = { .rows = 16, .columns = 10, .type = DMC_MSCH_CBDR },
>>> + [15] = { .rows = 16, .columns = 9, .type = DMC_MSCH_CBDR },
>>> + };
>>> +
>>> + /*
>>> + * For C-B-R-D, we need an exact match (i.e. both for the number of
>>> + * columns and rows), while for C-B-D-R, only the the number of
>>> + * columns needs to match.
>>> + */
>>> + for (i = 0; i < ARRAY_SIZE(ddrconf_table); i++) {
>>> + bool match = false;
>>> +
>>> + /* If this entry if for a different matcher, then skip it */
>>> + if (ddrconf_table[i].type != params->memory_schedule)
>>> + continue;
>>> +
>>> + /*
>>> + * Match according to the rules (exact/inexact/at-least)
>>> + * documented in the ddrconf_table above.
>>> + */
>>> + switch (params->memory_schedule) {
>>> + case DMC_MSCH_CBRD:
>>> + match = (ddrconf_table[i].columns == cols) &&
>>> + (ddrconf_table[i].rows == rows);
>>> + break;
>>> +
>>> + case DMC_MSCH_CRBD:
>>> + match = (ddrconf_table[i].columns == cols) &&
>>> + (ddrconf_table[i].rows <= rows);
>>> + break;
>>> +
>>> + case DMC_MSCH_CBDR:
>>> + match = (ddrconf_table[i].columns == cols) ||
>>> + ((ddrconf_table[i].columns <= cols) &&
>>> + (ddrconf_table[i].rows == rows));
>>> + break;
>>> +
>>> + default:
>>> + break;
>>> + }
>>> +
>>> + if (match) {
>>> + debug("%s: setting ddrconf 0x%x\n", __func__, i);
>>> + writel(i, &msch->ddrconf);
>>> + return 0;
>>> + }
>>> + }
>>> +
>>> + error("%s: ddrconf (NIU config) not found\n", __func__);
>>> + return -EINVAL;
>>> +}
>>> +
>>> +static void dram_all_config(struct udevice *dev)
>>> +{
>>> + struct dram_info *priv = dev_get_priv(dev);
>>> + struct rk3368_pmu_grf *pmugrf = priv->pmugrf;
>>> + struct rk3368_sdram_params *params = dev_get_platdata(dev);
>>> + const struct rk3288_sdram_channel *info = ¶ms->chan;
>>> + u32 sys_reg = 0;
>>> + const int chan = 0;
>>> +
>>> + sys_reg |= DDR3 << SYS_REG_DDRTYPE_SHIFT;
>>> + sys_reg |= 0 << SYS_REG_NUM_CH_SHIFT;
>>> +
>>> + sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan);
>>> + sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan);
>>> + sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan);
>>> + sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan);
>>> + sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan);
>>> + sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan);
>>> + sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan);
>>> + sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan);
>>> + sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan);
>>> +
>>> + writel(sys_reg, &pmugrf->os_reg[2]);
>>> +}
>>> +
>>> +static int setup_sdram(struct udevice *dev)
>>> +{
>>> + struct dram_info *priv = dev_get_priv(dev);
>>> + struct rk3368_sdram_params *params = dev_get_platdata(dev);
>>> +
>>> + struct rk3368_ddr_pctl *pctl = priv->pctl;
>>> + struct rk3368_ddrphy *ddrphy = priv->phy;
>>> + struct rk3368_cru *cru = priv->cru;
>>> + struct rk3368_grf *grf = priv->grf;
>>> + struct rk3368_msch *msch = priv->msch;
>>> +
>>> + int ret;
>>> +
>>> + /* The input clock (i.e. DPLL) needs to be 2x the DRAM frequency */
>>> + ret = clk_set_rate(&priv->ddr_clk, 2 * params->ddr_freq);
>>> + if (ret < 0) {
>>> + debug("%s: could not set DDR clock: %d\n", __func__, ret);
>>> + return ret;
>>> + }
>>> +
>>> + /* Update the read-latency for the RK3368 */
>>> + writel(0x32, &msch->readlatency);
>>> +
>>> + /* Initialise the DDR PCTL and DDR PHY */
>>> + ddrctl_reset(cru);
>>> + ddrphy_reset(ddrphy);
>>> + ddrphy_config_delays(ddrphy, params->ddr_freq);
>>> + dfi_cfg(pctl);
>>> + /* Configure relative system information of grf_ddrc0_con0 register */
>>> + ddr_set_ddr3_mode(grf, true);
>>> + ddr_set_noc_spr_err_stall(grf, true);
>>> + /* Calculate timings */
>>> + pctl_calc_timings(params, params->ddr_freq);
>>> + /* Initialise the device timings in protocol controller */
>>> + pctl_cfg(pctl, params, grf);
>>> + /* Configure AL, CL ... information of PHY registers */
>>> + ddrphy_config(ddrphy,
>>> + params->pctl_timing.tcl,
>>> + params->pctl_timing.tal,
>>> + params->pctl_timing.tcwl);
>>> +
>>> + /* Initialize DRAM and configure with mode-register values */
>>> + ret = memory_init(pctl, params);
>>> + if (ret)
>>> + goto error;
>>> +
>>> + move_to_config_state(pctl);
>>> + /* Perform data-training */
>>> + ddrphy_data_training(pctl, ddrphy);
>>> + move_to_access_state(pctl);
>>> +
>>> + /* TODO(prt): could detect rank in training... */
>>> + params->chan.rank = 2;
>>> + /* TODO(prt): bus width is not auto-detected (yet)... */
>>> + params->chan.bw = 2; /* 32bit wide bus */
>>> + params->chan.dbw = params->chan.dbw; /* 32bit wide bus */
>>> +
>>> + /* DDR3 is always 8 bank */
>>> + params->chan.bk = 3;
>>> + /* Detect col and row number */
>>> + ret = sdram_col_row_detect(dev);
>>> + if (ret)
>>> + goto error;
>>> +
>>> + /* Configure NIU DDR configuration */
>>> + ret = msch_niu_config(msch, params);
>>> + if (ret)
>>> + goto error;
>>> +
>>> + /* set up OS_REG to communicate w/ next stage and OS */
>>> + dram_all_config(dev);
>>> +
>>> + return 0;
>>> +
>>> +error:
>>> + printf("DRAM init failed!\n");
>>> + hang();
>>> +}
>>> +#endif
>>> +
>>> +static int rk3368_dmc_ofdata_to_platdata(struct udevice *dev)
>>> +{
>>> + int ret = 0;
>>> +
>>> +#if !CONFIG_IS_ENABLED(OF_PLATDATA)
>>> + struct rk3368_sdram_params *plat = dev_get_platdata(dev);
>>> +
>>> + ret = regmap_init_mem(dev, &plat->map);
>>> + if (ret)
>>> + return ret;
>>> +#endif
>>> +
>>> + return ret;
>>> +}
>>> +
>>> +#if CONFIG_IS_ENABLED(OF_PLATDATA)
>>> +static int conv_of_platdata(struct udevice *dev)
>>> +{
>>> + struct rk3368_sdram_params *plat = dev_get_platdata(dev);
>>> + struct dtd_rockchip_rk3368_dmc *of_plat = &plat->of_plat;
>>> + int ret;
>>> +
>>> + plat->ddr_freq = of_plat->rockchip_ddr_frequency;
>>> + plat->ddr_speed_bin = of_plat->rockchip_ddr_speed_bin;
>>> + plat->memory_schedule = of_plat->rockchip_memory_schedule;
>>> +
>>> + ret = regmap_init_mem_platdata(dev, of_plat->reg,
>>> + ARRAY_SIZE(of_plat->reg) / 2,
>>> + &plat->map);
>>> + if (ret)
>>> + return ret;
>>> +
>>> + return 0;
>>> +}
>>> +#endif
>>> +
>>> +static int rk3368_dmc_probe(struct udevice *dev)
>>> +{
>>> +#ifdef CONFIG_TPL_BUILD
>>> + struct rk3368_sdram_params *plat = dev_get_platdata(dev);
>>> + struct rk3368_ddr_pctl *pctl;
>>> + struct rk3368_ddrphy *ddrphy;
>>> + struct rk3368_cru *cru;
>>> + struct rk3368_grf *grf;
>>> + struct rk3368_msch *msch;
>>> + int ret;
>>> + struct udevice *dev_clk;
>>> +#endif
>>> + struct dram_info *priv = dev_get_priv(dev);
>>> +
>>> +#if CONFIG_IS_ENABLED(OF_PLATDATA)
>>> + ret = conv_of_platdata(dev);
>>> + if (ret)
>>> + return ret;
>>> +#endif
>>> +
>>> + priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
>>> + debug("%s: pmugrf=%p\n", __func__, priv->pmugrf);
>>> +
>>> +#ifdef CONFIG_TPL_BUILD
>>> + pctl = regmap_get_range(plat->map, 0);
>>> + ddrphy = regmap_get_range(plat->map, 1);
>>> + msch = syscon_get_first_range(ROCKCHIP_SYSCON_MSCH);
>>> + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
>>> +
>>> + priv->pctl = pctl;
>>> + priv->phy = ddrphy;
>>> + priv->msch = msch;
>>> + priv->grf = grf;
>>> +
>>> + ret = rockchip_get_clk(&dev_clk);
>>> + if (ret)
>>> + return ret;
>>> + priv->ddr_clk.id = CLK_DDR;
>>> + ret = clk_request(dev_clk, &priv->ddr_clk);
>>> + if (ret)
>>> + return ret;
>>> +
>>> + cru = rockchip_get_cru();
>>> + priv->cru = cru;
>>> + if (IS_ERR(priv->cru))
>>> + return PTR_ERR(priv->cru);
>>> +
>>> + ret = setup_sdram(dev);
>>> + if (ret)
>>> + return ret;
>>> +#endif
>>> +
>>> + priv->info.base = 0;
>>> + priv->info.size =
>>> + rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg[2]);
>>> +
>>> + /*
>>> + * we use the 0x00000000~0xfdffffff space since 0xff000000~0xffffffff
>>> + * is SoC register space (i.e. reserved), and 0xfe000000~0xfeffffff is
>>> + * inaccessible for some IP controller.
>>> + */
>>> + priv->info.size = min(priv->info.size, (size_t)0xfe000000);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int rk3368_dmc_get_info(struct udevice *dev, struct ram_info *info)
>>> +{
>>> + struct dram_info *priv = dev_get_priv(dev);
>>> +
>>> + *info = priv->info;
>>> + return 0;
>>> +}
>>> +
>>> +static struct ram_ops rk3368_dmc_ops = {
>>> + .get_info = rk3368_dmc_get_info,
>>> +};
>>> +
>>> +
>>> +static const struct udevice_id rk3368_dmc_ids[] = {
>>> + { .compatible = "rockchip,rk3368-dmc" },
>>> + { }
>>> +};
>>> +
>>> +U_BOOT_DRIVER(dmc_rk3368) = {
>>> + .name = "rockchip_rk3368_dmc",
>>> + .id = UCLASS_RAM,
>>> + .of_match = rk3368_dmc_ids,
>>> + .ops = &rk3368_dmc_ops,
>>> + .probe = rk3368_dmc_probe,
>>> + .priv_auto_alloc_size = sizeof(struct dram_info),
>>> + .ofdata_to_platdata = rk3368_dmc_ofdata_to_platdata,
>>> + .probe = rk3368_dmc_probe,
>>> + .priv_auto_alloc_size = sizeof(struct dram_info),
>>> + .platdata_auto_alloc_size = sizeof(struct rk3368_sdram_params),
>>> +};
>>> diff --git a/include/dt-bindings/memory/rk3368-dmc.h b/include/dt-bindings/memory/rk3368-dmc.h
>>> new file mode 100644
>>> index 0000000..b06ffde
>>> --- /dev/null
>>> +++ b/include/dt-bindings/memory/rk3368-dmc.h
>>> @@ -0,0 +1,30 @@
>>> +#ifndef DT_BINDINGS_RK3368_DMC_H
>>> +#define DT_BINDINGS_RK3368_DMC_H
>>> +
>>> +#define DMC_MSCH_CBDR 0x0
>>> +#define DMC_MSCH_CBRD 0x1
>>> +#define DMC_MSCH_CRBD 0x2
>>> +
>>> +#define DDR3_800D 0
>>> +#define DDR3_800E 1
>>> +#define DDR3_1066E 2
>>> +#define DDR3_1066F 3
>>> +#define DDR3_1066G 4
>>> +#define DDR3_1333F 5
>>> +#define DDR3_1333G 6
>>> +#define DDR3_1333H 7
>>> +#define DDR3_1333J 8
>>> +#define DDR3_1600G 9
>>> +#define DDR3_1600H 10
>>> +#define DDR3_1600J 11
>>> +#define DDR3_1600K 12
>>> +#define DDR3_1866J 13
>>> +#define DDR3_1866K 14
>>> +#define DDR3_1866L 15
>>> +#define DDR3_1866M 16
>>> +#define DDR3_2133K 17
>>> +#define DDR3_2133L 18
>>> +#define DDR3_2133M 19
>>> +#define DDR3_2133N 20
>>> +
>>> +#endif
>>
>> dpd;
>> + u32 trefi_mem_ddr3;
>> + u32 reserved5[45];
>> + u32 dtuwactl;
>> + u32 dturactl;
>> + u32 dtucfg;
>> + u32 dtuectl;
>> + u32 dtuwd0;
>> + u32 dtuwd1;
>> + u32 dtuwd2;
>> + u32 dtuwd3;
>> + u32 dtuwdm;
>> + u32 dturd0;
>> + u32 dturd1;
>> + u32 dturd2;
>> + u32 dturd3;
>> + u32 dtulfsrwd;
>> + u32 dtulfsrrd;
>> + u32 dtueaf;
>> + u32 dfitctrldelay;
>> + u32 dfiodtcfg;
>> + u32 dfiodtcfg1;
>> + u32 dfiodtrankmap;
>> + u32 dfitphywrdata;
>> + u32 dfitphywrlat;
>> + u32 reserved7[2];
>> + u32 dfitrddataen;
>> + u32 dfitphyrdlat;
>> + u32 reserved8[2];
>> + u32 dfitphyupdtype0;
>> + u32 dfitphyupdtype1;
>> + u32 dfitphyupdtype2;
>> + u32 dfitphyupdtype3;
>> + u32 dfitctrlupdmin;
>> + u32 dfitctrlupdmax;
>> + u32 dfitctrlupddly;
>> + u32 reserved9;
>> + u32 dfiupdcfg;
>> + u32 dfitrefmski;
>> + u32 dfitctrlupdi;
>> + u32 reserved10[4];
>> + u32 dfitrcfg0;
>> + u32 dfitrstat0;
>> + u32 dfitrwrlvlen;
>> + u32 dfitrrdlvlen;
>> + u32 dfitrrdlvlgateen;
>> + u32 dfiststat0;
>> + u32 dfistcfg0;
>> + u32 dfistcfg1;
>> + u32 reserved11;
>> + u32 dfitdramclken;
>> + u32 dfitdramclkdis;
>> + u32 dfistcfg2;
>> + u32 dfistparclr;
>> + u32 dfistparlog;
>> + u32 reserved12[3];
>> + u32 dfilpcfg0;
>> + u32 reserved13[3];
>> + u32 dfitrwrlvlresp0;
>> + u32 dfitrwrlvlresp1;
>> + u32 dfitrwrlvlresp2;
>> + u32 dfitrrdlvlresp0;
>> + u32 dfitrrdlvlresp1;
>> + u32 dfitrrdlvlresp2;
>> + u32 dfitrwrlvldelay0;
>> + u32 dfitrwrlvldelay1;
>> + u32 dfitrwrlvldelay2;
>> + u32 dfitrrdlvldelay0;
>> + u32 dfitrrdlvldelay1;
>> + u32 dfitrrdlvldelay2;
>> + u32 dfitrrdlvlgatedelay0;
>> + u32 dfitrrdlvlgatedelay1;
>> + u32 dfitrrdlvlgatedelay2;
>> + u32 dfitrcmd;
>> + u32 reserved14[46];
>> + u32 ipvr;
>> + u32 iptr;
>> +};
>> +check_member(rk3368_ddr_pctl, iptr, 0x03fc);
>> +
>> +struct rk3368_ddrphy {
>> + u32 reg[0x100];
>> +};
>> +check_member(rk3368_ddrphy, reg[0xff], 0x03fc);
>> +
>> +struct rk3368_msch {
>> + u32 coreid;
>> + u32 revisionid;
>> + u32 ddrconf;
>> + u32 ddrtiming;
>> + u32 ddrmode;
>> + u32 readlatency;
>> + u32 reserved1[8];
>> + u32 activate;
>> + u32 devtodev;
>> +};
>> +check_member(rk3368_msch, devtodev, 0x003c);
>> +
>> +/* GRF_SOC_CON0 */
>> +enum {
>> + NOC_RSP_ERR_STALL = BIT(9),
>> + MOBILE_DDR_SEL = BIT(4),
>> + DDR0_16BIT_EN = BIT(3),
>> + MSCH0_MAINDDR3_DDR3 = BIT(2),
>> + MSCH0_MAINPARTIALPOP = BIT(1),
>> + UPCTL_C_ACTIVE = BIT(0),
>> +};
>> +
>> +#endif
>> diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
>> index 1f84ff9..6b6651a 100644
>> --- a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
>> +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
>> @@ -76,8 +76,11 @@ struct rk3368_grf {
>> u32 soc_con15;
>> u32 soc_con16;
>> u32 soc_con17;
>> + u32 reserved5[0x6e];
>> + u32 ddrc0_con0;
>> };
>> check_member(rk3368_grf, soc_con17, 0x444);
>> +check_member(rk3368_grf, ddrc0_con0, 0x600);
>> struct rk3368_pmu_grf {
>> u32 gpio0a_iomux;
>> diff --git a/arch/arm/mach-rockchip/rk3368/Makefile b/arch/arm/mach-rockchip/rk3368/Makefile
>> index 0390716..46798c2 100644
>> --- a/arch/arm/mach-rockchip/rk3368/Makefile
>> +++ b/arch/arm/mach-rockchip/rk3368/Makefile
>> @@ -5,5 +5,4 @@
>> #
>> obj-y += clk_rk3368.o
>> obj-y += rk3368.o
>> -obj-y += sdram_rk3368.o
>> obj-y += syscon_rk3368.o
>
>
> The current PX5 EVB and Sheep board(they have no spl now) depend on this sdram_rk3368.c
> to get the sdram capacity, and so is the geekbox board.
> These boards will be broken when this driver removed.
> We got the failed log like this on PX5 EVB:
>
> DRAM: DRAM init failed: -19
> initcall sequence 000000002d=378208 failed at call 02023f0 (err=-19)
> ### ERROR ### Please RESET the board ###
>> diff --git a/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c b/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c
>> deleted file mode 100644
>> index d0d0900..0000000
>> --- a/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c
>> +++ /dev/null
>> @@ -1,60 +0,0 @@
>> -/*
>> - * (C) Copyright 2016 Rockchip Electronics Co., Ltd.
>> - *
>> - * SPDX-License-Identifier: GPL-2.0
>> - */
>> -
>> -#include <common.h>
>> -#include <dm.h>
>> -#include <ram.h>
>> -#include <syscon.h>
>> -#include <asm/arch/clock.h>
>> -#include <asm/arch/grf_rk3368.h>
>> -#include <asm/arch/sdram_common.h>
>> -
>> -DECLARE_GLOBAL_DATA_PTR;
>> -struct dram_info {
>> - struct ram_info info;
>> - struct rk3368_pmu_grf *pmugrf;
>> -};
>> -
>> -static int rk3368_dmc_probe(struct udevice *dev)
>> -{
>> - struct dram_info *priv = dev_get_priv(dev);
>> -
>> - priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
>> - debug("%s: grf=%p\n", __func__, priv->pmugrf);
>> - priv->info.base = CONFIG_SYS_SDRAM_BASE;
>> - priv->info.size = rockchip_sdram_size(
>> - (phys_addr_t)&priv->pmugrf->os_reg[2]);
>> -
>> - return 0;
>> -}
>> -
>> -static int rk3368_dmc_get_info(struct udevice *dev, struct ram_info *info)
>> -{
>> - struct dram_info *priv = dev_get_priv(dev);
>> -
>> - *info = priv->info;
>> -
>> - return 0;
>> -}
>> -
>> -static struct ram_ops rk3368_dmc_ops = {
>> - .get_info = rk3368_dmc_get_info,
>> -};
>> -
>> -
>> -static const struct udevice_id rk3368_dmc_ids[] = {
>> - { .compatible = "rockchip,rk3368-dmc" },
>> - { }
>> -};
>> -
>> -U_BOOT_DRIVER(dmc_rk3368) = {
>> - .name = "rockchip_rk3368_dmc",
>> - .id = UCLASS_RAM,
>> - .of_match = rk3368_dmc_ids,
>> - .ops = &rk3368_dmc_ops,
>> - .probe = rk3368_dmc_probe,
>> - .priv_auto_alloc_size = sizeof(struct dram_info),
>> -};
>> diff --git a/doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt b/doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt
>> new file mode 100644
>> index 0000000..8e7357d
>> --- /dev/null
>> +++ b/doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt
>> @@ -0,0 +1,67 @@
>> +RK3368 dynamic memory controller driver
>> +=======================================
>> +
>> +The RK3368 DMC (dynamic memory controller) driver supports setup/initialisation
>> +during TPL using configuration data from the DTS (i.e. OF_PLATDATA), based on
>> +the following key configuration data:
>> + (a) a target-frequency (i.e. operating point) for the memory operation
>> + (b) a speed-bin (as defined in JESD-79) for the DDR3 used in hardware
>> + (c) a memory-schedule (i.e. mapping from physical addresses to the address
>> + pins of the memory bus)
>> +
>> +Required properties
>> +-------------------
>> +
>> +- compatible: "rockchip,rk3368-dmc"
>> +- reg
>> + protocol controller (PCTL) address and PHY controller (DDRPHY) address
>> +- rockchip,ddr-speed-bin
>> + the DDR3 device's speed-bin (as specified according to JESD-79)
>> + DDR3_800D (5-5-5)
>> + DDR3_800E (6-6-6)
>> + DDR3_1066E (6-6-6)
>> + DDR3_1066F (7-7-7)
>> + DDR3_1066G (8-8-8)
>> + DDR3_1333F (7-7-7)
>> + DDR3_1333G (8-8-8)
>> + DDR3_1333H (9-9-9)
>> + DDR3_1333J (10-10-10)
>> + DDR3_1600G (8-8-8)
>> + DDR3_1600H (9-9-9)
>> + DDR3_1600J (10-10-10)
>> + DDR3_1600K (11-11-11)
>> + DDR3_1866J (10-10-10)
>> + DDR3_1866K (11-11-11)
>> + DDR3_1866L (12-12-12)
>> + DDR3_1866M (13-13-13)
>> + DDR3_2133K (11-11-11)
>> + DDR3_2133L (12-12-12)
>> + DDR3_2133M (13-13-13)
>> + DDR3_2133N (14-14-14)
>> +- rockchip,ddr-frequency:
>> + target DDR clock frequency in Hz (not all frequencies may be supported,
>> + as there's some cooperation from the clock-driver required)
>> +- rockchip,memory-schedule:
>> + controls the decoding of physical addresses to DRAM addressing (i.e. how
>> + the physical address maps onto the address pins/chip-select of the device)
>> + DMC_MSCH_CBDR: column -> bank -> device -> row
>> + DMC_MSCH_CBRD: column -> band -> row -> device
>> + DMC_MSCH_CRBD: column -> row -> band -> device
>> +
>> +Example (for DDR3-1600K and 800MHz)
>> +-----------------------------------
>> +
>> + #include <dt-bindings/memory/rk3368-dmc.h>
>> +
>> + dmc: dmc at ff610000 {
>> + u-boot,dm-pre-reloc;
>> + compatible = "rockchip,rk3368-dmc";
>> + reg = <0 0xff610000 0 0x400
>> + 0 0xff620000 0 0x400>;
>> + };
>> +
>> + &dmc {
>> + rockchip,ddr-speed-bin = <DDR3_1600K>;
>> + rockchip,ddr-frequency = <800000000>;
>> + rockchip,memory-schedule = <DMC_MSCH_CBRD>;
>> + };
>> diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
>> index c409c48..51ae6be 100644
>> --- a/drivers/ram/Makefile
>> +++ b/drivers/ram/Makefile
>> @@ -8,3 +8,5 @@ obj-$(CONFIG_RAM) += ram-uclass.o
>> obj-$(CONFIG_SANDBOX) += sandbox_ram.o
>> obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o
>> obj-$(CONFIG_ARCH_BMIPS) += bmips_ram.o
>> +
>> +obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
>> diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile
>> new file mode 100644
>> index 0000000..b09d03c
>> --- /dev/null
>> +++ b/drivers/ram/rockchip/Makefile
>> @@ -0,0 +1,7 @@
>> +#
>> +# Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
>> +#
>> +# SPDX-License-Identifier: GPL-2.0+
>> +#
>> +
>> +obj-$(CONFIG_ROCKCHIP_RK3368) = dmc-rk3368.o
>> diff --git a/drivers/ram/rockchip/dmc-rk3368.c b/drivers/ram/rockchip/dmc-rk3368.c
>> new file mode 100644
>> index 0000000..fea96a5
>> --- /dev/null
>> +++ b/drivers/ram/rockchip/dmc-rk3368.c
>> @@ -0,0 +1,990 @@
>> +/*
>> + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
>> + *
>> + * SPDX-License-Identifier: GPL-2.0
>> + */
>> +
>> +#include <common.h>
>> +#include <clk.h>
>> +#include <dm.h>
>> +#include <dt-bindings/memory/rk3368-dmc.h>
>> +#include <dt-structs.h>
>> +#include <ram.h>
>> +#include <regmap.h>
>> +#include <syscon.h>
>> +#include <asm/io.h>
>> +#include <asm/arch/clock.h>
>> +#include <asm/arch/cru_rk3368.h>
>> +#include <asm/arch/grf_rk3368.h>
>> +#include <asm/arch/ddr_rk3368.h>
>> +#include <asm/arch/sdram.h>
>> +#include <asm/arch/sdram_common.h>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +struct dram_info {
>> + struct ram_info info;
>> + struct clk ddr_clk;
>> + struct rk3368_cru *cru;
>> + struct rk3368_grf *grf;
>> + struct rk3368_ddr_pctl *pctl;
>> + struct rk3368_ddrphy *phy;
>> + struct rk3368_pmu_grf *pmugrf;
>> + struct rk3368_msch *msch;
>> +};
>> +
>> +struct rk3368_sdram_params {
>> +#if CONFIG_IS_ENABLED(OF_PLATDATA)
>> + struct dtd_rockchip_rk3368_dmc of_plat;
>> +#endif
>> + struct rk3288_sdram_pctl_timing pctl_timing;
>> + u32 trefi_mem_ddr3;
>> + struct rk3288_sdram_channel chan;
>> + struct regmap *map;
>> + u32 ddr_freq;
>> + u32 memory_schedule;
>> + u32 ddr_speed_bin;
>> + u32 tfaw_mult;
>> +};
>> +
>> +/* PTCL bits */
>> +enum {
>> + /* PCTL_DFISTCFG0 */
>> + DFI_INIT_START = BIT(0),
>> + DFI_DATA_BYTE_DISABLE_EN = BIT(2),
>> +
>> + /* PCTL_DFISTCFG1 */
>> + DFI_DRAM_CLK_SR_EN = BIT(0),
>> + DFI_DRAM_CLK_DPD_EN = BIT(1),
>> + ODT_LEN_BL8_W_SHIFT = 16,
>> +
>> + /* PCTL_DFISTCFG2 */
>> + DFI_PARITY_INTR_EN = BIT(0),
>> + DFI_PARITY_EN = BIT(1),
>> +
>> + /* PCTL_DFILPCFG0 */
>> + TLP_RESP_TIME_SHIFT = 16,
>> + LP_SR_EN = BIT(8),
>> + LP_PD_EN = BIT(0),
>> +
>> + /* PCTL_DFIODTCFG */
>> + RANK0_ODT_WRITE_SEL = BIT(3),
>> + RANK1_ODT_WRITE_SEL = BIT(11),
>> +
>> + /* PCTL_SCFG */
>> + HW_LOW_POWER_EN = BIT(0),
>> +
>> + /* PCTL_MCMD */
>> + START_CMD = BIT(31),
>> + MCMD_RANK0 = BIT(20),
>> + MCMD_RANK1 = BIT(21),
>> + DESELECT_CMD = 0,
>> + PREA_CMD,
>> + REF_CMD,
>> + MRS_CMD,
>> + ZQCS_CMD,
>> + ZQCL_CMD,
>> + RSTL_CMD,
>> + MRR_CMD = 8,
>> + DPDE_CMD,
>> +
>> + /* PCTL_POWCTL */
>> + POWER_UP_START = BIT(0),
>> +
>> + /* PCTL_POWSTAT */
>> + POWER_UP_DONE = BIT(0),
>> +
>> + /* PCTL_SCTL */
>> + INIT_STATE = 0,
>> + CFG_STATE,
>> + GO_STATE,
>> + SLEEP_STATE,
>> + WAKEUP_STATE,
>> +
>> + /* PCTL_STAT */
>> + LP_TRIG_SHIFT = 4,
>> + LP_TRIG_MASK = 7,
>> + PCTL_STAT_MSK = 7,
>> + INIT_MEM = 0,
>> + CONFIG,
>> + CONFIG_REQ,
>> + ACCESS,
>> + ACCESS_REQ,
>> + LOW_POWER,
>> + LOW_POWER_ENTRY_REQ,
>> + LOW_POWER_EXIT_REQ,
>> +
>> + /* PCTL_MCFG */
>> + DDR2_DDR3_BL_8 = BIT(0),
>> + DDR3_EN = BIT(5),
>> + TFAW_TRRD_MULT4 = (0 << 18),
>> + TFAW_TRRD_MULT5 = (1 << 18),
>> + TFAW_TRRD_MULT6 = (2 << 18),
>> +};
>> +
>> +#define DDR3_MR0_WR(n) \
>> + ((n <= 8) ? ((n - 4) << 9) : (((n >> 1) & 0x7) << 9))
>> +#define DDR3_MR0_CL(n) \
>> + ((((n - 4) & 0x7) << 4) | (((n - 4) & 0x8) >> 2))
>> +#define DDR3_MR0_BL8 \
>> + (0 << 0)
>> +#define DDR3_MR0_DLL_RESET \
>> + (1 << 8)
>> +#define DDR3_MR1_RTT120OHM \
>> + ((0 << 9) | (1 << 6) | (0 << 2))
>> +#define DDR3_MR2_TWL(n) \
>> + (((n - 5) & 0x7) << 3)
>> +
>> +
>> +#ifdef CONFIG_TPL_BUILD
>> +
>> +static void ddr_set_noc_spr_err_stall(struct rk3368_grf *grf, bool enable)
>> +{
>> + if (enable)
>> + rk_setreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL);
>> + else
>> + rk_clrreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL);
>> +}
>> +
>> +static void ddr_set_ddr3_mode(struct rk3368_grf *grf, bool ddr3_mode)
>> +{
>> + if (ddr3_mode)
>> + rk_setreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3);
>> + else
>> + rk_clrreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3);
>> +}
>> +
>> +static void ddrphy_config(struct rk3368_ddrphy *phy,
>> + u32 tcl, u32 tal, u32 tcwl)
>> +{
>> + int i;
>> +
>> + /* Set to DDR3 mode */
>> + clrsetbits_le32(&phy->reg[1], 0x3, 0x0);
>> +
>> + /* DDRPHY_REGB: CL, AL */
>> + clrsetbits_le32(&phy->reg[0xb], 0xff, tcl << 4 | tal);
>> + /* DDRPHY_REGC: CWL */
>> + clrsetbits_le32(&phy->reg[0xc], 0x0f, tcwl);
>> +
>> + /* Update drive-strength */
>> + writel(0xcc, &phy->reg[0x11]);
>> + writel(0xaa, &phy->reg[0x16]);
>> + /*
>> + * Update NRCOMP/PRCOMP for all 4 channels (for details of all
>> + * affected registers refer to the documentation of DDRPHY_REG20
>> + * and DDRPHY_REG21 in the RK3368 TRM.
>> + */
>> + for (i = 0; i < 4; ++i) {
>> + writel(0xcc, &phy->reg[0x20 + i * 0x10]);
>> + writel(0x44, &phy->reg[0x21 + i * 0x10]);
>> + }
>> +
>> + /* Enable write-leveling calibration bypass */
>> + setbits_le32(&phy->reg[2], BIT(3));
>> +}
>> +
>> +static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
>> +{
>> + int i;
>> +
>> + for (i = 0; i < n / sizeof(u32); i++)
>> + writel(*src++, dest++);
>> +}
>> +
>> +static void send_command(struct rk3368_ddr_pctl *pctl, u32 rank, u32 cmd)
>> +{
>> + u32 mcmd = START_CMD | cmd | rank;
>> +
>> + debug("%s: writing %x to MCMD\n", __func__, mcmd);
>> + writel(mcmd, &pctl->mcmd);
>> + while (readl(&pctl->mcmd) & START_CMD)
>> + /* spin */;
>> +}
>> +
>> +static void send_mrs(struct rk3368_ddr_pctl *pctl,
>> + u32 rank, u32 mr_num, u32 mr_data)
>> +{
>> + u32 mcmd = START_CMD | MRS_CMD | rank | (mr_num << 17) | (mr_data << 4);
>> +
>> + debug("%s: writing %x to MCMD\n", __func__, mcmd);
>> + writel(mcmd, &pctl->mcmd);
>> + while (readl(&pctl->mcmd) & START_CMD)
>> + /* spin */;
>> +}
>> +
>> +static int memory_init(struct rk3368_ddr_pctl *pctl,
>> + struct rk3368_sdram_params *params)
>> +{
>> + u32 mr[4];
>> + const ulong timeout_ms = 500;
>> + ulong tmp;
>> +
>> + /*
>> + * Power up DRAM by DDR_PCTL_POWCTL[0] register of PCTL and
>> + * wait power up DRAM finish with DDR_PCTL_POWSTAT[0] register
>> + * of PCTL.
>> + */
>> + writel(POWER_UP_START, &pctl->powctl);
>> +
>> + tmp = get_timer(0);
>> + do {
>> + if (get_timer(tmp) > timeout_ms) {
>> + error("%s: POWER_UP_START did not complete in %ld ms\n",
>> + __func__, timeout_ms);
>> + return -ETIME;
>> + }
>> + } while (!(readl(&pctl->powstat) & POWER_UP_DONE));
>> +
>> + /* Configure MR0 through MR3 */
>> + mr[0] = DDR3_MR0_WR(params->pctl_timing.twr) |
>> + DDR3_MR0_CL(params->pctl_timing.tcl) |
>> + DDR3_MR0_DLL_RESET;
>> + mr[1] = DDR3_MR1_RTT120OHM;
>> + mr[2] = DDR3_MR2_TWL(params->pctl_timing.tcwl);
>> + mr[3] = 0;
>> +
>> + /*
>> + * Also see RK3368 Technical Reference Manual:
>> + * "16.6.2 Initialization (DDR3 Initialization Sequence)"
>> + */
>> + send_command(pctl, MCMD_RANK0 | MCMD_RANK1, DESELECT_CMD);
>> + udelay(1);
>> + send_command(pctl, MCMD_RANK0 | MCMD_RANK1, PREA_CMD);
>> + send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 2, mr[2]);
>> + send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 3, mr[3]);
>> + send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 1, mr[1]);
>> + send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 0, mr[0]);
>> + send_command(pctl, MCMD_RANK0 | MCMD_RANK1, ZQCL_CMD);
>> +
>> + return 0;
>> +}
>> +
>> +static void move_to_config_state(struct rk3368_ddr_pctl *pctl)
>> +{
>> + /*
>> + * Also see RK3368 Technical Reference Manual:
>> + * "16.6.1 State transition of PCTL (Moving to Config State)"
>> + */
>> + u32 state = readl(&pctl->stat) & PCTL_STAT_MSK;
>> +
>> + switch (state) {
>> + case LOW_POWER:
>> + writel(WAKEUP_STATE, &pctl->sctl);
>> + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
>> + /* spin */;
>> +
>> + /* fall-through */
>> + case ACCESS:
>> + case INIT_MEM:
>> + writel(CFG_STATE, &pctl->sctl);
>> + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
>> + /* spin */;
>> + break;
>> +
>> + case CONFIG:
>> + return;
>> +
>> + default:
>> + break;
>> + }
>> +}
>> +
>> +static void move_to_access_state(struct rk3368_ddr_pctl *pctl)
>> +{
>> + /*
>> + * Also see RK3368 Technical Reference Manual:
>> + * "16.6.1 State transition of PCTL (Moving to Access State)"
>> + */
>> + u32 state = readl(&pctl->stat) & PCTL_STAT_MSK;
>> +
>> + switch (state) {
>> + case LOW_POWER:
>> + if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) &
>> + LP_TRIG_MASK) == 1)
>> + return;
>> +
>> + writel(WAKEUP_STATE, &pctl->sctl);
>> + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
>> + /* spin */;
>> +
>> + /* fall-through */
>> + case INIT_MEM:
>> + writel(CFG_STATE, &pctl->sctl);
>> + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
>> + /* spin */;
>> +
>> + /* fall-through */
>> + case CONFIG:
>> + writel(GO_STATE, &pctl->sctl);
>> + while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG)
>> + /* spin */;
>> + break;
>> +
>> + case ACCESS:
>> + return;
>> +
>> + default:
>> + break;
>> + }
>> +}
>> +
>> +static void ddrctl_reset(struct rk3368_cru *cru)
>> +{
>> + const u32 ctl_reset = BIT(3) | BIT(2);
>> + const u32 phy_reset = BIT(1) | BIT(0);
>> +
>> + rk_setreg(&cru->softrst_con[10], ctl_reset | phy_reset);
>> + udelay(1);
>> + rk_clrreg(&cru->softrst_con[10], ctl_reset | phy_reset);
>> +}
>> +
>> +static void ddrphy_reset(struct rk3368_ddrphy *ddrphy)
>> +{
>> + clrbits_le32(&ddrphy->reg[0], BIT(3) | BIT(2));
>> + udelay(1);
>> + setbits_le32(&ddrphy->reg[0], BIT(3) | BIT(2));
>> +}
>> +
>> +static void ddrphy_config_delays(struct rk3368_ddrphy *ddrphy, u32 freq)
>> +{
>> + u32 dqs_dll_delay;
>> +
>> + setbits_le32(&ddrphy->reg[0x13], BIT(4));
>> + clrbits_le32(&ddrphy->reg[0x14], BIT(3));
>> +
>> + setbits_le32(&ddrphy->reg[0x26], BIT(4));
>> + clrbits_le32(&ddrphy->reg[0x27], BIT(3));
>> +
>> + setbits_le32(&ddrphy->reg[0x36], BIT(4));
>> + clrbits_le32(&ddrphy->reg[0x37], BIT(3));
>> +
>> + setbits_le32(&ddrphy->reg[0x46], BIT(4));
>> + clrbits_le32(&ddrphy->reg[0x47], BIT(3));
>> +
>> + setbits_le32(&ddrphy->reg[0x56], BIT(4));
>> + clrbits_le32(&ddrphy->reg[0x57], BIT(3));
>> +
>> + if (freq <= 400000000)
>> + setbits_le32(&ddrphy->reg[0xa4], 0x1f);
>> + else
>> + clrbits_le32(&ddrphy->reg[0xa4], 0x1f);
>> +
>> + if (freq < 681000000)
>> + dqs_dll_delay = 3; /* 67.5 degree delay */
>> + else
>> + dqs_dll_delay = 2; /* 45 degree delay */
>> +
>> + writel(dqs_dll_delay, &ddrphy->reg[0x28]);
>> + writel(dqs_dll_delay, &ddrphy->reg[0x38]);
>> + writel(dqs_dll_delay, &ddrphy->reg[0x48]);
>> + writel(dqs_dll_delay, &ddrphy->reg[0x58]);
>> +}
>> +
>> +static int dfi_cfg(struct rk3368_ddr_pctl *pctl)
>> +{
>> + const ulong timeout_ms = 200;
>> + ulong tmp;
>> +
>> + writel(DFI_DATA_BYTE_DISABLE_EN, &pctl->dfistcfg0);
>> +
>> + writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN,
>> + &pctl->dfistcfg1);
>> + writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2);
>> + writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN,
>> + &pctl->dfilpcfg0);
>> +
>> + writel(1, &pctl->dfitphyupdtype0);
>> +
>> + writel(0x1f, &pctl->dfitphyrdlat);
>> + writel(0, &pctl->dfitphywrdata);
>> + writel(0, &pctl->dfiupdcfg); /* phyupd and ctrlupd disabled */
>> +
>> + setbits_le32(&pctl->dfistcfg0, DFI_INIT_START);
>> +
>> + tmp = get_timer(0);
>> + do {
>> + if (get_timer(tmp) > timeout_ms) {
>> + error("%s: DFI init did not complete within %ld ms\n",
>> + __func__, timeout_ms);
>> + return -ETIME;
>> + }
>> + } while ((readl(&pctl->dfiststat0) & 1) == 0);
>> +
>> + return 0;
>> +}
>> +
>> +static inline u32 ps_to_tCK(const u32 ps, const ulong freq)
>> +{
>> + const ulong MHz = 1000000;
>> + return DIV_ROUND_UP(ps * freq, 1000000 * MHz);
>> +}
>> +
>> +static inline u32 ns_to_tCK(const u32 ns, const ulong freq)
>> +{
>> + return ps_to_tCK(ns * 1000, freq);
>> +}
>> +
>> +static inline u32 tCK_to_ps(const ulong tCK, const ulong freq)
>> +{
>> + const ulong MHz = 1000000;
>> + return DIV_ROUND_UP(tCK * 1000000 * MHz, freq);
>> +}
>> +
>> +static int pctl_calc_timings(struct rk3368_sdram_params *params,
>> + ulong freq)
>> +{
>> + struct rk3288_sdram_pctl_timing *pctl_timing = ¶ms->pctl_timing;
>> + const ulong MHz = 1000000;
>> + u32 tccd;
>> + u32 tfaw_as_ps;
>> +
>> + if (params->ddr_speed_bin != DDR3_1600K) {
>> + error("%s: unimplemented DDR3 speed bin %d\n",
>> + __func__, params->ddr_speed_bin);
>> + return -1;
>> + }
>> +
>> + /* PCTL is clocked at 1/2 the DRAM clock; err on the side of caution */
>> + pctl_timing->togcnt1u = DIV_ROUND_UP(freq, 2 * MHz);
>> + pctl_timing->togcnt100n = DIV_ROUND_UP(freq / 10, 2 * MHz);
>> +
>> + pctl_timing->tinit = 200; /* 200 usec */
>> + pctl_timing->trsth = 500; /* 500 usec */
>> + pctl_timing->trefi = 78; /* 7.8usec = 78 * 100ns */
>> + params->trefi_mem_ddr3 = ns_to_tCK(pctl_timing->trefi * 100, freq);
>> +
>> + if (freq <= (400 * MHz)) {
>> + pctl_timing->tcl = 6;
>> + pctl_timing->tcwl = 10;
>> + } else if (freq <= (533 * MHz)) {
>> + pctl_timing->tcl = 8;
>> + pctl_timing->tcwl = 6;
>> + } else if (freq <= (666 * MHz)) {
>> + pctl_timing->tcl = 10;
>> + pctl_timing->tcwl = 7;
>> + } else {
>> + pctl_timing->tcl = 11;
>> + pctl_timing->tcwl = 8;
>> + }
>> +
>> + pctl_timing->tmrd = 4; /* 4 tCK (all speed bins) */
>> + pctl_timing->trfc = ns_to_tCK(350, freq); /* tRFC: 350 (max) @ 8GBit */
>> + pctl_timing->trp = max(4u, ps_to_tCK(13750, freq));
>> + /*
>> + * JESD-79:
>> + * READ to WRITE Command Delay = RL + tCCD / 2 + 2tCK - WL
>> + */
>> + tccd = 4;
>> + pctl_timing->trtw = pctl_timing->tcl + tccd/2 + 2 - pctl_timing->tcwl;
>> + pctl_timing->tal = 0;
>> + pctl_timing->tras = ps_to_tCK(35000, freq);
>> + pctl_timing->trc = ps_to_tCK(48750, freq);
>> + pctl_timing->trcd = ps_to_tCK(13750, freq);
>> + pctl_timing->trrd = max(4u, ps_to_tCK(7500, freq));
>> + pctl_timing->trtp = max(4u, ps_to_tCK(7500, freq));
>> + pctl_timing->twr = ps_to_tCK(15000, freq);
>> + /* The DDR3 mode-register does only support even values for tWR > 8. */
>> + if (pctl_timing->twr > 8)
>> + pctl_timing->twr = (pctl_timing->twr + 1) & ~1;
>> + pctl_timing->twtr = max(4u, ps_to_tCK(7500, freq));
>> + pctl_timing->texsr = 512; /* tEXSR(max) is tDLLLK */
>> + pctl_timing->txp = max(3u, ps_to_tCK(6000, freq));
>> + pctl_timing->txpdll = max(10u, ps_to_tCK(24000, freq));
>> + pctl_timing->tzqcs = max(64u, ps_to_tCK(80000, freq));
>> + pctl_timing->tzqcsi = 10000; /* as used by Rockchip */
>> + pctl_timing->tdqs = 1; /* fixed for DDR3 */
>> + pctl_timing->tcksre = max(5u, ps_to_tCK(10000, freq));
>> + pctl_timing->tcksrx = max(5u, ps_to_tCK(10000, freq));
>> + pctl_timing->tcke = max(3u, ps_to_tCK(5000, freq));
>> + pctl_timing->tmod = max(12u, ps_to_tCK(15000, freq));
>> + pctl_timing->trstl = ns_to_tCK(100, freq);
>> + pctl_timing->tzqcl = max(256u, ps_to_tCK(320000, freq)); /* tZQoper */
>> + pctl_timing->tmrr = 0;
>> + pctl_timing->tckesr = pctl_timing->tcke + 1; /* JESD-79: tCKE + 1tCK */
>> + pctl_timing->tdpd = 0; /* RK3368 TRM: "allowed values for DDR3: 0" */
>> +
>> +
>> + /*
>> + * The controller can represent tFAW as 4x, 5x or 6x tRRD only.
>> + * We want to use the smallest multiplier that satisfies the tFAW
>> + * requirements of the given speed-bin. If necessary, we stretch out
>> + * tRRD to allow us to operate on a 6x multiplier for tFAW.
>> + */
>> + tfaw_as_ps = 40000; /* 40ns: tFAW for DDR3-1600K, 2KB page-size */
>> + if (tCK_to_ps(pctl_timing->trrd * 6, freq) < tfaw_as_ps) {
>> + /* If tFAW is > 6 x tRRD, we need to stretch tRRD */
>> + pctl_timing->trrd = ps_to_tCK(DIV_ROUND_UP(40000, 6), freq);
>> + params->tfaw_mult = TFAW_TRRD_MULT6;
>> + } else if (tCK_to_ps(pctl_timing->trrd * 5, freq) < tfaw_as_ps) {
>> + params->tfaw_mult = TFAW_TRRD_MULT6;
>> + } else if (tCK_to_ps(pctl_timing->trrd * 4, freq) < tfaw_as_ps) {
>> + params->tfaw_mult = TFAW_TRRD_MULT5;
>> + } else {
>> + params->tfaw_mult = TFAW_TRRD_MULT4;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static void pctl_cfg(struct rk3368_ddr_pctl *pctl,
>> + struct rk3368_sdram_params *params,
>> + struct rk3368_grf *grf)
>> +{
>> + /* Configure PCTL timing registers */
>> + params->pctl_timing.trefi |= BIT(31); /* see PCTL_TREFI */
>> + copy_to_reg(&pctl->togcnt1u, ¶ms->pctl_timing.togcnt1u,
>> + sizeof(params->pctl_timing));
>> + writel(params->trefi_mem_ddr3, &pctl->trefi_mem_ddr3);
>> +
>> + /* Set up ODT write selector and ODT write length */
>> + writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL), &pctl->dfiodtcfg);
>> + writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1);
>> +
>> + /* Set up the CL/CWL-dependent timings of DFI */
>> + writel((params->pctl_timing.tcl - 1) / 2 - 1, &pctl->dfitrddataen);
>> + writel((params->pctl_timing.tcwl - 1) / 2 - 1, &pctl->dfitphywrlat);
>> +
>> + /* DDR3 */
>> + writel(params->tfaw_mult | DDR3_EN | DDR2_DDR3_BL_8, &pctl->mcfg);
>> + writel(0x001c0004, &grf->ddrc0_con0);
>> +
>> + setbits_le32(&pctl->scfg, HW_LOW_POWER_EN);
>> +}
>> +
>> +static int ddrphy_data_training(struct rk3368_ddr_pctl *pctl,
>> + struct rk3368_ddrphy *ddrphy)
>> +{
>> + const u32 trefi = readl(&pctl->trefi);
>> + const ulong timeout_ms = 500;
>> + ulong tmp;
>> +
>> + /* disable auto-refresh */
>> + writel(0 | BIT(31), &pctl->trefi);
>> +
>> + clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x20);
>> + clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x21);
>> +
>> + tmp = get_timer(0);
>> + do {
>> + if (get_timer(tmp) > timeout_ms) {
>> + error("%s: did not complete within %ld ms\n",
>> + __func__, timeout_ms);
>> + return -ETIME;
>> + }
>> + } while ((readl(&ddrphy->reg[0xff]) & 0xf) != 0xf);
>> +
>> + send_command(pctl, MCMD_RANK0 | MCMD_RANK1, PREA_CMD);
>> + clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x20);
>> + /* resume auto-refresh */
>> + writel(trefi | BIT(31), &pctl->trefi);
>> +
>> + return 0;
>> +}
>> +
>> +static int sdram_col_row_detect(struct udevice *dev)
>> +{
>> + struct dram_info *priv = dev_get_priv(dev);
>> + struct rk3368_sdram_params *params = dev_get_platdata(dev);
>> + struct rk3368_ddr_pctl *pctl = priv->pctl;
>> + struct rk3368_msch *msch = priv->msch;
>> + const u32 test_pattern = 0x5aa5f00f;
>> + int row, col;
>> + uintptr_t addr;
>> +
>> + move_to_config_state(pctl);
>> + writel(6, &msch->ddrconf);
>> + move_to_access_state(pctl);
>> +
>> + /* Detect col */
>> + for (col = 11; col >= 9; col--) {
>> + writel(0, CONFIG_SYS_SDRAM_BASE);
>> + addr = CONFIG_SYS_SDRAM_BASE +
>> + (1 << (col + params->chan.bw - 1));
>> + writel(test_pattern, addr);
>> + if ((readl(addr) == test_pattern) &&
>> + (readl(CONFIG_SYS_SDRAM_BASE) == 0))
>> + break;
>> + }
>> +
>> + if (col == 8) {
>> + error("%s: col detect error\n", __func__);
>> + return -EINVAL;
>> + }
>> +
>> + move_to_config_state(pctl);
>> + writel(15, &msch->ddrconf);
>> + move_to_access_state(pctl);
>> +
>> + /* Detect row*/
>> + for (row = 16; row >= 12; row--) {
>> + writel(0, CONFIG_SYS_SDRAM_BASE);
>> + addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
>> + writel(test_pattern, addr);
>> + if ((readl(addr) == test_pattern) &&
>> + (readl(CONFIG_SYS_SDRAM_BASE) == 0))
>> + break;
>> + }
>> +
>> + if (row == 11) {
>> + error("%s: row detect error\n", __func__);
>> + return -EINVAL;
>> + }
>> +
>> + /* Record results */
>> + debug("%s: col %d, row %d\n", __func__, col, row);
>> + params->chan.col = col;
>> + params->chan.cs0_row = row;
>> + params->chan.cs1_row = row;
>> + params->chan.row_3_4 = 0;
>> +
>> + return 0;
>> +}
>> +
>> +static int msch_niu_config(struct rk3368_msch *msch,
>> + struct rk3368_sdram_params *params)
>> +{
>> + int i;
>> + const u8 cols = params->chan.col - ((params->chan.bw == 2) ? 0 : 1);
>> + const u8 rows = params->chan.cs0_row;
>> +
>> + /*
>> + * The DDR address-translation table always assumes a 32bit
>> + * bus and the comparison below takes care of adjusting for
>> + * a 16bit bus (i.e. one column-address is consumed).
>> + */
>> + const struct {
>> + u8 rows;
>> + u8 columns;
>> + u8 type;
>> + } ddrconf_table[] = {
>> + /*
>> + * C-B-R-D patterns are first. For these we require an
>> + * exact match for the columns and rows (as there's
>> + * one entry per possible configuration).
>> + */
>> + [0] = { .rows = 13, .columns = 10, .type = DMC_MSCH_CBRD },
>> + [1] = { .rows = 14, .columns = 10, .type = DMC_MSCH_CBRD },
>> + [2] = { .rows = 15, .columns = 10, .type = DMC_MSCH_CBRD },
>> + [3] = { .rows = 16, .columns = 10, .type = DMC_MSCH_CBRD },
>> + [4] = { .rows = 14, .columns = 11, .type = DMC_MSCH_CBRD },
>> + [5] = { .rows = 15, .columns = 11, .type = DMC_MSCH_CBRD },
>> + [6] = { .rows = 16, .columns = 11, .type = DMC_MSCH_CBRD },
>> + [7] = { .rows = 13, .columns = 9, .type = DMC_MSCH_CBRD },
>> + [8] = { .rows = 14, .columns = 9, .type = DMC_MSCH_CBRD },
>> + [9] = { .rows = 15, .columns = 9, .type = DMC_MSCH_CBRD },
>> + [10] = { .rows = 16, .columns = 9, .type = DMC_MSCH_CBRD },
>> + /*
>> + * 11 through 13 are C-R-B-D patterns. These are
>> + * matched for an exact number of columns and to
>> + * ensure that the hardware uses at least as many rows
>> + * as the pattern requires (i.e. we make sure that
>> + * there's no gaps up until we hit the device/chip-select;
>> + * however, these patterns can accept up to 16 rows,
>> + * as the row-address continues right after the CS
>> + * switching)
>> + */
>> + [11] = { .rows = 15, .columns = 10, .type = DMC_MSCH_CRBD },
>> + [12] = { .rows = 14, .columns = 11, .type = DMC_MSCH_CRBD },
>> + [13] = { .rows = 13, .columns = 10, .type = DMC_MSCH_CRBD },
>> + /*
>> + * 14 and 15 are catch-all variants using a C-B-D-R
>> + * scheme (i.e. alternating the chip-select every time
>> + * C-B overflows) and stuffing the remaining C-bits
>> + * into the top. Matching needs to make sure that the
>> + * number of columns is either an exact match (i.e. we
>> + * can use less the the maximum number of rows) -or-
>> + * that the columns exceed what is given in this table
>> + * and the rows are an exact match (in which case the
>> + * remaining C-bits will be stuffed onto the top after
>> + * the device/chip-select switches).
>> + */
>> + [14] = { .rows = 16, .columns = 10, .type = DMC_MSCH_CBDR },
>> + [15] = { .rows = 16, .columns = 9, .type = DMC_MSCH_CBDR },
>> + };
>> +
>> + /*
>> + * For C-B-R-D, we need an exact match (i.e. both for the number of
>> + * columns and rows), while for C-B-D-R, only the the number of
>> + * columns needs to match.
>> + */
>> + for (i = 0; i < ARRAY_SIZE(ddrconf_table); i++) {
>> + bool match = false;
>> +
>> + /* If this entry if for a different matcher, then skip it */
>> + if (ddrconf_table[i].type != params->memory_schedule)
>> + continue;
>> +
>> + /*
>> + * Match according to the rules (exact/inexact/at-least)
>> + * documented in the ddrconf_table above.
>> + */
>> + switch (params->memory_schedule) {
>> + case DMC_MSCH_CBRD:
>> + match = (ddrconf_table[i].columns == cols) &&
>> + (ddrconf_table[i].rows == rows);
>> + break;
>> +
>> + case DMC_MSCH_CRBD:
>> + match = (ddrconf_table[i].columns == cols) &&
>> + (ddrconf_table[i].rows <= rows);
>> + break;
>> +
>> + case DMC_MSCH_CBDR:
>> + match = (ddrconf_table[i].columns == cols) ||
>> + ((ddrconf_table[i].columns <= cols) &&
>> + (ddrconf_table[i].rows == rows));
>> + break;
>> +
>> + default:
>> + break;
>> + }
>> +
>> + if (match) {
>> + debug("%s: setting ddrconf 0x%x\n", __func__, i);
>> + writel(i, &msch->ddrconf);
>> + return 0;
>> + }
>> + }
>> +
>> + error("%s: ddrconf (NIU config) not found\n", __func__);
>> + return -EINVAL;
>> +}
>> +
>> +static void dram_all_config(struct udevice *dev)
>> +{
>> + struct dram_info *priv = dev_get_priv(dev);
>> + struct rk3368_pmu_grf *pmugrf = priv->pmugrf;
>> + struct rk3368_sdram_params *params = dev_get_platdata(dev);
>> + const struct rk3288_sdram_channel *info = ¶ms->chan;
>> + u32 sys_reg = 0;
>> + const int chan = 0;
>> +
>> + sys_reg |= DDR3 << SYS_REG_DDRTYPE_SHIFT;
>> + sys_reg |= 0 << SYS_REG_NUM_CH_SHIFT;
>> +
>> + sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan);
>> + sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan);
>> + sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan);
>> + sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan);
>> + sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan);
>> + sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan);
>> + sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan);
>> + sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan);
>> + sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan);
>> +
>> + writel(sys_reg, &pmugrf->os_reg[2]);
>> +}
>> +
>> +static int setup_sdram(struct udevice *dev)
>> +{
>> + struct dram_info *priv = dev_get_priv(dev);
>> + struct rk3368_sdram_params *params = dev_get_platdata(dev);
>> +
>> + struct rk3368_ddr_pctl *pctl = priv->pctl;
>> + struct rk3368_ddrphy *ddrphy = priv->phy;
>> + struct rk3368_cru *cru = priv->cru;
>> + struct rk3368_grf *grf = priv->grf;
>> + struct rk3368_msch *msch = priv->msch;
>> +
>> + int ret;
>> +
>> + /* The input clock (i.e. DPLL) needs to be 2x the DRAM frequency */
>> + ret = clk_set_rate(&priv->ddr_clk, 2 * params->ddr_freq);
>> + if (ret < 0) {
>> + debug("%s: could not set DDR clock: %d\n", __func__, ret);
>> + return ret;
>> + }
>> +
>> + /* Update the read-latency for the RK3368 */
>> + writel(0x32, &msch->readlatency);
>> +
>> + /* Initialise the DDR PCTL and DDR PHY */
>> + ddrctl_reset(cru);
>> + ddrphy_reset(ddrphy);
>> + ddrphy_config_delays(ddrphy, params->ddr_freq);
>> + dfi_cfg(pctl);
>> + /* Configure relative system information of grf_ddrc0_con0 register */
>> + ddr_set_ddr3_mode(grf, true);
>> + ddr_set_noc_spr_err_stall(grf, true);
>> + /* Calculate timings */
>> + pctl_calc_timings(params, params->ddr_freq);
>> + /* Initialise the device timings in protocol controller */
>> + pctl_cfg(pctl, params, grf);
>> + /* Configure AL, CL ... information of PHY registers */
>> + ddrphy_config(ddrphy,
>> + params->pctl_timing.tcl,
>> + params->pctl_timing.tal,
>> + params->pctl_timing.tcwl);
>> +
>> + /* Initialize DRAM and configure with mode-register values */
>> + ret = memory_init(pctl, params);
>> + if (ret)
>> + goto error;
>> +
>> + move_to_config_state(pctl);
>> + /* Perform data-training */
>> + ddrphy_data_training(pctl, ddrphy);
>> + move_to_access_state(pctl);
>> +
>> + /* TODO(prt): could detect rank in training... */
>> + params->chan.rank = 2;
>> + /* TODO(prt): bus width is not auto-detected (yet)... */
>> + params->chan.bw = 2; /* 32bit wide bus */
>> + params->chan.dbw = params->chan.dbw; /* 32bit wide bus */
>> +
>> + /* DDR3 is always 8 bank */
>> + params->chan.bk = 3;
>> + /* Detect col and row number */
>> + ret = sdram_col_row_detect(dev);
>> + if (ret)
>> + goto error;
>> +
>> + /* Configure NIU DDR configuration */
>> + ret = msch_niu_config(msch, params);
>> + if (ret)
>> + goto error;
>> +
>> + /* set up OS_REG to communicate w/ next stage and OS */
>> + dram_all_config(dev);
>> +
>> + return 0;
>> +
>> +error:
>> + printf("DRAM init failed!\n");
>> + hang();
>> +}
>> +#endif
>> +
>> +static int rk3368_dmc_ofdata_to_platdata(struct udevice *dev)
>> +{
>> + int ret = 0;
>> +
>> +#if !CONFIG_IS_ENABLED(OF_PLATDATA)
>> + struct rk3368_sdram_params *plat = dev_get_platdata(dev);
>> +
>> + ret = regmap_init_mem(dev, &plat->map);
>> + if (ret)
>> + return ret;
>> +#endif
>> +
>> + return ret;
>> +}
>> +
>> +#if CONFIG_IS_ENABLED(OF_PLATDATA)
>> +static int conv_of_platdata(struct udevice *dev)
>> +{
>> + struct rk3368_sdram_params *plat = dev_get_platdata(dev);
>> + struct dtd_rockchip_rk3368_dmc *of_plat = &plat->of_plat;
>> + int ret;
>> +
>> + plat->ddr_freq = of_plat->rockchip_ddr_frequency;
>> + plat->ddr_speed_bin = of_plat->rockchip_ddr_speed_bin;
>> + plat->memory_schedule = of_plat->rockchip_memory_schedule;
>> +
>> + ret = regmap_init_mem_platdata(dev, of_plat->reg,
>> + ARRAY_SIZE(of_plat->reg) / 2,
>> + &plat->map);
>> + if (ret)
>> + return ret;
>> +
>> + return 0;
>> +}
>> +#endif
>> +
>> +static int rk3368_dmc_probe(struct udevice *dev)
>> +{
>> +#ifdef CONFIG_TPL_BUILD
>> + struct rk3368_sdram_params *plat = dev_get_platdata(dev);
>> + struct rk3368_ddr_pctl *pctl;
>> + struct rk3368_ddrphy *ddrphy;
>> + struct rk3368_cru *cru;
>> + struct rk3368_grf *grf;
>> + struct rk3368_msch *msch;
>> + int ret;
>> + struct udevice *dev_clk;
>> +#endif
>> + struct dram_info *priv = dev_get_priv(dev);
>> +
>> +#if CONFIG_IS_ENABLED(OF_PLATDATA)
>> + ret = conv_of_platdata(dev);
>> + if (ret)
>> + return ret;
>> +#endif
>> +
>> + priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
>> + debug("%s: pmugrf=%p\n", __func__, priv->pmugrf);
>> +
>> +#ifdef CONFIG_TPL_BUILD
>> + pctl = regmap_get_range(plat->map, 0);
>> + ddrphy = regmap_get_range(plat->map, 1);
>> + msch = syscon_get_first_range(ROCKCHIP_SYSCON_MSCH);
>> + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
>> +
>> + priv->pctl = pctl;
>> + priv->phy = ddrphy;
>> + priv->msch = msch;
>> + priv->grf = grf;
>> +
>> + ret = rockchip_get_clk(&dev_clk);
>> + if (ret)
>> + return ret;
>> + priv->ddr_clk.id = CLK_DDR;
>> + ret = clk_request(dev_clk, &priv->ddr_clk);
>> + if (ret)
>> + return ret;
>> +
>> + cru = rockchip_get_cru();
>> + priv->cru = cru;
>> + if (IS_ERR(priv->cru))
>> + return PTR_ERR(priv->cru);
>> +
>> + ret = setup_sdram(dev);
>> + if (ret)
>> + return ret;
>> +#endif
>> +
>> + priv->info.base = 0;
>> + priv->info.size =
>> + rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg[2]);
>> +
>> + /*
>> + * we use the 0x00000000~0xfdffffff space since 0xff000000~0xffffffff
>> + * is SoC register space (i.e. reserved), and 0xfe000000~0xfeffffff is
>> + * inaccessible for some IP controller.
>> + */
>> + priv->info.size = min(priv->info.size, (size_t)0xfe000000);
>> +
>> + return 0;
>> +}
>> +
>> +static int rk3368_dmc_get_info(struct udevice *dev, struct ram_info *info)
>> +{
>> + struct dram_info *priv = dev_get_priv(dev);
>> +
>> + *info = priv->info;
>> + return 0;
>> +}
>> +
>> +static struct ram_ops rk3368_dmc_ops = {
>> + .get_info = rk3368_dmc_get_info,
>> +};
>> +
>> +
>> +static const struct udevice_id rk3368_dmc_ids[] = {
>> + { .compatible = "rockchip,rk3368-dmc" },
>> + { }
>> +};
>> +
>> +U_BOOT_DRIVER(dmc_rk3368) = {
>> + .name = "rockchip_rk3368_dmc",
>> + .id = UCLASS_RAM,
>> + .of_match = rk3368_dmc_ids,
>> + .ops = &rk3368_dmc_ops,
>> + .probe = rk3368_dmc_probe,
>> + .priv_auto_alloc_size = sizeof(struct dram_info),
>> + .ofdata_to_platdata = rk3368_dmc_ofdata_to_platdata,
>> + .probe = rk3368_dmc_probe,
>> + .priv_auto_alloc_size = sizeof(struct dram_info),
>> + .platdata_auto_alloc_size = sizeof(struct rk3368_sdram_params),
>> +};
>> diff --git a/include/dt-bindings/memory/rk3368-dmc.h b/include/dt-bindings/memory/rk3368-dmc.h
>> new file mode 100644
>> index 0000000..b06ffde
>> --- /dev/null
>> +++ b/include/dt-bindings/memory/rk3368-dmc.h
>> @@ -0,0 +1,30 @@
>> +#ifndef DT_BINDINGS_RK3368_DMC_H
>> +#define DT_BINDINGS_RK3368_DMC_H
>> +
>> +#define DMC_MSCH_CBDR 0x0
>> +#define DMC_MSCH_CBRD 0x1
>> +#define DMC_MSCH_CRBD 0x2
>> +
>> +#define DDR3_800D 0
>> +#define DDR3_800E 1
>> +#define DDR3_1066E 2
>> +#define DDR3_1066F 3
>> +#define DDR3_1066G 4
>> +#define DDR3_1333F 5
>> +#define DDR3_1333G 6
>> +#define DDR3_1333H 7
>> +#define DDR3_1333J 8
>> +#define DDR3_1600G 9
>> +#define DDR3_1600H 10
>> +#define DDR3_1600J 11
>> +#define DDR3_1600K 12
>> +#define DDR3_1866J 13
>> +#define DDR3_1866K 14
>> +#define DDR3_1866L 15
>> +#define DDR3_1866M 16
>> +#define DDR3_2133K 17
>> +#define DDR3_2133L 18
>> +#define DDR3_2133M 19
>> +#define DDR3_2133N 20
>> +
>> +#endif
^ permalink raw reply [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 50/66] rockchip: rk3368: add DRAM controller driver with DRAM initialisation
2017-08-02 10:59 ` Dr. Philipp Tomsich
@ 2017-08-02 12:09 ` Andy Yan
0 siblings, 0 replies; 95+ messages in thread
From: Andy Yan @ 2017-08-02 12:09 UTC (permalink / raw)
To: u-boot
Hi Philipp:
On 2017年08月02日 18:59, Dr. Philipp Tomsich wrote:
> Andy,
>
> The functionality of the new driver should be equivalent for the non-TPL case.
> All the code from the original driver is still present in the new driver for non-TPL
> (see rk3368_dmc_probe).
Yes, it's so good that the new rk3368 dmc driver also has this
function.
I also need to add a xxx-u-boot.dtsi for the other rk3368 based boards.
>
> Seeing that -19 is -ENODEV, I suspect that something went wrong in the DM
> binding/probing: did you set 'status = “okay”’ for the DMC?
>
> Regards,
> Phil.
>
>> On 02 Aug 2017, at 12:06, Andy Yan <andy.yan@rock-chips.com> wrote:
>>
>> Hi Philipp:
>>
>>
>> On 2017年07月29日 03:22, Philipp Tomsich wrote:
>>> This adds a DRAM controller driver for the RK3368 and places it in
>>> drivers/ram/rockchip (where the other DM-enabled DRAM controller
>>> drivers for rockchip devices should also be moved eventually).
>>>
>>> At this stage, only the following feature-set is supported:
>>> - DDR3
>>> - 32-bit configuration (i.e. fully populated)
>>> - dual-rank (i.e. no auto-detection of ranks)
>>> - DDR3-1600K speed-bin
>>>
>>> This driver expects to run from a TPL stage that will later return to
>>> the RK3368 BROM. It communicates with later stages through the
>>> os_reg2 in the pmugrf (i.e. using the same mechanism as Rockchip's DDR
>>> init code).
>>>
>>> Unlike other DMC drivers for RK32xx and RK33xx parts, the required
>>> timings are calculated within the driver based on a target frequency
>>> and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this
>>> time).
>>>
>>> The RK3368 also has the DDRC0_CON0 (DDR ch. 0, control-register 0)
>>> register for controlling the operation of its (single-channel) DRAM
>>> controller in the GRF block. This provides for selecting DDR3, mobile
>>> DDR modes, and control low-power operation.
>>> As part of this change, DDRC0_CON0 is also added to the GRF structure
>>> definition (at offset 0x600).
>>>
>>> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>>>
>>> Reviewed-by: Simon Glass <sjg@chromium.org>
>>> ---
>>>
>>> Changes in v3:
>>> - correctly states the location of the driver in the commit message
>>>
>>> Changes in v2: None
>>>
>>> arch/arm/include/asm/arch-rockchip/ddr_rk3368.h | 187 ++++
>>> arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 3 +
>>> arch/arm/mach-rockchip/rk3368/Makefile | 1 -
>>> arch/arm/mach-rockchip/rk3368/sdram_rk3368.c | 60 --
>>> .../clock/rockchip,rk3368-dmc.txt | 67 ++
>>> drivers/ram/Makefile | 2 +
>>> drivers/ram/rockchip/Makefile | 7 +
>>> drivers/ram/rockchip/dmc-rk3368.c | 990 +++++++++++++++++++++
>>> include/dt-bindings/memory/rk3368-dmc.h | 30 +
>>> 9 files changed, 1286 insertions(+), 61 deletions(-)
>>> create mode 100644 arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
>>> delete mode 100644 arch/arm/mach-rockchip/rk3368/sdram_rk3368.c
>>> create mode 100644 doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt
>>> create mode 100644 drivers/ram/rockchip/Makefile
>>> create mode 100644 drivers/ram/rockchip/dmc-rk3368.c
>>> create mode 100644 include/dt-bindings/memory/rk3368-dmc.h
>>>
>>> diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h b/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
>>> new file mode 100644
>>> index 0000000..4e2b233
>>> --- /dev/null
>>> +++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
>>> @@ -0,0 +1,187 @@
>>> +/*
>>> + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
>>> + *
>>> + * SPDX-License-Identifier: GPL-2.0
>>> + */
>>> +
>>> +#ifndef __ASM_ARCH_DDR_RK3368_H__
>>> +#define __ASM_ARCH_DDR_RK3368_H__
>>> +
>>> +/*
>>> + * The RK3368 DDR PCTL differs from the incarnation in the RK3288 only
>>> + * in a few details. Most notably, it has an additional field to track
>>> + * tREFI in controller cycles (i.e. trefi_mem_ddr3).
>>> + */
>>> +struct rk3368_ddr_pctl {
>>> + u32 scfg;
>>> + u32 sctl;
>>> + u32 stat;
>>> + u32 intrstat;
>>> + u32 reserved0[12];
>>> + u32 mcmd;
>>> + u32 powctl;
>>> + u32 powstat;
>>> + u32 cmdtstat;
>>> + u32 cmdtstaten;
>>> + u32 reserved1[3];
>>> + u32 mrrcfg0;
>>> + u32 mrrstat0;
>>> + u32 mrrstat1;
>>> + u32 reserved2[4];
>>> + u32 mcfg1;
>>> + u32 mcfg;
>>> + u32 ppcfg;
>>> + u32 mstat;
>>> + u32 lpddr2zqcfg;
>>> + u32 reserved3;
>>> + u32 dtupdes;
>>> + u32 dtuna;
>>> + u32 dtune;
>>> + u32 dtuprd0;
>>> + u32 dtuprd1;
>>> + u32 dtuprd2;
>>> + u32 dtuprd3;
>>> + u32 dtuawdt;
>>> + u32 reserved4[3];
>>> + u32 togcnt1u;
>>> + u32 tinit;
>>> + u32 trsth;
>>> + u32 togcnt100n;
>>> + u32 trefi;
>>> + u32 tmrd;
>>> + u32 trfc;
>>> + u32 trp;
>>> + u32 trtw;
>>> + u32 tal;
>>> + u32 tcl;
>>> + u32 tcwl;
>>> + u32 tras;
>>> + u32 trc;
>>> + u32 trcd;
>>> + u32 trrd;
>>> + u32 trtp;
>>> + u32 twr;
>>> + u32 twtr;
>>> + u32 texsr;
>>> + u32 txp;
>>> + u32 txpdll;
>>> + u32 tzqcs;
>>> + u32 tzqcsi;
>>> + u32 tdqs;
>>> + u32 tcksre;
>>> + u32 tcksrx;
>>> + u32 tcke;
>>> + u32 tmod;
>>> + u32 trstl;
>>> + u32 tzqcl;
>>> + u32 tmrr;
>>> + u32 tckesr;
>>> + u32 t
>>>
>>> Hi Philipp:
>>>
>>>
>>> On 2017年07月29日 03:22, Philipp Tomsich wrote:
>>>> This adds a DRAM controller driver for the RK3368 and places it in
>>>> drivers/ram/rockchip (where the other DM-enabled DRAM controller
>>>> drivers for rockchip devices should also be moved eventually).
>>>>
>>>> At this stage, only the following feature-set is supported:
>>>> - DDR3
>>>> - 32-bit configuration (i.e. fully populated)
>>>> - dual-rank (i.e. no auto-detection of ranks)
>>>> - DDR3-1600K speed-bin
>>>>
>>>> This driver expects to run from a TPL stage that will later return to
>>>> the RK3368 BROM. It communicates with later stages through the
>>>> os_reg2 in the pmugrf (i.e. using the same mechanism as Rockchip's DDR
>>>> init code).
>>>>
>>>> Unlike other DMC drivers for RK32xx and RK33xx parts, the required
>>>> timings are calculated within the driver based on a target frequency
>>>> and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this
>>>> time).
>>>>
>>>> The RK3368 also has the DDRC0_CON0 (DDR ch. 0, control-register 0)
>>>> register for controlling the operation of its (single-channel) DRAM
>>>> controller in the GRF block. This provides for selecting DDR3, mobile
>>>> DDR modes, and control low-power operation.
>>>> As part of this change, DDRC0_CON0 is also added to the GRF structure
>>>> definition (at offset 0x600).
>>>>
>>>> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>>>>
>>>> Reviewed-by: Simon Glass <sjg@chromium.org>
>>>> ---
>>>>
>>>> Changes in v3:
>>>> - correctly states the location of the driver in the commit message
>>>>
>>>> Changes in v2: None
>>>>
>>>> arch/arm/include/asm/arch-rockchip/ddr_rk3368.h | 187 ++++
>>>> arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 3 +
>>>> arch/arm/mach-rockchip/rk3368/Makefile | 1 -
>>>> arch/arm/mach-rockchip/rk3368/sdram_rk3368.c | 60 --
>>>> .../clock/rockchip,rk3368-dmc.txt | 67 ++
>>>> drivers/ram/Makefile | 2 +
>>>> drivers/ram/rockchip/Makefile | 7 +
>>>> drivers/ram/rockchip/dmc-rk3368.c | 990 +++++++++++++++++++++
>>>> include/dt-bindings/memory/rk3368-dmc.h | 30 +
>>>> 9 files changed, 1286 insertions(+), 61 deletions(-)
>>>> create mode 100644 arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
>>>> delete mode 100644 arch/arm/mach-rockchip/rk3368/sdram_rk3368.c
>>>> create mode 100644 doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt
>>>> create mode 100644 drivers/ram/rockchip/Makefile
>>>> create mode 100644 drivers/ram/rockchip/dmc-rk3368.c
>>>> create mode 100644 include/dt-bindings/memory/rk3368-dmc.h
>>>>
>>>> diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h b/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
>>>> new file mode 100644
>>>> index 0000000..4e2b233
>>>> --- /dev/null
>>>> +++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
>>>> @@ -0,0 +1,187 @@
>>>> +/*
>>>> + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
>>>> + *
>>>> + * SPDX-License-Identifier: GPL-2.0
>>>> + */
>>>> +
>>>> +#ifndef __ASM_ARCH_DDR_RK3368_H__
>>>> +#define __ASM_ARCH_DDR_RK3368_H__
>>>> +
>>>> +/*
>>>> + * The RK3368 DDR PCTL differs from the incarnation in the RK3288 only
>>>> + * in a few details. Most notably, it has an additional field to track
>>>> + * tREFI in controller cycles (i.e. trefi_mem_ddr3).
>>>> + */
>>>> +struct rk3368_ddr_pctl {
>>>> + u32 scfg;
>>>> + u32 sctl;
>>>> + u32 stat;
>>>> + u32 intrstat;
>>>> + u32 reserved0[12];
>>>> + u32 mcmd;
>>>> + u32 powctl;
>>>> + u32 powstat;
>>>> + u32 cmdtstat;
>>>> + u32 cmdtstaten;
>>>> + u32 reserved1[3];
>>>> + u32 mrrcfg0;
>>>> + u32 mrrstat0;
>>>> + u32 mrrstat1;
>>>> + u32 reserved2[4];
>>>> + u32 mcfg1;
>>>> + u32 mcfg;
>>>> + u32 ppcfg;
>>>> + u32 mstat;
>>>> + u32 lpddr2zqcfg;
>>>> + u32 reserved3;
>>>> + u32 dtupdes;
>>>> + u32 dtuna;
>>>> + u32 dtune;
>>>> + u32 dtuprd0;
>>>> + u32 dtuprd1;
>>>> + u32 dtuprd2;
>>>> + u32 dtuprd3;
>>>> + u32 dtuawdt;
>>>> + u32 reserved4[3];
>>>> + u32 togcnt1u;
>>>> + u32 tinit;
>>>> + u32 trsth;
>>>> + u32 togcnt100n;
>>>> + u32 trefi;
>>>> + u32 tmrd;
>>>> + u32 trfc;
>>>> + u32 trp;
>>>> + u32 trtw;
>>>> + u32 tal;
>>>> + u32 tcl;
>>>> + u32 tcwl;
>>>> + u32 tras;
>>>> + u32 trc;
>>>> + u32 trcd;
>>>> + u32 trrd;
>>>> + u32 trtp;
>>>> + u32 twr;
>>>> + u32 twtr;
>>>> + u32 texsr;
>>>> + u32 txp;
>>>> + u32 txpdll;
>>>> + u32 tzqcs;
>>>> + u32 tzqcsi;
>>>> + u32 tdqs;
>>>> + u32 tcksre;
>>>> + u32 tcksrx;
>>>> + u32 tcke;
>>>> + u32 tmod;
>>>> + u32 trstl;
>>>> + u32 tzqcl;
>>>> + u32 tmrr;
>>>> + u32 tckesr;
>>>> + u32 tdpd;
>>>> + u32 trefi_mem_ddr3;
>>>> + u32 reserved5[45];
>>>> + u32 dtuwactl;
>>>> + u32 dturactl;
>>>> + u32 dtucfg;
>>>> + u32 dtuectl;
>>>> + u32 dtuwd0;
>>>> + u32 dtuwd1;
>>>> + u32 dtuwd2;
>>>> + u32 dtuwd3;
>>>> + u32 dtuwdm;
>>>> + u32 dturd0;
>>>> + u32 dturd1;
>>>> + u32 dturd2;
>>>> + u32 dturd3;
>>>> + u32 dtulfsrwd;
>>>> + u32 dtulfsrrd;
>>>> + u32 dtueaf;
>>>> + u32 dfitctrldelay;
>>>> + u32 dfiodtcfg;
>>>> + u32 dfiodtcfg1;
>>>> + u32 dfiodtrankmap;
>>>> + u32 dfitphywrdata;
>>>> + u32 dfitphywrlat;
>>>> + u32 reserved7[2];
>>>> + u32 dfitrddataen;
>>>> + u32 dfitphyrdlat;
>>>> + u32 reserved8[2];
>>>> + u32 dfitphyupdtype0;
>>>> + u32 dfitphyupdtype1;
>>>> + u32 dfitphyupdtype2;
>>>> + u32 dfitphyupdtype3;
>>>> + u32 dfitctrlupdmin;
>>>> + u32 dfitctrlupdmax;
>>>> + u32 dfitctrlupddly;
>>>> + u32 reserved9;
>>>> + u32 dfiupdcfg;
>>>> + u32 dfitrefmski;
>>>> + u32 dfitctrlupdi;
>>>> + u32 reserved10[4];
>>>> + u32 dfitrcfg0;
>>>> + u32 dfitrstat0;
>>>> + u32 dfitrwrlvlen;
>>>> + u32 dfitrrdlvlen;
>>>> + u32 dfitrrdlvlgateen;
>>>> + u32 dfiststat0;
>>>> + u32 dfistcfg0;
>>>> + u32 dfistcfg1;
>>>> + u32 reserved11;
>>>> + u32 dfitdramclken;
>>>> + u32 dfitdramclkdis;
>>>> + u32 dfistcfg2;
>>>> + u32 dfistparclr;
>>>> + u32 dfistparlog;
>>>> + u32 reserved12[3];
>>>> + u32 dfilpcfg0;
>>>> + u32 reserved13[3];
>>>> + u32 dfitrwrlvlresp0;
>>>> + u32 dfitrwrlvlresp1;
>>>> + u32 dfitrwrlvlresp2;
>>>> + u32 dfitrrdlvlresp0;
>>>> + u32 dfitrrdlvlresp1;
>>>> + u32 dfitrrdlvlresp2;
>>>> + u32 dfitrwrlvldelay0;
>>>> + u32 dfitrwrlvldelay1;
>>>> + u32 dfitrwrlvldelay2;
>>>> + u32 dfitrrdlvldelay0;
>>>> + u32 dfitrrdlvldelay1;
>>>> + u32 dfitrrdlvldelay2;
>>>> + u32 dfitrrdlvlgatedelay0;
>>>> + u32 dfitrrdlvlgatedelay1;
>>>> + u32 dfitrrdlvlgatedelay2;
>>>> + u32 dfitrcmd;
>>>> + u32 reserved14[46];
>>>> + u32 ipvr;
>>>> + u32 iptr;
>>>> +};
>>>> +check_member(rk3368_ddr_pctl, iptr, 0x03fc);
>>>> +
>>>> +struct rk3368_ddrphy {
>>>> + u32 reg[0x100];
>>>> +};
>>>> +check_member(rk3368_ddrphy, reg[0xff], 0x03fc);
>>>> +
>>>> +struct rk3368_msch {
>>>> + u32 coreid;
>>>> + u32 revisionid;
>>>> + u32 ddrconf;
>>>> + u32 ddrtiming;
>>>> + u32 ddrmode;
>>>> + u32 readlatency;
>>>> + u32 reserved1[8];
>>>> + u32 activate;
>>>> + u32 devtodev;
>>>> +};
>>>> +check_member(rk3368_msch, devtodev, 0x003c);
>>>> +
>>>> +/* GRF_SOC_CON0 */
>>>> +enum {
>>>> + NOC_RSP_ERR_STALL = BIT(9),
>>>> + MOBILE_DDR_SEL = BIT(4),
>>>> + DDR0_16BIT_EN = BIT(3),
>>>> + MSCH0_MAINDDR3_DDR3 = BIT(2),
>>>> + MSCH0_MAINPARTIALPOP = BIT(1),
>>>> + UPCTL_C_ACTIVE = BIT(0),
>>>> +};
>>>> +
>>>> +#endif
>>>> diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
>>>> index 1f84ff9..6b6651a 100644
>>>> --- a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
>>>> +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
>>>> @@ -76,8 +76,11 @@ struct rk3368_grf {
>>>> u32 soc_con15;
>>>> u32 soc_con16;
>>>> u32 soc_con17;
>>>> + u32 reserved5[0x6e];
>>>> + u32 ddrc0_con0;
>>>> };
>>>> check_member(rk3368_grf, soc_con17, 0x444);
>>>> +check_member(rk3368_grf, ddrc0_con0, 0x600);
>>>> struct rk3368_pmu_grf {
>>>> u32 gpio0a_iomux;
>>>> diff --git a/arch/arm/mach-rockchip/rk3368/Makefile b/arch/arm/mach-rockchip/rk3368/Makefile
>>>> index 0390716..46798c2 100644
>>>> --- a/arch/arm/mach-rockchip/rk3368/Makefile
>>>> +++ b/arch/arm/mach-rockchip/rk3368/Makefile
>>>> @@ -5,5 +5,4 @@
>>>> #
>>>> obj-y += clk_rk3368.o
>>>> obj-y += rk3368.o
>>>> -obj-y += sdram_rk3368.o
>>>> obj-y += syscon_rk3368.o
>>> the current PX5 EVB and Sheep board(they don't use spl now) depend on
>>> the sdram_rk3368 driver to get the sdram capacity, and so is the geekbox.
>>> They will be broken when this driver removed.
>>>
>>> We got the boot failed log on PX5 like bellow:
>>>
>>>> diff --git a/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c b/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c
>>>> deleted file mode 100644
>>>> index d0d0900..0000000
>>>> --- a/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c
>>>> +++ /dev/null
>>>> @@ -1,60 +0,0 @@
>>>> -/*
>>>> - * (C) Copyright 2016 Rockchip Electronics Co., Ltd.
>>>> - *
>>>> - * SPDX-License-Identifier: GPL-2.0
>>>> - */
>>>> -
>>>> -#include <common.h>
>>>> -#include <dm.h>
>>>> -#include <ram.h>
>>>> -#include <syscon.h>
>>>> -#include <asm/arch/clock.h>
>>>> -#include <asm/arch/grf_rk3368.h>
>>>> -#include <asm/arch/sdram_common.h>
>>>> -
>>>> -DECLARE_GLOBAL_DATA_PTR;
>>>> -struct dram_info {
>>>> - struct ram_info info;
>>>> - struct rk3368_pmu_grf *pmugrf;
>>>> -};
>>>> -
>>>> -static int rk3368_dmc_probe(struct udevice *dev)
>>>> -{
>>>> - struct dram_info *priv = dev_get_priv(dev);
>>>> -
>>>> - priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
>>>> - debug("%s: grf=%p\n", __func__, priv->pmugrf);
>>>> - priv->info.base = CONFIG_SYS_SDRAM_BASE;
>>>> - priv->info.size = rockchip_sdram_size(
>>>> - (phys_addr_t)&priv->pmugrf->os_reg[2]);
>>>> -
>>>> - return 0;
>>>> -}
>>>> -
>>>> -static int rk3368_dmc_get_info(struct udevice *dev, struct ram_info *info)
>>>> -{
>>>> - struct dram_info *priv = dev_get_priv(dev);
>>>> -
>>>> - *info = priv->info;
>>>> -
>>>> - return 0;
>>>> -}
>>>> -
>>>> -static struct ram_ops rk3368_dmc_ops = {
>>>> - .get_info = rk3368_dmc_get_info,
>>>> -};
>>>> -
>>>> -
>>>> -static const struct udevice_id rk3368_dmc_ids[] = {
>>>> - { .compatible = "rockchip,rk3368-dmc" },
>>>> - { }
>>>> -};
>>>> -
>>>> -U_BOOT_DRIVER(dmc_rk3368) = {
>>>> - .name = "rockchip_rk3368_dmc",
>>>> - .id = UCLASS_RAM,
>>>> - .of_match = rk3368_dmc_ids,
>>>> - .ops = &rk3368_dmc_ops,
>>>> - .probe = rk3368_dmc_probe,
>>>> - .priv_auto_alloc_size = sizeof(struct dram_info),
>>>> -};
>>>> diff --git a/doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt b/doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt
>>>> new file mode 100644
>>>> index 0000000..8e7357d
>>>> --- /dev/null
>>>> +++ b/doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt
>>>> @@ -0,0 +1,67 @@
>>>> +RK3368 dynamic memory controller driver
>>>> +=======================================
>>>> +
>>>> +The RK3368 DMC (dynamic memory controller) driver supports setup/initialisation
>>>> +during TPL using configuration data from the DTS (i.e. OF_PLATDATA), based on
>>>> +the following key configuration data:
>>>> + (a) a target-frequency (i.e. operating point) for the memory operation
>>>> + (b) a speed-bin (as defined in JESD-79) for the DDR3 used in hardware
>>>> + (c) a memory-schedule (i.e. mapping from physical addresses to the address
>>>> + pins of the memory bus)
>>>> +
>>>> +Required properties
>>>> +-------------------
>>>> +
>>>> +- compatible: "rockchip,rk3368-dmc"
>>>> +- reg
>>>> + protocol controller (PCTL) address and PHY controller (DDRPHY) address
>>>> +- rockchip,ddr-speed-bin
>>>> + the DDR3 device's speed-bin (as specified according to JESD-79)
>>>> + DDR3_800D (5-5-5)
>>>> + DDR3_800E (6-6-6)
>>>> + DDR3_1066E (6-6-6)
>>>> + DDR3_1066F (7-7-7)
>>>> + DDR3_1066G (8-8-8)
>>>> + DDR3_1333F (7-7-7)
>>>> + DDR3_1333G (8-8-8)
>>>> + DDR3_1333H (9-9-9)
>>>> + DDR3_1333J (10-10-10)
>>>> + DDR3_1600G (8-8-8)
>>>> + DDR3_1600H (9-9-9)
>>>> + DDR3_1600J (10-10-10)
>>>> + DDR3_1600K (11-11-11)
>>>> + DDR3_1866J (10-10-10)
>>>> + DDR3_1866K (11-11-11)
>>>> + DDR3_1866L (12-12-12)
>>>> + DDR3_1866M (13-13-13)
>>>> + DDR3_2133K (11-11-11)
>>>> + DDR3_2133L (12-12-12)
>>>> + DDR3_2133M (13-13-13)
>>>> + DDR3_2133N (14-14-14)
>>>> +- rockchip,ddr-frequency:
>>>> + target DDR clock frequency in Hz (not all frequencies may be supported,
>>>> + as there's some cooperation from the clock-driver required)
>>>> +- rockchip,memory-schedule:
>>>> + controls the decoding of physical addresses to DRAM addressing (i.e. how
>>>> + the physical address maps onto the address pins/chip-select of the device)
>>>> + DMC_MSCH_CBDR: column -> bank -> device -> row
>>>> + DMC_MSCH_CBRD: column -> band -> row -> device
>>>> + DMC_MSCH_CRBD: column -> row -> band -> device
>>>> +
>>>> +Example (for DDR3-1600K and 800MHz)
>>>> +-----------------------------------
>>>> +
>>>> + #include <dt-bindings/memory/rk3368-dmc.h>
>>>> +
>>>> + dmc: dmc at ff610000 {
>>>> + u-boot,dm-pre-reloc;
>>>> + compatible = "rockchip,rk3368-dmc";
>>>> + reg = <0 0xff610000 0 0x400
>>>> + 0 0xff620000 0 0x400>;
>>>> + };
>>>> +
>>>> + &dmc {
>>>> + rockchip,ddr-speed-bin = <DDR3_1600K>;
>>>> + rockchip,ddr-frequency = <800000000>;
>>>> + rockchip,memory-schedule = <DMC_MSCH_CBRD>;
>>>> + };
>>>> diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
>>>> index c409c48..51ae6be 100644
>>>> --- a/drivers/ram/Makefile
>>>> +++ b/drivers/ram/Makefile
>>>> @@ -8,3 +8,5 @@ obj-$(CONFIG_RAM) += ram-uclass.o
>>>> obj-$(CONFIG_SANDBOX) += sandbox_ram.o
>>>> obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o
>>>> obj-$(CONFIG_ARCH_BMIPS) += bmips_ram.o
>>>> +
>>>> +obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
>>>> diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile
>>>> new file mode 100644
>>>> index 0000000..b09d03c
>>>> --- /dev/null
>>>> +++ b/drivers/ram/rockchip/Makefile
>>>> @@ -0,0 +1,7 @@
>>>> +#
>>>> +# Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
>>>> +#
>>>> +# SPDX-License-Identifier: GPL-2.0+
>>>> +#
>>>> +
>>>> +obj-$(CONFIG_ROCKCHIP_RK3368) = dmc-rk3368.o
>>>> diff --git a/drivers/ram/rockchip/dmc-rk3368.c b/drivers/ram/rockchip/dmc-rk3368.c
>>>> new file mode 100644
>>>> index 0000000..fea96a5
>>>> --- /dev/null
>>>> +++ b/drivers/ram/rockchip/dmc-rk3368.c
>>>> @@ -0,0 +1,990 @@
>>>> +/*
>>>> + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
>>>> + *
>>>> + * SPDX-License-Identifier: GPL-2.0
>>>> + */
>>>> +
>>>> +#include <common.h>
>>>> +#include <clk.h>
>>>> +#include <dm.h>
>>>> +#include <dt-bindings/memory/rk3368-dmc.h>
>>>> +#include <dt-structs.h>
>>>> +#include <ram.h>
>>>> +#include <regmap.h>
>>>> +#include <syscon.h>
>>>> +#include <asm/io.h>
>>>> +#include <asm/arch/clock.h>
>>>> +#include <asm/arch/cru_rk3368.h>
>>>> +#include <asm/arch/grf_rk3368.h>
>>>> +#include <asm/arch/ddr_rk3368.h>
>>>> +#include <asm/arch/sdram.h>
>>>> +#include <asm/arch/sdram_common.h>
>>>> +
>>>> +DECLARE_GLOBAL_DATA_PTR;
>>>> +
>>>> +struct dram_info {
>>>> + struct ram_info info;
>>>> + struct clk ddr_clk;
>>>> + struct rk3368_cru *cru;
>>>> + struct rk3368_grf *grf;
>>>> + struct rk3368_ddr_pctl *pctl;
>>>> + struct rk3368_ddrphy *phy;
>>>> + struct rk3368_pmu_grf *pmugrf;
>>>> + struct rk3368_msch *msch;
>>>> +};
>>>> +
>>>> +struct rk3368_sdram_params {
>>>> +#if CONFIG_IS_ENABLED(OF_PLATDATA)
>>>> + struct dtd_rockchip_rk3368_dmc of_plat;
>>>> +#endif
>>>> + struct rk3288_sdram_pctl_timing pctl_timing;
>>>> + u32 trefi_mem_ddr3;
>>>> + struct rk3288_sdram_channel chan;
>>>> + struct regmap *map;
>>>> + u32 ddr_freq;
>>>> + u32 memory_schedule;
>>>> + u32 ddr_speed_bin;
>>>> + u32 tfaw_mult;
>>>> +};
>>>> +
>>>> +/* PTCL bits */
>>>> +enum {
>>>> + /* PCTL_DFISTCFG0 */
>>>> + DFI_INIT_START = BIT(0),
>>>> + DFI_DATA_BYTE_DISABLE_EN = BIT(2),
>>>> +
>>>> + /* PCTL_DFISTCFG1 */
>>>> + DFI_DRAM_CLK_SR_EN = BIT(0),
>>>> + DFI_DRAM_CLK_DPD_EN = BIT(1),
>>>> + ODT_LEN_BL8_W_SHIFT = 16,
>>>> +
>>>> + /* PCTL_DFISTCFG2 */
>>>> + DFI_PARITY_INTR_EN = BIT(0),
>>>> + DFI_PARITY_EN = BIT(1),
>>>> +
>>>> + /* PCTL_DFILPCFG0 */
>>>> + TLP_RESP_TIME_SHIFT = 16,
>>>> + LP_SR_EN = BIT(8),
>>>> + LP_PD_EN = BIT(0),
>>>> +
>>>> + /* PCTL_DFIODTCFG */
>>>> + RANK0_ODT_WRITE_SEL = BIT(3),
>>>> + RANK1_ODT_WRITE_SEL = BIT(11),
>>>> +
>>>> + /* PCTL_SCFG */
>>>> + HW_LOW_POWER_EN = BIT(0),
>>>> +
>>>> + /* PCTL_MCMD */
>>>> + START_CMD = BIT(31),
>>>> + MCMD_RANK0 = BIT(20),
>>>> + MCMD_RANK1 = BIT(21),
>>>> + DESELECT_CMD = 0,
>>>> + PREA_CMD,
>>>> + REF_CMD,
>>>> + MRS_CMD,
>>>> + ZQCS_CMD,
>>>> + ZQCL_CMD,
>>>> + RSTL_CMD,
>>>> + MRR_CMD = 8,
>>>> + DPDE_CMD,
>>>> +
>>>> + /* PCTL_POWCTL */
>>>> + POWER_UP_START = BIT(0),
>>>> +
>>>> + /* PCTL_POWSTAT */
>>>> + POWER_UP_DONE = BIT(0),
>>>> +
>>>> + /* PCTL_SCTL */
>>>> + INIT_STATE = 0,
>>>> + CFG_STATE,
>>>> + GO_STATE,
>>>> + SLEEP_STATE,
>>>> + WAKEUP_STATE,
>>>> +
>>>> + /* PCTL_STAT */
>>>> + LP_TRIG_SHIFT = 4,
>>>> + LP_TRIG_MASK = 7,
>>>> + PCTL_STAT_MSK = 7,
>>>> + INIT_MEM = 0,
>>>> + CONFIG,
>>>> + CONFIG_REQ,
>>>> + ACCESS,
>>>> + ACCESS_REQ,
>>>> + LOW_POWER,
>>>> + LOW_POWER_ENTRY_REQ,
>>>> + LOW_POWER_EXIT_REQ,
>>>> +
>>>> + /* PCTL_MCFG */
>>>> + DDR2_DDR3_BL_8 = BIT(0),
>>>> + DDR3_EN = BIT(5),
>>>> + TFAW_TRRD_MULT4 = (0 << 18),
>>>> + TFAW_TRRD_MULT5 = (1 << 18),
>>>> + TFAW_TRRD_MULT6 = (2 << 18),
>>>> +};
>>>> +
>>>> +#define DDR3_MR0_WR(n) \
>>>> + ((n <= 8) ? ((n - 4) << 9) : (((n >> 1) & 0x7) << 9))
>>>> +#define DDR3_MR0_CL(n) \
>>>> + ((((n - 4) & 0x7) << 4) | (((n - 4) & 0x8) >> 2))
>>>> +#define DDR3_MR0_BL8 \
>>>> + (0 << 0)
>>>> +#define DDR3_MR0_DLL_RESET \
>>>> + (1 << 8)
>>>> +#define DDR3_MR1_RTT120OHM \
>>>> + ((0 << 9) | (1 << 6) | (0 << 2))
>>>> +#define DDR3_MR2_TWL(n) \
>>>> + (((n - 5) & 0x7) << 3)
>>>> +
>>>> +
>>>> +#ifdef CONFIG_TPL_BUILD
>>>> +
>>>> +static void ddr_set_noc_spr_err_stall(struct rk3368_grf *grf, bool enable)
>>>> +{
>>>> + if (enable)
>>>> + rk_setreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL);
>>>> + else
>>>> + rk_clrreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL);
>>>> +}
>>>> +
>>>> +static void ddr_set_ddr3_mode(struct rk3368_grf *grf, bool ddr3_mode)
>>>> +{
>>>> + if (ddr3_mode)
>>>> + rk_setreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3);
>>>> + else
>>>> + rk_clrreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3);
>>>> +}
>>>> +
>>>> +static void ddrphy_config(struct rk3368_ddrphy *phy,
>>>> + u32 tcl, u32 tal, u32 tcwl)
>>>> +{
>>>> + int i;
>>>> +
>>>> + /* Set to DDR3 mode */
>>>> + clrsetbits_le32(&phy->reg[1], 0x3, 0x0);
>>>> +
>>>> + /* DDRPHY_REGB: CL, AL */
>>>> + clrsetbits_le32(&phy->reg[0xb], 0xff, tcl << 4 | tal);
>>>> + /* DDRPHY_REGC: CWL */
>>>> + clrsetbits_le32(&phy->reg[0xc], 0x0f, tcwl);
>>>> +
>>>> + /* Update drive-strength */
>>>> + writel(0xcc, &phy->reg[0x11]);
>>>> + writel(0xaa, &phy->reg[0x16]);
>>>> + /*
>>>> + * Update NRCOMP/PRCOMP for all 4 channels (for details of all
>>>> + * affected registers refer to the documentation of DDRPHY_REG20
>>>> + * and DDRPHY_REG21 in the RK3368 TRM.
>>>> + */
>>>> + for (i = 0; i < 4; ++i) {
>>>> + writel(0xcc, &phy->reg[0x20 + i * 0x10]);
>>>> + writel(0x44, &phy->reg[0x21 + i * 0x10]);
>>>> + }
>>>> +
>>>> + /* Enable write-leveling calibration bypass */
>>>> + setbits_le32(&phy->reg[2], BIT(3));
>>>> +}
>>>> +
>>>> +static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
>>>> +{
>>>> + int i;
>>>> +
>>>> + for (i = 0; i < n / sizeof(u32); i++)
>>>> + writel(*src++, dest++);
>>>> +}
>>>> +
>>>> +static void send_command(struct rk3368_ddr_pctl *pctl, u32 rank, u32 cmd)
>>>> +{
>>>> + u32 mcmd = START_CMD | cmd | rank;
>>>> +
>>>> + debug("%s: writing %x to MCMD\n", __func__, mcmd);
>>>> + writel(mcmd, &pctl->mcmd);
>>>> + while (readl(&pctl->mcmd) & START_CMD)
>>>> + /* spin */;
>>>> +}
>>>> +
>>>> +static void send_mrs(struct rk3368_ddr_pctl *pctl,
>>>> + u32 rank, u32 mr_num, u32 mr_data)
>>>> +{
>>>> + u32 mcmd = START_CMD | MRS_CMD | rank | (mr_num << 17) | (mr_data << 4);
>>>> +
>>>> + debug("%s: writing %x to MCMD\n", __func__, mcmd);
>>>> + writel(mcmd, &pctl->mcmd);
>>>> + while (readl(&pctl->mcmd) & START_CMD)
>>>> + /* spin */;
>>>> +}
>>>> +
>>>> +static int memory_init(struct rk3368_ddr_pctl *pctl,
>>>> + struct rk3368_sdram_params *params)
>>>> +{
>>>> + u32 mr[4];
>>>> + const ulong timeout_ms = 500;
>>>> + ulong tmp;
>>>> +
>>>> + /*
>>>> + * Power up DRAM by DDR_PCTL_POWCTL[0] register of PCTL and
>>>> + * wait power up DRAM finish with DDR_PCTL_POWSTAT[0] register
>>>> + * of PCTL.
>>>> + */
>>>> + writel(POWER_UP_START, &pctl->powctl);
>>>> +
>>>> + tmp = get_timer(0);
>>>> + do {
>>>> + if (get_timer(tmp) > timeout_ms) {
>>>> + error("%s: POWER_UP_START did not complete in %ld ms\n",
>>>> + __func__, timeout_ms);
>>>> + return -ETIME;
>>>> + }
>>>> + } while (!(readl(&pctl->powstat) & POWER_UP_DONE));
>>>> +
>>>> + /* Configure MR0 through MR3 */
>>>> + mr[0] = DDR3_MR0_WR(params->pctl_timing.twr) |
>>>> + DDR3_MR0_CL(params->pctl_timing.tcl) |
>>>> + DDR3_MR0_DLL_RESET;
>>>> + mr[1] = DDR3_MR1_RTT120OHM;
>>>> + mr[2] = DDR3_MR2_TWL(params->pctl_timing.tcwl);
>>>> + mr[3] = 0;
>>>> +
>>>> + /*
>>>> + * Also see RK3368 Technical Reference Manual:
>>>> + * "16.6.2 Initialization (DDR3 Initialization Sequence)"
>>>> + */
>>>> + send_command(pctl, MCMD_RANK0 | MCMD_RANK1, DESELECT_CMD);
>>>> + udelay(1);
>>>> + send_command(pctl, MCMD_RANK0 | MCMD_RANK1, PREA_CMD);
>>>> + send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 2, mr[2]);
>>>> + send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 3, mr[3]);
>>>> + send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 1, mr[1]);
>>>> + send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 0, mr[0]);
>>>> + send_command(pctl, MCMD_RANK0 | MCMD_RANK1, ZQCL_CMD);
>>>> +
>>>> + return 0;
>>>> +}
>>>> +
>>>> +static void move_to_config_state(struct rk3368_ddr_pctl *pctl)
>>>> +{
>>>> + /*
>>>> + * Also see RK3368 Technical Reference Manual:
>>>> + * "16.6.1 State transition of PCTL (Moving to Config State)"
>>>> + */
>>>> + u32 state = readl(&pctl->stat) & PCTL_STAT_MSK;
>>>> +
>>>> + switch (state) {
>>>> + case LOW_POWER:
>>>> + writel(WAKEUP_STATE, &pctl->sctl);
>>>> + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
>>>> + /* spin */;
>>>> +
>>>> + /* fall-through */
>>>> + case ACCESS:
>>>> + case INIT_MEM:
>>>> + writel(CFG_STATE, &pctl->sctl);
>>>> + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
>>>> + /* spin */;
>>>> + break;
>>>> +
>>>> + case CONFIG:
>>>> + return;
>>>> +
>>>> + default:
>>>> + break;
>>>> + }
>>>> +}
>>>> +
>>>> +static void move_to_access_state(struct rk3368_ddr_pctl *pctl)
>>>> +{
>>>> + /*
>>>> + * Also see RK3368 Technical Reference Manual:
>>>> + * "16.6.1 State transition of PCTL (Moving to Access State)"
>>>> + */
>>>> + u32 state = readl(&pctl->stat) & PCTL_STAT_MSK;
>>>> +
>>>> + switch (state) {
>>>> + case LOW_POWER:
>>>> + if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) &
>>>> + LP_TRIG_MASK) == 1)
>>>> + return;
>>>> +
>>>> + writel(WAKEUP_STATE, &pctl->sctl);
>>>> + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
>>>> + /* spin */;
>>>> +
>>>> + /* fall-through */
>>>> + case INIT_MEM:
>>>> + writel(CFG_STATE, &pctl->sctl);
>>>> + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
>>>> + /* spin */;
>>>> +
>>>> + /* fall-through */
>>>> + case CONFIG:
>>>> + writel(GO_STATE, &pctl->sctl);
>>>> + while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG)
>>>> + /* spin */;
>>>> + break;
>>>> +
>>>> + case ACCESS:
>>>> + return;
>>>> +
>>>> + default:
>>>> + break;
>>>> + }
>>>> +}
>>>> +
>>>> +static void ddrctl_reset(struct rk3368_cru *cru)
>>>> +{
>>>> + const u32 ctl_reset = BIT(3) | BIT(2);
>>>> + const u32 phy_reset = BIT(1) | BIT(0);
>>>> +
>>>> + rk_setreg(&cru->softrst_con[10], ctl_reset | phy_reset);
>>>> + udelay(1);
>>>> + rk_clrreg(&cru->softrst_con[10], ctl_reset | phy_reset);
>>>> +}
>>>> +
>>>> +static void ddrphy_reset(struct rk3368_ddrphy *ddrphy)
>>>> +{
>>>> + clrbits_le32(&ddrphy->reg[0], BIT(3) | BIT(2));
>>>> + udelay(1);
>>>> + setbits_le32(&ddrphy->reg[0], BIT(3) | BIT(2));
>>>> +}
>>>> +
>>>> +static void ddrphy_config_delays(struct rk3368_ddrphy *ddrphy, u32 freq)
>>>> +{
>>>> + u32 dqs_dll_delay;
>>>> +
>>>> + setbits_le32(&ddrphy->reg[0x13], BIT(4));
>>>> + clrbits_le32(&ddrphy->reg[0x14], BIT(3));
>>>> +
>>>> + setbits_le32(&ddrphy->reg[0x26], BIT(4));
>>>> + clrbits_le32(&ddrphy->reg[0x27], BIT(3));
>>>> +
>>>> + setbits_le32(&ddrphy->reg[0x36], BIT(4));
>>>> + clrbits_le32(&ddrphy->reg[0x37], BIT(3));
>>>> +
>>>> + setbits_le32(&ddrphy->reg[0x46], BIT(4));
>>>> + clrbits_le32(&ddrphy->reg[0x47], BIT(3));
>>>> +
>>>> + setbits_le32(&ddrphy->reg[0x56], BIT(4));
>>>> + clrbits_le32(&ddrphy->reg[0x57], BIT(3));
>>>> +
>>>> + if (freq <= 400000000)
>>>> + setbits_le32(&ddrphy->reg[0xa4], 0x1f);
>>>> + else
>>>> + clrbits_le32(&ddrphy->reg[0xa4], 0x1f);
>>>> +
>>>> + if (freq < 681000000)
>>>> + dqs_dll_delay = 3; /* 67.5 degree delay */
>>>> + else
>>>> + dqs_dll_delay = 2; /* 45 degree delay */
>>>> +
>>>> + writel(dqs_dll_delay, &ddrphy->reg[0x28]);
>>>> + writel(dqs_dll_delay, &ddrphy->reg[0x38]);
>>>> + writel(dqs_dll_delay, &ddrphy->reg[0x48]);
>>>> + writel(dqs_dll_delay, &ddrphy->reg[0x58]);
>>>> +}
>>>> +
>>>> +static int dfi_cfg(struct rk3368_ddr_pctl *pctl)
>>>> +{
>>>> + const ulong timeout_ms = 200;
>>>> + ulong tmp;
>>>> +
>>>> + writel(DFI_DATA_BYTE_DISABLE_EN, &pctl->dfistcfg0);
>>>> +
>>>> + writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN,
>>>> + &pctl->dfistcfg1);
>>>> + writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2);
>>>> + writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN,
>>>> + &pctl->dfilpcfg0);
>>>> +
>>>> + writel(1, &pctl->dfitphyupdtype0);
>>>> +
>>>> + writel(0x1f, &pctl->dfitphyrdlat);
>>>> + writel(0, &pctl->dfitphywrdata);
>>>> + writel(0, &pctl->dfiupdcfg); /* phyupd and ctrlupd disabled */
>>>> +
>>>> + setbits_le32(&pctl->dfistcfg0, DFI_INIT_START);
>>>> +
>>>> + tmp = get_timer(0);
>>>> + do {
>>>> + if (get_timer(tmp) > timeout_ms) {
>>>> + error("%s: DFI init did not complete within %ld ms\n",
>>>> + __func__, timeout_ms);
>>>> + return -ETIME;
>>>> + }
>>>> + } while ((readl(&pctl->dfiststat0) & 1) == 0);
>>>> +
>>>> + return 0;
>>>> +}
>>>> +
>>>> +static inline u32 ps_to_tCK(const u32 ps, const ulong freq)
>>>> +{
>>>> + const ulong MHz = 1000000;
>>>> + return DIV_ROUND_UP(ps * freq, 1000000 * MHz);
>>>> +}
>>>> +
>>>> +static inline u32 ns_to_tCK(const u32 ns, const ulong freq)
>>>> +{
>>>> + return ps_to_tCK(ns * 1000, freq);
>>>> +}
>>>> +
>>>> +static inline u32 tCK_to_ps(const ulong tCK, const ulong freq)
>>>> +{
>>>> + const ulong MHz = 1000000;
>>>> + return DIV_ROUND_UP(tCK * 1000000 * MHz, freq);
>>>> +}
>>>> +
>>>> +static int pctl_calc_timings(struct rk3368_sdram_params *params,
>>>> + ulong freq)
>>>> +{
>>>> + struct rk3288_sdram_pctl_timing *pctl_timing = ¶ms->pctl_timing;
>>>> + const ulong MHz = 1000000;
>>>> + u32 tccd;
>>>> + u32 tfaw_as_ps;
>>>> +
>>>> + if (params->ddr_speed_bin != DDR3_1600K) {
>>>> + error("%s: unimplemented DDR3 speed bin %d\n",
>>>> + __func__, params->ddr_speed_bin);
>>>> + return -1;
>>>> + }
>>>> +
>>>> + /* PCTL is clocked at 1/2 the DRAM clock; err on the side of caution */
>>>> + pctl_timing->togcnt1u = DIV_ROUND_UP(freq, 2 * MHz);
>>>> + pctl_timing->togcnt100n = DIV_ROUND_UP(freq / 10, 2 * MHz);
>>>> +
>>>> + pctl_timing->tinit = 200; /* 200 usec */
>>>> + pctl_timing->trsth = 500; /* 500 usec */
>>>> + pctl_timing->trefi = 78; /* 7.8usec = 78 * 100ns */
>>>> + params->trefi_mem_ddr3 = ns_to_tCK(pctl_timing->trefi * 100, freq);
>>>> +
>>>> + if (freq <= (400 * MHz)) {
>>>> + pctl_timing->tcl = 6;
>>>> + pctl_timing->tcwl = 10;
>>>> + } else if (freq <= (533 * MHz)) {
>>>> + pctl_timing->tcl = 8;
>>>> + pctl_timing->tcwl = 6;
>>>> + } else if (freq <= (666 * MHz)) {
>>>> + pctl_timing->tcl = 10;
>>>> + pctl_timing->tcwl = 7;
>>>> + } else {
>>>> + pctl_timing->tcl = 11;
>>>> + pctl_timing->tcwl = 8;
>>>> + }
>>>> +
>>>> + pctl_timing->tmrd = 4; /* 4 tCK (all speed bins) */
>>>> + pctl_timing->trfc = ns_to_tCK(350, freq); /* tRFC: 350 (max) @ 8GBit */
>>>> + pctl_timing->trp = max(4u, ps_to_tCK(13750, freq));
>>>> + /*
>>>> + * JESD-79:
>>>> + * READ to WRITE Command Delay = RL + tCCD / 2 + 2tCK - WL
>>>> + */
>>>> + tccd = 4;
>>>> + pctl_timing->trtw = pctl_timing->tcl + tccd/2 + 2 - pctl_timing->tcwl;
>>>> + pctl_timing->tal = 0;
>>>> + pctl_timing->tras = ps_to_tCK(35000, freq);
>>>> + pctl_timing->trc = ps_to_tCK(48750, freq);
>>>> + pctl_timing->trcd = ps_to_tCK(13750, freq);
>>>> + pctl_timing->trrd = max(4u, ps_to_tCK(7500, freq));
>>>> + pctl_timing->trtp = max(4u, ps_to_tCK(7500, freq));
>>>> + pctl_timing->twr = ps_to_tCK(15000, freq);
>>>> + /* The DDR3 mode-register does only support even values for tWR > 8. */
>>>> + if (pctl_timing->twr > 8)
>>>> + pctl_timing->twr = (pctl_timing->twr + 1) & ~1;
>>>> + pctl_timing->twtr = max(4u, ps_to_tCK(7500, freq));
>>>> + pctl_timing->texsr = 512; /* tEXSR(max) is tDLLLK */
>>>> + pctl_timing->txp = max(3u, ps_to_tCK(6000, freq));
>>>> + pctl_timing->txpdll = max(10u, ps_to_tCK(24000, freq));
>>>> + pctl_timing->tzqcs = max(64u, ps_to_tCK(80000, freq));
>>>> + pctl_timing->tzqcsi = 10000; /* as used by Rockchip */
>>>> + pctl_timing->tdqs = 1; /* fixed for DDR3 */
>>>> + pctl_timing->tcksre = max(5u, ps_to_tCK(10000, freq));
>>>> + pctl_timing->tcksrx = max(5u, ps_to_tCK(10000, freq));
>>>> + pctl_timing->tcke = max(3u, ps_to_tCK(5000, freq));
>>>> + pctl_timing->tmod = max(12u, ps_to_tCK(15000, freq));
>>>> + pctl_timing->trstl = ns_to_tCK(100, freq);
>>>> + pctl_timing->tzqcl = max(256u, ps_to_tCK(320000, freq)); /* tZQoper */
>>>> + pctl_timing->tmrr = 0;
>>>> + pctl_timing->tckesr = pctl_timing->tcke + 1; /* JESD-79: tCKE + 1tCK */
>>>> + pctl_timing->tdpd = 0; /* RK3368 TRM: "allowed values for DDR3: 0" */
>>>> +
>>>> +
>>>> + /*
>>>> + * The controller can represent tFAW as 4x, 5x or 6x tRRD only.
>>>> + * We want to use the smallest multiplier that satisfies the tFAW
>>>> + * requirements of the given speed-bin. If necessary, we stretch out
>>>> + * tRRD to allow us to operate on a 6x multiplier for tFAW.
>>>> + */
>>>> + tfaw_as_ps = 40000; /* 40ns: tFAW for DDR3-1600K, 2KB page-size */
>>>> + if (tCK_to_ps(pctl_timing->trrd * 6, freq) < tfaw_as_ps) {
>>>> + /* If tFAW is > 6 x tRRD, we need to stretch tRRD */
>>>> + pctl_timing->trrd = ps_to_tCK(DIV_ROUND_UP(40000, 6), freq);
>>>> + params->tfaw_mult = TFAW_TRRD_MULT6;
>>>> + } else if (tCK_to_ps(pctl_timing->trrd * 5, freq) < tfaw_as_ps) {
>>>> + params->tfaw_mult = TFAW_TRRD_MULT6;
>>>> + } else if (tCK_to_ps(pctl_timing->trrd * 4, freq) < tfaw_as_ps) {
>>>> + params->tfaw_mult = TFAW_TRRD_MULT5;
>>>> + } else {
>>>> + params->tfaw_mult = TFAW_TRRD_MULT4;
>>>> + }
>>>> +
>>>> + return 0;
>>>> +}
>>>> +
>>>> +static void pctl_cfg(struct rk3368_ddr_pctl *pctl,
>>>> + struct rk3368_sdram_params *params,
>>>> + struct rk3368_grf *grf)
>>>> +{
>>>> + /* Configure PCTL timing registers */
>>>> + params->pctl_timing.trefi |= BIT(31); /* see PCTL_TREFI */
>>>> + copy_to_reg(&pctl->togcnt1u, ¶ms->pctl_timing.togcnt1u,
>>>> + sizeof(params->pctl_timing));
>>>> + writel(params->trefi_mem_ddr3, &pctl->trefi_mem_ddr3);
>>>> +
>>>> + /* Set up ODT write selector and ODT write length */
>>>> + writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL), &pctl->dfiodtcfg);
>>>> + writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1);
>>>> +
>>>> + /* Set up the CL/CWL-dependent timings of DFI */
>>>> + writel((params->pctl_timing.tcl - 1) / 2 - 1, &pctl->dfitrddataen);
>>>> + writel((params->pctl_timing.tcwl - 1) / 2 - 1, &pctl->dfitphywrlat);
>>>> +
>>>> + /* DDR3 */
>>>> + writel(params->tfaw_mult | DDR3_EN | DDR2_DDR3_BL_8, &pctl->mcfg);
>>>> + writel(0x001c0004, &grf->ddrc0_con0);
>>>> +
>>>> + setbits_le32(&pctl->scfg, HW_LOW_POWER_EN);
>>>> +}
>>>> +
>>>> +static int ddrphy_data_training(struct rk3368_ddr_pctl *pctl,
>>>> + struct rk3368_ddrphy *ddrphy)
>>>> +{
>>>> + const u32 trefi = readl(&pctl->trefi);
>>>> + const ulong timeout_ms = 500;
>>>> + ulong tmp;
>>>> +
>>>> + /* disable auto-refresh */
>>>> + writel(0 | BIT(31), &pctl->trefi);
>>>> +
>>>> + clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x20);
>>>> + clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x21);
>>>> +
>>>> + tmp = get_timer(0);
>>>> + do {
>>>> + if (get_timer(tmp) > timeout_ms) {
>>>> + error("%s: did not complete within %ld ms\n",
>>>> + __func__, timeout_ms);
>>>> + return -ETIME;
>>>> + }
>>>> + } while ((readl(&ddrphy->reg[0xff]) & 0xf) != 0xf);
>>>> +
>>>> + send_command(pctl, MCMD_RANK0 | MCMD_RANK1, PREA_CMD);
>>>> + clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x20);
>>>> + /* resume auto-refresh */
>>>> + writel(trefi | BIT(31), &pctl->trefi);
>>>> +
>>>> + return 0;
>>>> +}
>>>> +
>>>> +static int sdram_col_row_detect(struct udevice *dev)
>>>> +{
>>>> + struct dram_info *priv = dev_get_priv(dev);
>>>> + struct rk3368_sdram_params *params = dev_get_platdata(dev);
>>>> + struct rk3368_ddr_pctl *pctl = priv->pctl;
>>>> + struct rk3368_msch *msch = priv->msch;
>>>> + const u32 test_pattern = 0x5aa5f00f;
>>>> + int row, col;
>>>> + uintptr_t addr;
>>>> +
>>>> + move_to_config_state(pctl);
>>>> + writel(6, &msch->ddrconf);
>>>> + move_to_access_state(pctl);
>>>> +
>>>> + /* Detect col */
>>>> + for (col = 11; col >= 9; col--) {
>>>> + writel(0, CONFIG_SYS_SDRAM_BASE);
>>>> + addr = CONFIG_SYS_SDRAM_BASE +
>>>> + (1 << (col + params->chan.bw - 1));
>>>> + writel(test_pattern, addr);
>>>> + if ((readl(addr) == test_pattern) &&
>>>> + (readl(CONFIG_SYS_SDRAM_BASE) == 0))
>>>> + break;
>>>> + }
>>>> +
>>>> + if (col == 8) {
>>>> + error("%s: col detect error\n", __func__);
>>>> + return -EINVAL;
>>>> + }
>>>> +
>>>> + move_to_config_state(pctl);
>>>> + writel(15, &msch->ddrconf);
>>>> + move_to_access_state(pctl);
>>>> +
>>>> + /* Detect row*/
>>>> + for (row = 16; row >= 12; row--) {
>>>> + writel(0, CONFIG_SYS_SDRAM_BASE);
>>>> + addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
>>>> + writel(test_pattern, addr);
>>>> + if ((readl(addr) == test_pattern) &&
>>>> + (readl(CONFIG_SYS_SDRAM_BASE) == 0))
>>>> + break;
>>>> + }
>>>> +
>>>> + if (row == 11) {
>>>> + error("%s: row detect error\n", __func__);
>>>> + return -EINVAL;
>>>> + }
>>>> +
>>>> + /* Record results */
>>>> + debug("%s: col %d, row %d\n", __func__, col, row);
>>>> + params->chan.col = col;
>>>> + params->chan.cs0_row = row;
>>>> + params->chan.cs1_row = row;
>>>> + params->chan.row_3_4 = 0;
>>>> +
>>>> + return 0;
>>>> +}
>>>> +
>>>> +static int msch_niu_config(struct rk3368_msch *msch,
>>>> + struct rk3368_sdram_params *params)
>>>> +{
>>>> + int i;
>>>> + const u8 cols = params->chan.col - ((params->chan.bw == 2) ? 0 : 1);
>>>> + const u8 rows = params->chan.cs0_row;
>>>> +
>>>> + /*
>>>> + * The DDR address-translation table always assumes a 32bit
>>>> + * bus and the comparison below takes care of adjusting for
>>>> + * a 16bit bus (i.e. one column-address is consumed).
>>>> + */
>>>> + const struct {
>>>> + u8 rows;
>>>> + u8 columns;
>>>> + u8 type;
>>>> + } ddrconf_table[] = {
>>>> + /*
>>>> + * C-B-R-D patterns are first. For these we require an
>>>> + * exact match for the columns and rows (as there's
>>>> + * one entry per possible configuration).
>>>> + */
>>>> + [0] = { .rows = 13, .columns = 10, .type = DMC_MSCH_CBRD },
>>>> + [1] = { .rows = 14, .columns = 10, .type = DMC_MSCH_CBRD },
>>>> + [2] = { .rows = 15, .columns = 10, .type = DMC_MSCH_CBRD },
>>>> + [3] = { .rows = 16, .columns = 10, .type = DMC_MSCH_CBRD },
>>>> + [4] = { .rows = 14, .columns = 11, .type = DMC_MSCH_CBRD },
>>>> + [5] = { .rows = 15, .columns = 11, .type = DMC_MSCH_CBRD },
>>>> + [6] = { .rows = 16, .columns = 11, .type = DMC_MSCH_CBRD },
>>>> + [7] = { .rows = 13, .columns = 9, .type = DMC_MSCH_CBRD },
>>>> + [8] = { .rows = 14, .columns = 9, .type = DMC_MSCH_CBRD },
>>>> + [9] = { .rows = 15, .columns = 9, .type = DMC_MSCH_CBRD },
>>>> + [10] = { .rows = 16, .columns = 9, .type = DMC_MSCH_CBRD },
>>>> + /*
>>>> + * 11 through 13 are C-R-B-D patterns. These are
>>>> + * matched for an exact number of columns and to
>>>> + * ensure that the hardware uses at least as many rows
>>>> + * as the pattern requires (i.e. we make sure that
>>>> + * there's no gaps up until we hit the device/chip-select;
>>>> + * however, these patterns can accept up to 16 rows,
>>>> + * as the row-address continues right after the CS
>>>> + * switching)
>>>> + */
>>>> + [11] = { .rows = 15, .columns = 10, .type = DMC_MSCH_CRBD },
>>>> + [12] = { .rows = 14, .columns = 11, .type = DMC_MSCH_CRBD },
>>>> + [13] = { .rows = 13, .columns = 10, .type = DMC_MSCH_CRBD },
>>>> + /*
>>>> + * 14 and 15 are catch-all variants using a C-B-D-R
>>>> + * scheme (i.e. alternating the chip-select every time
>>>> + * C-B overflows) and stuffing the remaining C-bits
>>>> + * into the top. Matching needs to make sure that the
>>>> + * number of columns is either an exact match (i.e. we
>>>> + * can use less the the maximum number of rows) -or-
>>>> + * that the columns exceed what is given in this table
>>>> + * and the rows are an exact match (in which case the
>>>> + * remaining C-bits will be stuffed onto the top after
>>>> + * the device/chip-select switches).
>>>> + */
>>>> + [14] = { .rows = 16, .columns = 10, .type = DMC_MSCH_CBDR },
>>>> + [15] = { .rows = 16, .columns = 9, .type = DMC_MSCH_CBDR },
>>>> + };
>>>> +
>>>> + /*
>>>> + * For C-B-R-D, we need an exact match (i.e. both for the number of
>>>> + * columns and rows), while for C-B-D-R, only the the number of
>>>> + * columns needs to match.
>>>> + */
>>>> + for (i = 0; i < ARRAY_SIZE(ddrconf_table); i++) {
>>>> + bool match = false;
>>>> +
>>>> + /* If this entry if for a different matcher, then skip it */
>>>> + if (ddrconf_table[i].type != params->memory_schedule)
>>>> + continue;
>>>> +
>>>> + /*
>>>> + * Match according to the rules (exact/inexact/at-least)
>>>> + * documented in the ddrconf_table above.
>>>> + */
>>>> + switch (params->memory_schedule) {
>>>> + case DMC_MSCH_CBRD:
>>>> + match = (ddrconf_table[i].columns == cols) &&
>>>> + (ddrconf_table[i].rows == rows);
>>>> + break;
>>>> +
>>>> + case DMC_MSCH_CRBD:
>>>> + match = (ddrconf_table[i].columns == cols) &&
>>>> + (ddrconf_table[i].rows <= rows);
>>>> + break;
>>>> +
>>>> + case DMC_MSCH_CBDR:
>>>> + match = (ddrconf_table[i].columns == cols) ||
>>>> + ((ddrconf_table[i].columns <= cols) &&
>>>> + (ddrconf_table[i].rows == rows));
>>>> + break;
>>>> +
>>>> + default:
>>>> + break;
>>>> + }
>>>> +
>>>> + if (match) {
>>>> + debug("%s: setting ddrconf 0x%x\n", __func__, i);
>>>> + writel(i, &msch->ddrconf);
>>>> + return 0;
>>>> + }
>>>> + }
>>>> +
>>>> + error("%s: ddrconf (NIU config) not found\n", __func__);
>>>> + return -EINVAL;
>>>> +}
>>>> +
>>>> +static void dram_all_config(struct udevice *dev)
>>>> +{
>>>> + struct dram_info *priv = dev_get_priv(dev);
>>>> + struct rk3368_pmu_grf *pmugrf = priv->pmugrf;
>>>> + struct rk3368_sdram_params *params = dev_get_platdata(dev);
>>>> + const struct rk3288_sdram_channel *info = ¶ms->chan;
>>>> + u32 sys_reg = 0;
>>>> + const int chan = 0;
>>>> +
>>>> + sys_reg |= DDR3 << SYS_REG_DDRTYPE_SHIFT;
>>>> + sys_reg |= 0 << SYS_REG_NUM_CH_SHIFT;
>>>> +
>>>> + sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan);
>>>> + sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan);
>>>> + sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan);
>>>> + sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan);
>>>> + sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan);
>>>> + sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan);
>>>> + sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan);
>>>> + sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan);
>>>> + sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan);
>>>> +
>>>> + writel(sys_reg, &pmugrf->os_reg[2]);
>>>> +}
>>>> +
>>>> +static int setup_sdram(struct udevice *dev)
>>>> +{
>>>> + struct dram_info *priv = dev_get_priv(dev);
>>>> + struct rk3368_sdram_params *params = dev_get_platdata(dev);
>>>> +
>>>> + struct rk3368_ddr_pctl *pctl = priv->pctl;
>>>> + struct rk3368_ddrphy *ddrphy = priv->phy;
>>>> + struct rk3368_cru *cru = priv->cru;
>>>> + struct rk3368_grf *grf = priv->grf;
>>>> + struct rk3368_msch *msch = priv->msch;
>>>> +
>>>> + int ret;
>>>> +
>>>> + /* The input clock (i.e. DPLL) needs to be 2x the DRAM frequency */
>>>> + ret = clk_set_rate(&priv->ddr_clk, 2 * params->ddr_freq);
>>>> + if (ret < 0) {
>>>> + debug("%s: could not set DDR clock: %d\n", __func__, ret);
>>>> + return ret;
>>>> + }
>>>> +
>>>> + /* Update the read-latency for the RK3368 */
>>>> + writel(0x32, &msch->readlatency);
>>>> +
>>>> + /* Initialise the DDR PCTL and DDR PHY */
>>>> + ddrctl_reset(cru);
>>>> + ddrphy_reset(ddrphy);
>>>> + ddrphy_config_delays(ddrphy, params->ddr_freq);
>>>> + dfi_cfg(pctl);
>>>> + /* Configure relative system information of grf_ddrc0_con0 register */
>>>> + ddr_set_ddr3_mode(grf, true);
>>>> + ddr_set_noc_spr_err_stall(grf, true);
>>>> + /* Calculate timings */
>>>> + pctl_calc_timings(params, params->ddr_freq);
>>>> + /* Initialise the device timings in protocol controller */
>>>> + pctl_cfg(pctl, params, grf);
>>>> + /* Configure AL, CL ... information of PHY registers */
>>>> + ddrphy_config(ddrphy,
>>>> + params->pctl_timing.tcl,
>>>> + params->pctl_timing.tal,
>>>> + params->pctl_timing.tcwl);
>>>> +
>>>> + /* Initialize DRAM and configure with mode-register values */
>>>> + ret = memory_init(pctl, params);
>>>> + if (ret)
>>>> + goto error;
>>>> +
>>>> + move_to_config_state(pctl);
>>>> + /* Perform data-training */
>>>> + ddrphy_data_training(pctl, ddrphy);
>>>> + move_to_access_state(pctl);
>>>> +
>>>> + /* TODO(prt): could detect rank in training... */
>>>> + params->chan.rank = 2;
>>>> + /* TODO(prt): bus width is not auto-detected (yet)... */
>>>> + params->chan.bw = 2; /* 32bit wide bus */
>>>> + params->chan.dbw = params->chan.dbw; /* 32bit wide bus */
>>>> +
>>>> + /* DDR3 is always 8 bank */
>>>> + params->chan.bk = 3;
>>>> + /* Detect col and row number */
>>>> + ret = sdram_col_row_detect(dev);
>>>> + if (ret)
>>>> + goto error;
>>>> +
>>>> + /* Configure NIU DDR configuration */
>>>> + ret = msch_niu_config(msch, params);
>>>> + if (ret)
>>>> + goto error;
>>>> +
>>>> + /* set up OS_REG to communicate w/ next stage and OS */
>>>> + dram_all_config(dev);
>>>> +
>>>> + return 0;
>>>> +
>>>> +error:
>>>> + printf("DRAM init failed!\n");
>>>> + hang();
>>>> +}
>>>> +#endif
>>>> +
>>>> +static int rk3368_dmc_ofdata_to_platdata(struct udevice *dev)
>>>> +{
>>>> + int ret = 0;
>>>> +
>>>> +#if !CONFIG_IS_ENABLED(OF_PLATDATA)
>>>> + struct rk3368_sdram_params *plat = dev_get_platdata(dev);
>>>> +
>>>> + ret = regmap_init_mem(dev, &plat->map);
>>>> + if (ret)
>>>> + return ret;
>>>> +#endif
>>>> +
>>>> + return ret;
>>>> +}
>>>> +
>>>> +#if CONFIG_IS_ENABLED(OF_PLATDATA)
>>>> +static int conv_of_platdata(struct udevice *dev)
>>>> +{
>>>> + struct rk3368_sdram_params *plat = dev_get_platdata(dev);
>>>> + struct dtd_rockchip_rk3368_dmc *of_plat = &plat->of_plat;
>>>> + int ret;
>>>> +
>>>> + plat->ddr_freq = of_plat->rockchip_ddr_frequency;
>>>> + plat->ddr_speed_bin = of_plat->rockchip_ddr_speed_bin;
>>>> + plat->memory_schedule = of_plat->rockchip_memory_schedule;
>>>> +
>>>> + ret = regmap_init_mem_platdata(dev, of_plat->reg,
>>>> + ARRAY_SIZE(of_plat->reg) / 2,
>>>> + &plat->map);
>>>> + if (ret)
>>>> + return ret;
>>>> +
>>>> + return 0;
>>>> +}
>>>> +#endif
>>>> +
>>>> +static int rk3368_dmc_probe(struct udevice *dev)
>>>> +{
>>>> +#ifdef CONFIG_TPL_BUILD
>>>> + struct rk3368_sdram_params *plat = dev_get_platdata(dev);
>>>> + struct rk3368_ddr_pctl *pctl;
>>>> + struct rk3368_ddrphy *ddrphy;
>>>> + struct rk3368_cru *cru;
>>>> + struct rk3368_grf *grf;
>>>> + struct rk3368_msch *msch;
>>>> + int ret;
>>>> + struct udevice *dev_clk;
>>>> +#endif
>>>> + struct dram_info *priv = dev_get_priv(dev);
>>>> +
>>>> +#if CONFIG_IS_ENABLED(OF_PLATDATA)
>>>> + ret = conv_of_platdata(dev);
>>>> + if (ret)
>>>> + return ret;
>>>> +#endif
>>>> +
>>>> + priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
>>>> + debug("%s: pmugrf=%p\n", __func__, priv->pmugrf);
>>>> +
>>>> +#ifdef CONFIG_TPL_BUILD
>>>> + pctl = regmap_get_range(plat->map, 0);
>>>> + ddrphy = regmap_get_range(plat->map, 1);
>>>> + msch = syscon_get_first_range(ROCKCHIP_SYSCON_MSCH);
>>>> + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
>>>> +
>>>> + priv->pctl = pctl;
>>>> + priv->phy = ddrphy;
>>>> + priv->msch = msch;
>>>> + priv->grf = grf;
>>>> +
>>>> + ret = rockchip_get_clk(&dev_clk);
>>>> + if (ret)
>>>> + return ret;
>>>> + priv->ddr_clk.id = CLK_DDR;
>>>> + ret = clk_request(dev_clk, &priv->ddr_clk);
>>>> + if (ret)
>>>> + return ret;
>>>> +
>>>> + cru = rockchip_get_cru();
>>>> + priv->cru = cru;
>>>> + if (IS_ERR(priv->cru))
>>>> + return PTR_ERR(priv->cru);
>>>> +
>>>> + ret = setup_sdram(dev);
>>>> + if (ret)
>>>> + return ret;
>>>> +#endif
>>>> +
>>>> + priv->info.base = 0;
>>>> + priv->info.size =
>>>> + rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg[2]);
>>>> +
>>>> + /*
>>>> + * we use the 0x00000000~0xfdffffff space since 0xff000000~0xffffffff
>>>> + * is SoC register space (i.e. reserved), and 0xfe000000~0xfeffffff is
>>>> + * inaccessible for some IP controller.
>>>> + */
>>>> + priv->info.size = min(priv->info.size, (size_t)0xfe000000);
>>>> +
>>>> + return 0;
>>>> +}
>>>> +
>>>> +static int rk3368_dmc_get_info(struct udevice *dev, struct ram_info *info)
>>>> +{
>>>> + struct dram_info *priv = dev_get_priv(dev);
>>>> +
>>>> + *info = priv->info;
>>>> + return 0;
>>>> +}
>>>> +
>>>> +static struct ram_ops rk3368_dmc_ops = {
>>>> + .get_info = rk3368_dmc_get_info,
>>>> +};
>>>> +
>>>> +
>>>> +static const struct udevice_id rk3368_dmc_ids[] = {
>>>> + { .compatible = "rockchip,rk3368-dmc" },
>>>> + { }
>>>> +};
>>>> +
>>>> +U_BOOT_DRIVER(dmc_rk3368) = {
>>>> + .name = "rockchip_rk3368_dmc",
>>>> + .id = UCLASS_RAM,
>>>> + .of_match = rk3368_dmc_ids,
>>>> + .ops = &rk3368_dmc_ops,
>>>> + .probe = rk3368_dmc_probe,
>>>> + .priv_auto_alloc_size = sizeof(struct dram_info),
>>>> + .ofdata_to_platdata = rk3368_dmc_ofdata_to_platdata,
>>>> + .probe = rk3368_dmc_probe,
>>>> + .priv_auto_alloc_size = sizeof(struct dram_info),
>>>> + .platdata_auto_alloc_size = sizeof(struct rk3368_sdram_params),
>>>> +};
>>>> diff --git a/include/dt-bindings/memory/rk3368-dmc.h b/include/dt-bindings/memory/rk3368-dmc.h
>>>> new file mode 100644
>>>> index 0000000..b06ffde
>>>> --- /dev/null
>>>> +++ b/include/dt-bindings/memory/rk3368-dmc.h
>>>> @@ -0,0 +1,30 @@
>>>> +#ifndef DT_BINDINGS_RK3368_DMC_H
>>>> +#define DT_BINDINGS_RK3368_DMC_H
>>>> +
>>>> +#define DMC_MSCH_CBDR 0x0
>>>> +#define DMC_MSCH_CBRD 0x1
>>>> +#define DMC_MSCH_CRBD 0x2
>>>> +
>>>> +#define DDR3_800D 0
>>>> +#define DDR3_800E 1
>>>> +#define DDR3_1066E 2
>>>> +#define DDR3_1066F 3
>>>> +#define DDR3_1066G 4
>>>> +#define DDR3_1333F 5
>>>> +#define DDR3_1333G 6
>>>> +#define DDR3_1333H 7
>>>> +#define DDR3_1333J 8
>>>> +#define DDR3_1600G 9
>>>> +#define DDR3_1600H 10
>>>> +#define DDR3_1600J 11
>>>> +#define DDR3_1600K 12
>>>> +#define DDR3_1866J 13
>>>> +#define DDR3_1866K 14
>>>> +#define DDR3_1866L 15
>>>> +#define DDR3_1866M 16
>>>> +#define DDR3_2133K 17
>>>> +#define DDR3_2133L 18
>>>> +#define DDR3_2133M 19
>>>> +#define DDR3_2133N 20
>>>> +
>>>> +#endif
>>> dpd;
>>> + u32 trefi_mem_ddr3;
>>> + u32 reserved5[45];
>>> + u32 dtuwactl;
>>> + u32 dturactl;
>>> + u32 dtucfg;
>>> + u32 dtuectl;
>>> + u32 dtuwd0;
>>> + u32 dtuwd1;
>>> + u32 dtuwd2;
>>> + u32 dtuwd3;
>>> + u32 dtuwdm;
>>> + u32 dturd0;
>>> + u32 dturd1;
>>> + u32 dturd2;
>>> + u32 dturd3;
>>> + u32 dtulfsrwd;
>>> + u32 dtulfsrrd;
>>> + u32 dtueaf;
>>> + u32 dfitctrldelay;
>>> + u32 dfiodtcfg;
>>> + u32 dfiodtcfg1;
>>> + u32 dfiodtrankmap;
>>> + u32 dfitphywrdata;
>>> + u32 dfitphywrlat;
>>> + u32 reserved7[2];
>>> + u32 dfitrddataen;
>>> + u32 dfitphyrdlat;
>>> + u32 reserved8[2];
>>> + u32 dfitphyupdtype0;
>>> + u32 dfitphyupdtype1;
>>> + u32 dfitphyupdtype2;
>>> + u32 dfitphyupdtype3;
>>> + u32 dfitctrlupdmin;
>>> + u32 dfitctrlupdmax;
>>> + u32 dfitctrlupddly;
>>> + u32 reserved9;
>>> + u32 dfiupdcfg;
>>> + u32 dfitrefmski;
>>> + u32 dfitctrlupdi;
>>> + u32 reserved10[4];
>>> + u32 dfitrcfg0;
>>> + u32 dfitrstat0;
>>> + u32 dfitrwrlvlen;
>>> + u32 dfitrrdlvlen;
>>> + u32 dfitrrdlvlgateen;
>>> + u32 dfiststat0;
>>> + u32 dfistcfg0;
>>> + u32 dfistcfg1;
>>> + u32 reserved11;
>>> + u32 dfitdramclken;
>>> + u32 dfitdramclkdis;
>>> + u32 dfistcfg2;
>>> + u32 dfistparclr;
>>> + u32 dfistparlog;
>>> + u32 reserved12[3];
>>> + u32 dfilpcfg0;
>>> + u32 reserved13[3];
>>> + u32 dfitrwrlvlresp0;
>>> + u32 dfitrwrlvlresp1;
>>> + u32 dfitrwrlvlresp2;
>>> + u32 dfitrrdlvlresp0;
>>> + u32 dfitrrdlvlresp1;
>>> + u32 dfitrrdlvlresp2;
>>> + u32 dfitrwrlvldelay0;
>>> + u32 dfitrwrlvldelay1;
>>> + u32 dfitrwrlvldelay2;
>>> + u32 dfitrrdlvldelay0;
>>> + u32 dfitrrdlvldelay1;
>>> + u32 dfitrrdlvldelay2;
>>> + u32 dfitrrdlvlgatedelay0;
>>> + u32 dfitrrdlvlgatedelay1;
>>> + u32 dfitrrdlvlgatedelay2;
>>> + u32 dfitrcmd;
>>> + u32 reserved14[46];
>>> + u32 ipvr;
>>> + u32 iptr;
>>> +};
>>> +check_member(rk3368_ddr_pctl, iptr, 0x03fc);
>>> +
>>> +struct rk3368_ddrphy {
>>> + u32 reg[0x100];
>>> +};
>>> +check_member(rk3368_ddrphy, reg[0xff], 0x03fc);
>>> +
>>> +struct rk3368_msch {
>>> + u32 coreid;
>>> + u32 revisionid;
>>> + u32 ddrconf;
>>> + u32 ddrtiming;
>>> + u32 ddrmode;
>>> + u32 readlatency;
>>> + u32 reserved1[8];
>>> + u32 activate;
>>> + u32 devtodev;
>>> +};
>>> +check_member(rk3368_msch, devtodev, 0x003c);
>>> +
>>> +/* GRF_SOC_CON0 */
>>> +enum {
>>> + NOC_RSP_ERR_STALL = BIT(9),
>>> + MOBILE_DDR_SEL = BIT(4),
>>> + DDR0_16BIT_EN = BIT(3),
>>> + MSCH0_MAINDDR3_DDR3 = BIT(2),
>>> + MSCH0_MAINPARTIALPOP = BIT(1),
>>> + UPCTL_C_ACTIVE = BIT(0),
>>> +};
>>> +
>>> +#endif
>>> diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
>>> index 1f84ff9..6b6651a 100644
>>> --- a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
>>> +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
>>> @@ -76,8 +76,11 @@ struct rk3368_grf {
>>> u32 soc_con15;
>>> u32 soc_con16;
>>> u32 soc_con17;
>>> + u32 reserved5[0x6e];
>>> + u32 ddrc0_con0;
>>> };
>>> check_member(rk3368_grf, soc_con17, 0x444);
>>> +check_member(rk3368_grf, ddrc0_con0, 0x600);
>>> struct rk3368_pmu_grf {
>>> u32 gpio0a_iomux;
>>> diff --git a/arch/arm/mach-rockchip/rk3368/Makefile b/arch/arm/mach-rockchip/rk3368/Makefile
>>> index 0390716..46798c2 100644
>>> --- a/arch/arm/mach-rockchip/rk3368/Makefile
>>> +++ b/arch/arm/mach-rockchip/rk3368/Makefile
>>> @@ -5,5 +5,4 @@
>>> #
>>> obj-y += clk_rk3368.o
>>> obj-y += rk3368.o
>>> -obj-y += sdram_rk3368.o
>>> obj-y += syscon_rk3368.o
>>
>> The current PX5 EVB and Sheep board(they have no spl now) depend on this sdram_rk3368.c
>> to get the sdram capacity, and so is the geekbox board.
>> These boards will be broken when this driver removed.
>> We got the failed log like this on PX5 EVB:
>>
>> DRAM: DRAM init failed: -19
>> initcall sequence 000000002d=378208 failed at call 02023f0 (err=-19)
>> ### ERROR ### Please RESET the board ###
>>> diff --git a/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c b/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c
>>> deleted file mode 100644
>>> index d0d0900..0000000
>>> --- a/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c
>>> +++ /dev/null
>>> @@ -1,60 +0,0 @@
>>> -/*
>>> - * (C) Copyright 2016 Rockchip Electronics Co., Ltd.
>>> - *
>>> - * SPDX-License-Identifier: GPL-2.0
>>> - */
>>> -
>>> -#include <common.h>
>>> -#include <dm.h>
>>> -#include <ram.h>
>>> -#include <syscon.h>
>>> -#include <asm/arch/clock.h>
>>> -#include <asm/arch/grf_rk3368.h>
>>> -#include <asm/arch/sdram_common.h>
>>> -
>>> -DECLARE_GLOBAL_DATA_PTR;
>>> -struct dram_info {
>>> - struct ram_info info;
>>> - struct rk3368_pmu_grf *pmugrf;
>>> -};
>>> -
>>> -static int rk3368_dmc_probe(struct udevice *dev)
>>> -{
>>> - struct dram_info *priv = dev_get_priv(dev);
>>> -
>>> - priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
>>> - debug("%s: grf=%p\n", __func__, priv->pmugrf);
>>> - priv->info.base = CONFIG_SYS_SDRAM_BASE;
>>> - priv->info.size = rockchip_sdram_size(
>>> - (phys_addr_t)&priv->pmugrf->os_reg[2]);
>>> -
>>> - return 0;
>>> -}
>>> -
>>> -static int rk3368_dmc_get_info(struct udevice *dev, struct ram_info *info)
>>> -{
>>> - struct dram_info *priv = dev_get_priv(dev);
>>> -
>>> - *info = priv->info;
>>> -
>>> - return 0;
>>> -}
>>> -
>>> -static struct ram_ops rk3368_dmc_ops = {
>>> - .get_info = rk3368_dmc_get_info,
>>> -};
>>> -
>>> -
>>> -static const struct udevice_id rk3368_dmc_ids[] = {
>>> - { .compatible = "rockchip,rk3368-dmc" },
>>> - { }
>>> -};
>>> -
>>> -U_BOOT_DRIVER(dmc_rk3368) = {
>>> - .name = "rockchip_rk3368_dmc",
>>> - .id = UCLASS_RAM,
>>> - .of_match = rk3368_dmc_ids,
>>> - .ops = &rk3368_dmc_ops,
>>> - .probe = rk3368_dmc_probe,
>>> - .priv_auto_alloc_size = sizeof(struct dram_info),
>>> -};
>>> diff --git a/doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt b/doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt
>>> new file mode 100644
>>> index 0000000..8e7357d
>>> --- /dev/null
>>> +++ b/doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt
>>> @@ -0,0 +1,67 @@
>>> +RK3368 dynamic memory controller driver
>>> +=======================================
>>> +
>>> +The RK3368 DMC (dynamic memory controller) driver supports setup/initialisation
>>> +during TPL using configuration data from the DTS (i.e. OF_PLATDATA), based on
>>> +the following key configuration data:
>>> + (a) a target-frequency (i.e. operating point) for the memory operation
>>> + (b) a speed-bin (as defined in JESD-79) for the DDR3 used in hardware
>>> + (c) a memory-schedule (i.e. mapping from physical addresses to the address
>>> + pins of the memory bus)
>>> +
>>> +Required properties
>>> +-------------------
>>> +
>>> +- compatible: "rockchip,rk3368-dmc"
>>> +- reg
>>> + protocol controller (PCTL) address and PHY controller (DDRPHY) address
>>> +- rockchip,ddr-speed-bin
>>> + the DDR3 device's speed-bin (as specified according to JESD-79)
>>> + DDR3_800D (5-5-5)
>>> + DDR3_800E (6-6-6)
>>> + DDR3_1066E (6-6-6)
>>> + DDR3_1066F (7-7-7)
>>> + DDR3_1066G (8-8-8)
>>> + DDR3_1333F (7-7-7)
>>> + DDR3_1333G (8-8-8)
>>> + DDR3_1333H (9-9-9)
>>> + DDR3_1333J (10-10-10)
>>> + DDR3_1600G (8-8-8)
>>> + DDR3_1600H (9-9-9)
>>> + DDR3_1600J (10-10-10)
>>> + DDR3_1600K (11-11-11)
>>> + DDR3_1866J (10-10-10)
>>> + DDR3_1866K (11-11-11)
>>> + DDR3_1866L (12-12-12)
>>> + DDR3_1866M (13-13-13)
>>> + DDR3_2133K (11-11-11)
>>> + DDR3_2133L (12-12-12)
>>> + DDR3_2133M (13-13-13)
>>> + DDR3_2133N (14-14-14)
>>> +- rockchip,ddr-frequency:
>>> + target DDR clock frequency in Hz (not all frequencies may be supported,
>>> + as there's some cooperation from the clock-driver required)
>>> +- rockchip,memory-schedule:
>>> + controls the decoding of physical addresses to DRAM addressing (i.e. how
>>> + the physical address maps onto the address pins/chip-select of the device)
>>> + DMC_MSCH_CBDR: column -> bank -> device -> row
>>> + DMC_MSCH_CBRD: column -> band -> row -> device
>>> + DMC_MSCH_CRBD: column -> row -> band -> device
>>> +
>>> +Example (for DDR3-1600K and 800MHz)
>>> +-----------------------------------
>>> +
>>> + #include <dt-bindings/memory/rk3368-dmc.h>
>>> +
>>> + dmc: dmc at ff610000 {
>>> + u-boot,dm-pre-reloc;
>>> + compatible = "rockchip,rk3368-dmc";
>>> + reg = <0 0xff610000 0 0x400
>>> + 0 0xff620000 0 0x400>;
>>> + };
>>> +
>>> + &dmc {
>>> + rockchip,ddr-speed-bin = <DDR3_1600K>;
>>> + rockchip,ddr-frequency = <800000000>;
>>> + rockchip,memory-schedule = <DMC_MSCH_CBRD>;
>>> + };
>>> diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
>>> index c409c48..51ae6be 100644
>>> --- a/drivers/ram/Makefile
>>> +++ b/drivers/ram/Makefile
>>> @@ -8,3 +8,5 @@ obj-$(CONFIG_RAM) += ram-uclass.o
>>> obj-$(CONFIG_SANDBOX) += sandbox_ram.o
>>> obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o
>>> obj-$(CONFIG_ARCH_BMIPS) += bmips_ram.o
>>> +
>>> +obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
>>> diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile
>>> new file mode 100644
>>> index 0000000..b09d03c
>>> --- /dev/null
>>> +++ b/drivers/ram/rockchip/Makefile
>>> @@ -0,0 +1,7 @@
>>> +#
>>> +# Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
>>> +#
>>> +# SPDX-License-Identifier: GPL-2.0+
>>> +#
>>> +
>>> +obj-$(CONFIG_ROCKCHIP_RK3368) = dmc-rk3368.o
>>> diff --git a/drivers/ram/rockchip/dmc-rk3368.c b/drivers/ram/rockchip/dmc-rk3368.c
>>> new file mode 100644
>>> index 0000000..fea96a5
>>> --- /dev/null
>>> +++ b/drivers/ram/rockchip/dmc-rk3368.c
>>> @@ -0,0 +1,990 @@
>>> +/*
>>> + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
>>> + *
>>> + * SPDX-License-Identifier: GPL-2.0
>>> + */
>>> +
>>> +#include <common.h>
>>> +#include <clk.h>
>>> +#include <dm.h>
>>> +#include <dt-bindings/memory/rk3368-dmc.h>
>>> +#include <dt-structs.h>
>>> +#include <ram.h>
>>> +#include <regmap.h>
>>> +#include <syscon.h>
>>> +#include <asm/io.h>
>>> +#include <asm/arch/clock.h>
>>> +#include <asm/arch/cru_rk3368.h>
>>> +#include <asm/arch/grf_rk3368.h>
>>> +#include <asm/arch/ddr_rk3368.h>
>>> +#include <asm/arch/sdram.h>
>>> +#include <asm/arch/sdram_common.h>
>>> +
>>> +DECLARE_GLOBAL_DATA_PTR;
>>> +
>>> +struct dram_info {
>>> + struct ram_info info;
>>> + struct clk ddr_clk;
>>> + struct rk3368_cru *cru;
>>> + struct rk3368_grf *grf;
>>> + struct rk3368_ddr_pctl *pctl;
>>> + struct rk3368_ddrphy *phy;
>>> + struct rk3368_pmu_grf *pmugrf;
>>> + struct rk3368_msch *msch;
>>> +};
>>> +
>>> +struct rk3368_sdram_params {
>>> +#if CONFIG_IS_ENABLED(OF_PLATDATA)
>>> + struct dtd_rockchip_rk3368_dmc of_plat;
>>> +#endif
>>> + struct rk3288_sdram_pctl_timing pctl_timing;
>>> + u32 trefi_mem_ddr3;
>>> + struct rk3288_sdram_channel chan;
>>> + struct regmap *map;
>>> + u32 ddr_freq;
>>> + u32 memory_schedule;
>>> + u32 ddr_speed_bin;
>>> + u32 tfaw_mult;
>>> +};
>>> +
>>> +/* PTCL bits */
>>> +enum {
>>> + /* PCTL_DFISTCFG0 */
>>> + DFI_INIT_START = BIT(0),
>>> + DFI_DATA_BYTE_DISABLE_EN = BIT(2),
>>> +
>>> + /* PCTL_DFISTCFG1 */
>>> + DFI_DRAM_CLK_SR_EN = BIT(0),
>>> + DFI_DRAM_CLK_DPD_EN = BIT(1),
>>> + ODT_LEN_BL8_W_SHIFT = 16,
>>> +
>>> + /* PCTL_DFISTCFG2 */
>>> + DFI_PARITY_INTR_EN = BIT(0),
>>> + DFI_PARITY_EN = BIT(1),
>>> +
>>> + /* PCTL_DFILPCFG0 */
>>> + TLP_RESP_TIME_SHIFT = 16,
>>> + LP_SR_EN = BIT(8),
>>> + LP_PD_EN = BIT(0),
>>> +
>>> + /* PCTL_DFIODTCFG */
>>> + RANK0_ODT_WRITE_SEL = BIT(3),
>>> + RANK1_ODT_WRITE_SEL = BIT(11),
>>> +
>>> + /* PCTL_SCFG */
>>> + HW_LOW_POWER_EN = BIT(0),
>>> +
>>> + /* PCTL_MCMD */
>>> + START_CMD = BIT(31),
>>> + MCMD_RANK0 = BIT(20),
>>> + MCMD_RANK1 = BIT(21),
>>> + DESELECT_CMD = 0,
>>> + PREA_CMD,
>>> + REF_CMD,
>>> + MRS_CMD,
>>> + ZQCS_CMD,
>>> + ZQCL_CMD,
>>> + RSTL_CMD,
>>> + MRR_CMD = 8,
>>> + DPDE_CMD,
>>> +
>>> + /* PCTL_POWCTL */
>>> + POWER_UP_START = BIT(0),
>>> +
>>> + /* PCTL_POWSTAT */
>>> + POWER_UP_DONE = BIT(0),
>>> +
>>> + /* PCTL_SCTL */
>>> + INIT_STATE = 0,
>>> + CFG_STATE,
>>> + GO_STATE,
>>> + SLEEP_STATE,
>>> + WAKEUP_STATE,
>>> +
>>> + /* PCTL_STAT */
>>> + LP_TRIG_SHIFT = 4,
>>> + LP_TRIG_MASK = 7,
>>> + PCTL_STAT_MSK = 7,
>>> + INIT_MEM = 0,
>>> + CONFIG,
>>> + CONFIG_REQ,
>>> + ACCESS,
>>> + ACCESS_REQ,
>>> + LOW_POWER,
>>> + LOW_POWER_ENTRY_REQ,
>>> + LOW_POWER_EXIT_REQ,
>>> +
>>> + /* PCTL_MCFG */
>>> + DDR2_DDR3_BL_8 = BIT(0),
>>> + DDR3_EN = BIT(5),
>>> + TFAW_TRRD_MULT4 = (0 << 18),
>>> + TFAW_TRRD_MULT5 = (1 << 18),
>>> + TFAW_TRRD_MULT6 = (2 << 18),
>>> +};
>>> +
>>> +#define DDR3_MR0_WR(n) \
>>> + ((n <= 8) ? ((n - 4) << 9) : (((n >> 1) & 0x7) << 9))
>>> +#define DDR3_MR0_CL(n) \
>>> + ((((n - 4) & 0x7) << 4) | (((n - 4) & 0x8) >> 2))
>>> +#define DDR3_MR0_BL8 \
>>> + (0 << 0)
>>> +#define DDR3_MR0_DLL_RESET \
>>> + (1 << 8)
>>> +#define DDR3_MR1_RTT120OHM \
>>> + ((0 << 9) | (1 << 6) | (0 << 2))
>>> +#define DDR3_MR2_TWL(n) \
>>> + (((n - 5) & 0x7) << 3)
>>> +
>>> +
>>> +#ifdef CONFIG_TPL_BUILD
>>> +
>>> +static void ddr_set_noc_spr_err_stall(struct rk3368_grf *grf, bool enable)
>>> +{
>>> + if (enable)
>>> + rk_setreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL);
>>> + else
>>> + rk_clrreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL);
>>> +}
>>> +
>>> +static void ddr_set_ddr3_mode(struct rk3368_grf *grf, bool ddr3_mode)
>>> +{
>>> + if (ddr3_mode)
>>> + rk_setreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3);
>>> + else
>>> + rk_clrreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3);
>>> +}
>>> +
>>> +static void ddrphy_config(struct rk3368_ddrphy *phy,
>>> + u32 tcl, u32 tal, u32 tcwl)
>>> +{
>>> + int i;
>>> +
>>> + /* Set to DDR3 mode */
>>> + clrsetbits_le32(&phy->reg[1], 0x3, 0x0);
>>> +
>>> + /* DDRPHY_REGB: CL, AL */
>>> + clrsetbits_le32(&phy->reg[0xb], 0xff, tcl << 4 | tal);
>>> + /* DDRPHY_REGC: CWL */
>>> + clrsetbits_le32(&phy->reg[0xc], 0x0f, tcwl);
>>> +
>>> + /* Update drive-strength */
>>> + writel(0xcc, &phy->reg[0x11]);
>>> + writel(0xaa, &phy->reg[0x16]);
>>> + /*
>>> + * Update NRCOMP/PRCOMP for all 4 channels (for details of all
>>> + * affected registers refer to the documentation of DDRPHY_REG20
>>> + * and DDRPHY_REG21 in the RK3368 TRM.
>>> + */
>>> + for (i = 0; i < 4; ++i) {
>>> + writel(0xcc, &phy->reg[0x20 + i * 0x10]);
>>> + writel(0x44, &phy->reg[0x21 + i * 0x10]);
>>> + }
>>> +
>>> + /* Enable write-leveling calibration bypass */
>>> + setbits_le32(&phy->reg[2], BIT(3));
>>> +}
>>> +
>>> +static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
>>> +{
>>> + int i;
>>> +
>>> + for (i = 0; i < n / sizeof(u32); i++)
>>> + writel(*src++, dest++);
>>> +}
>>> +
>>> +static void send_command(struct rk3368_ddr_pctl *pctl, u32 rank, u32 cmd)
>>> +{
>>> + u32 mcmd = START_CMD | cmd | rank;
>>> +
>>> + debug("%s: writing %x to MCMD\n", __func__, mcmd);
>>> + writel(mcmd, &pctl->mcmd);
>>> + while (readl(&pctl->mcmd) & START_CMD)
>>> + /* spin */;
>>> +}
>>> +
>>> +static void send_mrs(struct rk3368_ddr_pctl *pctl,
>>> + u32 rank, u32 mr_num, u32 mr_data)
>>> +{
>>> + u32 mcmd = START_CMD | MRS_CMD | rank | (mr_num << 17) | (mr_data << 4);
>>> +
>>> + debug("%s: writing %x to MCMD\n", __func__, mcmd);
>>> + writel(mcmd, &pctl->mcmd);
>>> + while (readl(&pctl->mcmd) & START_CMD)
>>> + /* spin */;
>>> +}
>>> +
>>> +static int memory_init(struct rk3368_ddr_pctl *pctl,
>>> + struct rk3368_sdram_params *params)
>>> +{
>>> + u32 mr[4];
>>> + const ulong timeout_ms = 500;
>>> + ulong tmp;
>>> +
>>> + /*
>>> + * Power up DRAM by DDR_PCTL_POWCTL[0] register of PCTL and
>>> + * wait power up DRAM finish with DDR_PCTL_POWSTAT[0] register
>>> + * of PCTL.
>>> + */
>>> + writel(POWER_UP_START, &pctl->powctl);
>>> +
>>> + tmp = get_timer(0);
>>> + do {
>>> + if (get_timer(tmp) > timeout_ms) {
>>> + error("%s: POWER_UP_START did not complete in %ld ms\n",
>>> + __func__, timeout_ms);
>>> + return -ETIME;
>>> + }
>>> + } while (!(readl(&pctl->powstat) & POWER_UP_DONE));
>>> +
>>> + /* Configure MR0 through MR3 */
>>> + mr[0] = DDR3_MR0_WR(params->pctl_timing.twr) |
>>> + DDR3_MR0_CL(params->pctl_timing.tcl) |
>>> + DDR3_MR0_DLL_RESET;
>>> + mr[1] = DDR3_MR1_RTT120OHM;
>>> + mr[2] = DDR3_MR2_TWL(params->pctl_timing.tcwl);
>>> + mr[3] = 0;
>>> +
>>> + /*
>>> + * Also see RK3368 Technical Reference Manual:
>>> + * "16.6.2 Initialization (DDR3 Initialization Sequence)"
>>> + */
>>> + send_command(pctl, MCMD_RANK0 | MCMD_RANK1, DESELECT_CMD);
>>> + udelay(1);
>>> + send_command(pctl, MCMD_RANK0 | MCMD_RANK1, PREA_CMD);
>>> + send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 2, mr[2]);
>>> + send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 3, mr[3]);
>>> + send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 1, mr[1]);
>>> + send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 0, mr[0]);
>>> + send_command(pctl, MCMD_RANK0 | MCMD_RANK1, ZQCL_CMD);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static void move_to_config_state(struct rk3368_ddr_pctl *pctl)
>>> +{
>>> + /*
>>> + * Also see RK3368 Technical Reference Manual:
>>> + * "16.6.1 State transition of PCTL (Moving to Config State)"
>>> + */
>>> + u32 state = readl(&pctl->stat) & PCTL_STAT_MSK;
>>> +
>>> + switch (state) {
>>> + case LOW_POWER:
>>> + writel(WAKEUP_STATE, &pctl->sctl);
>>> + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
>>> + /* spin */;
>>> +
>>> + /* fall-through */
>>> + case ACCESS:
>>> + case INIT_MEM:
>>> + writel(CFG_STATE, &pctl->sctl);
>>> + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
>>> + /* spin */;
>>> + break;
>>> +
>>> + case CONFIG:
>>> + return;
>>> +
>>> + default:
>>> + break;
>>> + }
>>> +}
>>> +
>>> +static void move_to_access_state(struct rk3368_ddr_pctl *pctl)
>>> +{
>>> + /*
>>> + * Also see RK3368 Technical Reference Manual:
>>> + * "16.6.1 State transition of PCTL (Moving to Access State)"
>>> + */
>>> + u32 state = readl(&pctl->stat) & PCTL_STAT_MSK;
>>> +
>>> + switch (state) {
>>> + case LOW_POWER:
>>> + if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) &
>>> + LP_TRIG_MASK) == 1)
>>> + return;
>>> +
>>> + writel(WAKEUP_STATE, &pctl->sctl);
>>> + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
>>> + /* spin */;
>>> +
>>> + /* fall-through */
>>> + case INIT_MEM:
>>> + writel(CFG_STATE, &pctl->sctl);
>>> + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
>>> + /* spin */;
>>> +
>>> + /* fall-through */
>>> + case CONFIG:
>>> + writel(GO_STATE, &pctl->sctl);
>>> + while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG)
>>> + /* spin */;
>>> + break;
>>> +
>>> + case ACCESS:
>>> + return;
>>> +
>>> + default:
>>> + break;
>>> + }
>>> +}
>>> +
>>> +static void ddrctl_reset(struct rk3368_cru *cru)
>>> +{
>>> + const u32 ctl_reset = BIT(3) | BIT(2);
>>> + const u32 phy_reset = BIT(1) | BIT(0);
>>> +
>>> + rk_setreg(&cru->softrst_con[10], ctl_reset | phy_reset);
>>> + udelay(1);
>>> + rk_clrreg(&cru->softrst_con[10], ctl_reset | phy_reset);
>>> +}
>>> +
>>> +static void ddrphy_reset(struct rk3368_ddrphy *ddrphy)
>>> +{
>>> + clrbits_le32(&ddrphy->reg[0], BIT(3) | BIT(2));
>>> + udelay(1);
>>> + setbits_le32(&ddrphy->reg[0], BIT(3) | BIT(2));
>>> +}
>>> +
>>> +static void ddrphy_config_delays(struct rk3368_ddrphy *ddrphy, u32 freq)
>>> +{
>>> + u32 dqs_dll_delay;
>>> +
>>> + setbits_le32(&ddrphy->reg[0x13], BIT(4));
>>> + clrbits_le32(&ddrphy->reg[0x14], BIT(3));
>>> +
>>> + setbits_le32(&ddrphy->reg[0x26], BIT(4));
>>> + clrbits_le32(&ddrphy->reg[0x27], BIT(3));
>>> +
>>> + setbits_le32(&ddrphy->reg[0x36], BIT(4));
>>> + clrbits_le32(&ddrphy->reg[0x37], BIT(3));
>>> +
>>> + setbits_le32(&ddrphy->reg[0x46], BIT(4));
>>> + clrbits_le32(&ddrphy->reg[0x47], BIT(3));
>>> +
>>> + setbits_le32(&ddrphy->reg[0x56], BIT(4));
>>> + clrbits_le32(&ddrphy->reg[0x57], BIT(3));
>>> +
>>> + if (freq <= 400000000)
>>> + setbits_le32(&ddrphy->reg[0xa4], 0x1f);
>>> + else
>>> + clrbits_le32(&ddrphy->reg[0xa4], 0x1f);
>>> +
>>> + if (freq < 681000000)
>>> + dqs_dll_delay = 3; /* 67.5 degree delay */
>>> + else
>>> + dqs_dll_delay = 2; /* 45 degree delay */
>>> +
>>> + writel(dqs_dll_delay, &ddrphy->reg[0x28]);
>>> + writel(dqs_dll_delay, &ddrphy->reg[0x38]);
>>> + writel(dqs_dll_delay, &ddrphy->reg[0x48]);
>>> + writel(dqs_dll_delay, &ddrphy->reg[0x58]);
>>> +}
>>> +
>>> +static int dfi_cfg(struct rk3368_ddr_pctl *pctl)
>>> +{
>>> + const ulong timeout_ms = 200;
>>> + ulong tmp;
>>> +
>>> + writel(DFI_DATA_BYTE_DISABLE_EN, &pctl->dfistcfg0);
>>> +
>>> + writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN,
>>> + &pctl->dfistcfg1);
>>> + writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2);
>>> + writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN,
>>> + &pctl->dfilpcfg0);
>>> +
>>> + writel(1, &pctl->dfitphyupdtype0);
>>> +
>>> + writel(0x1f, &pctl->dfitphyrdlat);
>>> + writel(0, &pctl->dfitphywrdata);
>>> + writel(0, &pctl->dfiupdcfg); /* phyupd and ctrlupd disabled */
>>> +
>>> + setbits_le32(&pctl->dfistcfg0, DFI_INIT_START);
>>> +
>>> + tmp = get_timer(0);
>>> + do {
>>> + if (get_timer(tmp) > timeout_ms) {
>>> + error("%s: DFI init did not complete within %ld ms\n",
>>> + __func__, timeout_ms);
>>> + return -ETIME;
>>> + }
>>> + } while ((readl(&pctl->dfiststat0) & 1) == 0);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static inline u32 ps_to_tCK(const u32 ps, const ulong freq)
>>> +{
>>> + const ulong MHz = 1000000;
>>> + return DIV_ROUND_UP(ps * freq, 1000000 * MHz);
>>> +}
>>> +
>>> +static inline u32 ns_to_tCK(const u32 ns, const ulong freq)
>>> +{
>>> + return ps_to_tCK(ns * 1000, freq);
>>> +}
>>> +
>>> +static inline u32 tCK_to_ps(const ulong tCK, const ulong freq)
>>> +{
>>> + const ulong MHz = 1000000;
>>> + return DIV_ROUND_UP(tCK * 1000000 * MHz, freq);
>>> +}
>>> +
>>> +static int pctl_calc_timings(struct rk3368_sdram_params *params,
>>> + ulong freq)
>>> +{
>>> + struct rk3288_sdram_pctl_timing *pctl_timing = ¶ms->pctl_timing;
>>> + const ulong MHz = 1000000;
>>> + u32 tccd;
>>> + u32 tfaw_as_ps;
>>> +
>>> + if (params->ddr_speed_bin != DDR3_1600K) {
>>> + error("%s: unimplemented DDR3 speed bin %d\n",
>>> + __func__, params->ddr_speed_bin);
>>> + return -1;
>>> + }
>>> +
>>> + /* PCTL is clocked at 1/2 the DRAM clock; err on the side of caution */
>>> + pctl_timing->togcnt1u = DIV_ROUND_UP(freq, 2 * MHz);
>>> + pctl_timing->togcnt100n = DIV_ROUND_UP(freq / 10, 2 * MHz);
>>> +
>>> + pctl_timing->tinit = 200; /* 200 usec */
>>> + pctl_timing->trsth = 500; /* 500 usec */
>>> + pctl_timing->trefi = 78; /* 7.8usec = 78 * 100ns */
>>> + params->trefi_mem_ddr3 = ns_to_tCK(pctl_timing->trefi * 100, freq);
>>> +
>>> + if (freq <= (400 * MHz)) {
>>> + pctl_timing->tcl = 6;
>>> + pctl_timing->tcwl = 10;
>>> + } else if (freq <= (533 * MHz)) {
>>> + pctl_timing->tcl = 8;
>>> + pctl_timing->tcwl = 6;
>>> + } else if (freq <= (666 * MHz)) {
>>> + pctl_timing->tcl = 10;
>>> + pctl_timing->tcwl = 7;
>>> + } else {
>>> + pctl_timing->tcl = 11;
>>> + pctl_timing->tcwl = 8;
>>> + }
>>> +
>>> + pctl_timing->tmrd = 4; /* 4 tCK (all speed bins) */
>>> + pctl_timing->trfc = ns_to_tCK(350, freq); /* tRFC: 350 (max) @ 8GBit */
>>> + pctl_timing->trp = max(4u, ps_to_tCK(13750, freq));
>>> + /*
>>> + * JESD-79:
>>> + * READ to WRITE Command Delay = RL + tCCD / 2 + 2tCK - WL
>>> + */
>>> + tccd = 4;
>>> + pctl_timing->trtw = pctl_timing->tcl + tccd/2 + 2 - pctl_timing->tcwl;
>>> + pctl_timing->tal = 0;
>>> + pctl_timing->tras = ps_to_tCK(35000, freq);
>>> + pctl_timing->trc = ps_to_tCK(48750, freq);
>>> + pctl_timing->trcd = ps_to_tCK(13750, freq);
>>> + pctl_timing->trrd = max(4u, ps_to_tCK(7500, freq));
>>> + pctl_timing->trtp = max(4u, ps_to_tCK(7500, freq));
>>> + pctl_timing->twr = ps_to_tCK(15000, freq);
>>> + /* The DDR3 mode-register does only support even values for tWR > 8. */
>>> + if (pctl_timing->twr > 8)
>>> + pctl_timing->twr = (pctl_timing->twr + 1) & ~1;
>>> + pctl_timing->twtr = max(4u, ps_to_tCK(7500, freq));
>>> + pctl_timing->texsr = 512; /* tEXSR(max) is tDLLLK */
>>> + pctl_timing->txp = max(3u, ps_to_tCK(6000, freq));
>>> + pctl_timing->txpdll = max(10u, ps_to_tCK(24000, freq));
>>> + pctl_timing->tzqcs = max(64u, ps_to_tCK(80000, freq));
>>> + pctl_timing->tzqcsi = 10000; /* as used by Rockchip */
>>> + pctl_timing->tdqs = 1; /* fixed for DDR3 */
>>> + pctl_timing->tcksre = max(5u, ps_to_tCK(10000, freq));
>>> + pctl_timing->tcksrx = max(5u, ps_to_tCK(10000, freq));
>>> + pctl_timing->tcke = max(3u, ps_to_tCK(5000, freq));
>>> + pctl_timing->tmod = max(12u, ps_to_tCK(15000, freq));
>>> + pctl_timing->trstl = ns_to_tCK(100, freq);
>>> + pctl_timing->tzqcl = max(256u, ps_to_tCK(320000, freq)); /* tZQoper */
>>> + pctl_timing->tmrr = 0;
>>> + pctl_timing->tckesr = pctl_timing->tcke + 1; /* JESD-79: tCKE + 1tCK */
>>> + pctl_timing->tdpd = 0; /* RK3368 TRM: "allowed values for DDR3: 0" */
>>> +
>>> +
>>> + /*
>>> + * The controller can represent tFAW as 4x, 5x or 6x tRRD only.
>>> + * We want to use the smallest multiplier that satisfies the tFAW
>>> + * requirements of the given speed-bin. If necessary, we stretch out
>>> + * tRRD to allow us to operate on a 6x multiplier for tFAW.
>>> + */
>>> + tfaw_as_ps = 40000; /* 40ns: tFAW for DDR3-1600K, 2KB page-size */
>>> + if (tCK_to_ps(pctl_timing->trrd * 6, freq) < tfaw_as_ps) {
>>> + /* If tFAW is > 6 x tRRD, we need to stretch tRRD */
>>> + pctl_timing->trrd = ps_to_tCK(DIV_ROUND_UP(40000, 6), freq);
>>> + params->tfaw_mult = TFAW_TRRD_MULT6;
>>> + } else if (tCK_to_ps(pctl_timing->trrd * 5, freq) < tfaw_as_ps) {
>>> + params->tfaw_mult = TFAW_TRRD_MULT6;
>>> + } else if (tCK_to_ps(pctl_timing->trrd * 4, freq) < tfaw_as_ps) {
>>> + params->tfaw_mult = TFAW_TRRD_MULT5;
>>> + } else {
>>> + params->tfaw_mult = TFAW_TRRD_MULT4;
>>> + }
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static void pctl_cfg(struct rk3368_ddr_pctl *pctl,
>>> + struct rk3368_sdram_params *params,
>>> + struct rk3368_grf *grf)
>>> +{
>>> + /* Configure PCTL timing registers */
>>> + params->pctl_timing.trefi |= BIT(31); /* see PCTL_TREFI */
>>> + copy_to_reg(&pctl->togcnt1u, ¶ms->pctl_timing.togcnt1u,
>>> + sizeof(params->pctl_timing));
>>> + writel(params->trefi_mem_ddr3, &pctl->trefi_mem_ddr3);
>>> +
>>> + /* Set up ODT write selector and ODT write length */
>>> + writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL), &pctl->dfiodtcfg);
>>> + writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1);
>>> +
>>> + /* Set up the CL/CWL-dependent timings of DFI */
>>> + writel((params->pctl_timing.tcl - 1) / 2 - 1, &pctl->dfitrddataen);
>>> + writel((params->pctl_timing.tcwl - 1) / 2 - 1, &pctl->dfitphywrlat);
>>> +
>>> + /* DDR3 */
>>> + writel(params->tfaw_mult | DDR3_EN | DDR2_DDR3_BL_8, &pctl->mcfg);
>>> + writel(0x001c0004, &grf->ddrc0_con0);
>>> +
>>> + setbits_le32(&pctl->scfg, HW_LOW_POWER_EN);
>>> +}
>>> +
>>> +static int ddrphy_data_training(struct rk3368_ddr_pctl *pctl,
>>> + struct rk3368_ddrphy *ddrphy)
>>> +{
>>> + const u32 trefi = readl(&pctl->trefi);
>>> + const ulong timeout_ms = 500;
>>> + ulong tmp;
>>> +
>>> + /* disable auto-refresh */
>>> + writel(0 | BIT(31), &pctl->trefi);
>>> +
>>> + clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x20);
>>> + clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x21);
>>> +
>>> + tmp = get_timer(0);
>>> + do {
>>> + if (get_timer(tmp) > timeout_ms) {
>>> + error("%s: did not complete within %ld ms\n",
>>> + __func__, timeout_ms);
>>> + return -ETIME;
>>> + }
>>> + } while ((readl(&ddrphy->reg[0xff]) & 0xf) != 0xf);
>>> +
>>> + send_command(pctl, MCMD_RANK0 | MCMD_RANK1, PREA_CMD);
>>> + clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x20);
>>> + /* resume auto-refresh */
>>> + writel(trefi | BIT(31), &pctl->trefi);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int sdram_col_row_detect(struct udevice *dev)
>>> +{
>>> + struct dram_info *priv = dev_get_priv(dev);
>>> + struct rk3368_sdram_params *params = dev_get_platdata(dev);
>>> + struct rk3368_ddr_pctl *pctl = priv->pctl;
>>> + struct rk3368_msch *msch = priv->msch;
>>> + const u32 test_pattern = 0x5aa5f00f;
>>> + int row, col;
>>> + uintptr_t addr;
>>> +
>>> + move_to_config_state(pctl);
>>> + writel(6, &msch->ddrconf);
>>> + move_to_access_state(pctl);
>>> +
>>> + /* Detect col */
>>> + for (col = 11; col >= 9; col--) {
>>> + writel(0, CONFIG_SYS_SDRAM_BASE);
>>> + addr = CONFIG_SYS_SDRAM_BASE +
>>> + (1 << (col + params->chan.bw - 1));
>>> + writel(test_pattern, addr);
>>> + if ((readl(addr) == test_pattern) &&
>>> + (readl(CONFIG_SYS_SDRAM_BASE) == 0))
>>> + break;
>>> + }
>>> +
>>> + if (col == 8) {
>>> + error("%s: col detect error\n", __func__);
>>> + return -EINVAL;
>>> + }
>>> +
>>> + move_to_config_state(pctl);
>>> + writel(15, &msch->ddrconf);
>>> + move_to_access_state(pctl);
>>> +
>>> + /* Detect row*/
>>> + for (row = 16; row >= 12; row--) {
>>> + writel(0, CONFIG_SYS_SDRAM_BASE);
>>> + addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
>>> + writel(test_pattern, addr);
>>> + if ((readl(addr) == test_pattern) &&
>>> + (readl(CONFIG_SYS_SDRAM_BASE) == 0))
>>> + break;
>>> + }
>>> +
>>> + if (row == 11) {
>>> + error("%s: row detect error\n", __func__);
>>> + return -EINVAL;
>>> + }
>>> +
>>> + /* Record results */
>>> + debug("%s: col %d, row %d\n", __func__, col, row);
>>> + params->chan.col = col;
>>> + params->chan.cs0_row = row;
>>> + params->chan.cs1_row = row;
>>> + params->chan.row_3_4 = 0;
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int msch_niu_config(struct rk3368_msch *msch,
>>> + struct rk3368_sdram_params *params)
>>> +{
>>> + int i;
>>> + const u8 cols = params->chan.col - ((params->chan.bw == 2) ? 0 : 1);
>>> + const u8 rows = params->chan.cs0_row;
>>> +
>>> + /*
>>> + * The DDR address-translation table always assumes a 32bit
>>> + * bus and the comparison below takes care of adjusting for
>>> + * a 16bit bus (i.e. one column-address is consumed).
>>> + */
>>> + const struct {
>>> + u8 rows;
>>> + u8 columns;
>>> + u8 type;
>>> + } ddrconf_table[] = {
>>> + /*
>>> + * C-B-R-D patterns are first. For these we require an
>>> + * exact match for the columns and rows (as there's
>>> + * one entry per possible configuration).
>>> + */
>>> + [0] = { .rows = 13, .columns = 10, .type = DMC_MSCH_CBRD },
>>> + [1] = { .rows = 14, .columns = 10, .type = DMC_MSCH_CBRD },
>>> + [2] = { .rows = 15, .columns = 10, .type = DMC_MSCH_CBRD },
>>> + [3] = { .rows = 16, .columns = 10, .type = DMC_MSCH_CBRD },
>>> + [4] = { .rows = 14, .columns = 11, .type = DMC_MSCH_CBRD },
>>> + [5] = { .rows = 15, .columns = 11, .type = DMC_MSCH_CBRD },
>>> + [6] = { .rows = 16, .columns = 11, .type = DMC_MSCH_CBRD },
>>> + [7] = { .rows = 13, .columns = 9, .type = DMC_MSCH_CBRD },
>>> + [8] = { .rows = 14, .columns = 9, .type = DMC_MSCH_CBRD },
>>> + [9] = { .rows = 15, .columns = 9, .type = DMC_MSCH_CBRD },
>>> + [10] = { .rows = 16, .columns = 9, .type = DMC_MSCH_CBRD },
>>> + /*
>>> + * 11 through 13 are C-R-B-D patterns. These are
>>> + * matched for an exact number of columns and to
>>> + * ensure that the hardware uses at least as many rows
>>> + * as the pattern requires (i.e. we make sure that
>>> + * there's no gaps up until we hit the device/chip-select;
>>> + * however, these patterns can accept up to 16 rows,
>>> + * as the row-address continues right after the CS
>>> + * switching)
>>> + */
>>> + [11] = { .rows = 15, .columns = 10, .type = DMC_MSCH_CRBD },
>>> + [12] = { .rows = 14, .columns = 11, .type = DMC_MSCH_CRBD },
>>> + [13] = { .rows = 13, .columns = 10, .type = DMC_MSCH_CRBD },
>>> + /*
>>> + * 14 and 15 are catch-all variants using a C-B-D-R
>>> + * scheme (i.e. alternating the chip-select every time
>>> + * C-B overflows) and stuffing the remaining C-bits
>>> + * into the top. Matching needs to make sure that the
>>> + * number of columns is either an exact match (i.e. we
>>> + * can use less the the maximum number of rows) -or-
>>> + * that the columns exceed what is given in this table
>>> + * and the rows are an exact match (in which case the
>>> + * remaining C-bits will be stuffed onto the top after
>>> + * the device/chip-select switches).
>>> + */
>>> + [14] = { .rows = 16, .columns = 10, .type = DMC_MSCH_CBDR },
>>> + [15] = { .rows = 16, .columns = 9, .type = DMC_MSCH_CBDR },
>>> + };
>>> +
>>> + /*
>>> + * For C-B-R-D, we need an exact match (i.e. both for the number of
>>> + * columns and rows), while for C-B-D-R, only the the number of
>>> + * columns needs to match.
>>> + */
>>> + for (i = 0; i < ARRAY_SIZE(ddrconf_table); i++) {
>>> + bool match = false;
>>> +
>>> + /* If this entry if for a different matcher, then skip it */
>>> + if (ddrconf_table[i].type != params->memory_schedule)
>>> + continue;
>>> +
>>> + /*
>>> + * Match according to the rules (exact/inexact/at-least)
>>> + * documented in the ddrconf_table above.
>>> + */
>>> + switch (params->memory_schedule) {
>>> + case DMC_MSCH_CBRD:
>>> + match = (ddrconf_table[i].columns == cols) &&
>>> + (ddrconf_table[i].rows == rows);
>>> + break;
>>> +
>>> + case DMC_MSCH_CRBD:
>>> + match = (ddrconf_table[i].columns == cols) &&
>>> + (ddrconf_table[i].rows <= rows);
>>> + break;
>>> +
>>> + case DMC_MSCH_CBDR:
>>> + match = (ddrconf_table[i].columns == cols) ||
>>> + ((ddrconf_table[i].columns <= cols) &&
>>> + (ddrconf_table[i].rows == rows));
>>> + break;
>>> +
>>> + default:
>>> + break;
>>> + }
>>> +
>>> + if (match) {
>>> + debug("%s: setting ddrconf 0x%x\n", __func__, i);
>>> + writel(i, &msch->ddrconf);
>>> + return 0;
>>> + }
>>> + }
>>> +
>>> + error("%s: ddrconf (NIU config) not found\n", __func__);
>>> + return -EINVAL;
>>> +}
>>> +
>>> +static void dram_all_config(struct udevice *dev)
>>> +{
>>> + struct dram_info *priv = dev_get_priv(dev);
>>> + struct rk3368_pmu_grf *pmugrf = priv->pmugrf;
>>> + struct rk3368_sdram_params *params = dev_get_platdata(dev);
>>> + const struct rk3288_sdram_channel *info = ¶ms->chan;
>>> + u32 sys_reg = 0;
>>> + const int chan = 0;
>>> +
>>> + sys_reg |= DDR3 << SYS_REG_DDRTYPE_SHIFT;
>>> + sys_reg |= 0 << SYS_REG_NUM_CH_SHIFT;
>>> +
>>> + sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan);
>>> + sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan);
>>> + sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan);
>>> + sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan);
>>> + sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan);
>>> + sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan);
>>> + sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan);
>>> + sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan);
>>> + sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan);
>>> +
>>> + writel(sys_reg, &pmugrf->os_reg[2]);
>>> +}
>>> +
>>> +static int setup_sdram(struct udevice *dev)
>>> +{
>>> + struct dram_info *priv = dev_get_priv(dev);
>>> + struct rk3368_sdram_params *params = dev_get_platdata(dev);
>>> +
>>> + struct rk3368_ddr_pctl *pctl = priv->pctl;
>>> + struct rk3368_ddrphy *ddrphy = priv->phy;
>>> + struct rk3368_cru *cru = priv->cru;
>>> + struct rk3368_grf *grf = priv->grf;
>>> + struct rk3368_msch *msch = priv->msch;
>>> +
>>> + int ret;
>>> +
>>> + /* The input clock (i.e. DPLL) needs to be 2x the DRAM frequency */
>>> + ret = clk_set_rate(&priv->ddr_clk, 2 * params->ddr_freq);
>>> + if (ret < 0) {
>>> + debug("%s: could not set DDR clock: %d\n", __func__, ret);
>>> + return ret;
>>> + }
>>> +
>>> + /* Update the read-latency for the RK3368 */
>>> + writel(0x32, &msch->readlatency);
>>> +
>>> + /* Initialise the DDR PCTL and DDR PHY */
>>> + ddrctl_reset(cru);
>>> + ddrphy_reset(ddrphy);
>>> + ddrphy_config_delays(ddrphy, params->ddr_freq);
>>> + dfi_cfg(pctl);
>>> + /* Configure relative system information of grf_ddrc0_con0 register */
>>> + ddr_set_ddr3_mode(grf, true);
>>> + ddr_set_noc_spr_err_stall(grf, true);
>>> + /* Calculate timings */
>>> + pctl_calc_timings(params, params->ddr_freq);
>>> + /* Initialise the device timings in protocol controller */
>>> + pctl_cfg(pctl, params, grf);
>>> + /* Configure AL, CL ... information of PHY registers */
>>> + ddrphy_config(ddrphy,
>>> + params->pctl_timing.tcl,
>>> + params->pctl_timing.tal,
>>> + params->pctl_timing.tcwl);
>>> +
>>> + /* Initialize DRAM and configure with mode-register values */
>>> + ret = memory_init(pctl, params);
>>> + if (ret)
>>> + goto error;
>>> +
>>> + move_to_config_state(pctl);
>>> + /* Perform data-training */
>>> + ddrphy_data_training(pctl, ddrphy);
>>> + move_to_access_state(pctl);
>>> +
>>> + /* TODO(prt): could detect rank in training... */
>>> + params->chan.rank = 2;
>>> + /* TODO(prt): bus width is not auto-detected (yet)... */
>>> + params->chan.bw = 2; /* 32bit wide bus */
>>> + params->chan.dbw = params->chan.dbw; /* 32bit wide bus */
>>> +
>>> + /* DDR3 is always 8 bank */
>>> + params->chan.bk = 3;
>>> + /* Detect col and row number */
>>> + ret = sdram_col_row_detect(dev);
>>> + if (ret)
>>> + goto error;
>>> +
>>> + /* Configure NIU DDR configuration */
>>> + ret = msch_niu_config(msch, params);
>>> + if (ret)
>>> + goto error;
>>> +
>>> + /* set up OS_REG to communicate w/ next stage and OS */
>>> + dram_all_config(dev);
>>> +
>>> + return 0;
>>> +
>>> +error:
>>> + printf("DRAM init failed!\n");
>>> + hang();
>>> +}
>>> +#endif
>>> +
>>> +static int rk3368_dmc_ofdata_to_platdata(struct udevice *dev)
>>> +{
>>> + int ret = 0;
>>> +
>>> +#if !CONFIG_IS_ENABLED(OF_PLATDATA)
>>> + struct rk3368_sdram_params *plat = dev_get_platdata(dev);
>>> +
>>> + ret = regmap_init_mem(dev, &plat->map);
>>> + if (ret)
>>> + return ret;
>>> +#endif
>>> +
>>> + return ret;
>>> +}
>>> +
>>> +#if CONFIG_IS_ENABLED(OF_PLATDATA)
>>> +static int conv_of_platdata(struct udevice *dev)
>>> +{
>>> + struct rk3368_sdram_params *plat = dev_get_platdata(dev);
>>> + struct dtd_rockchip_rk3368_dmc *of_plat = &plat->of_plat;
>>> + int ret;
>>> +
>>> + plat->ddr_freq = of_plat->rockchip_ddr_frequency;
>>> + plat->ddr_speed_bin = of_plat->rockchip_ddr_speed_bin;
>>> + plat->memory_schedule = of_plat->rockchip_memory_schedule;
>>> +
>>> + ret = regmap_init_mem_platdata(dev, of_plat->reg,
>>> + ARRAY_SIZE(of_plat->reg) / 2,
>>> + &plat->map);
>>> + if (ret)
>>> + return ret;
>>> +
>>> + return 0;
>>> +}
>>> +#endif
>>> +
>>> +static int rk3368_dmc_probe(struct udevice *dev)
>>> +{
>>> +#ifdef CONFIG_TPL_BUILD
>>> + struct rk3368_sdram_params *plat = dev_get_platdata(dev);
>>> + struct rk3368_ddr_pctl *pctl;
>>> + struct rk3368_ddrphy *ddrphy;
>>> + struct rk3368_cru *cru;
>>> + struct rk3368_grf *grf;
>>> + struct rk3368_msch *msch;
>>> + int ret;
>>> + struct udevice *dev_clk;
>>> +#endif
>>> + struct dram_info *priv = dev_get_priv(dev);
>>> +
>>> +#if CONFIG_IS_ENABLED(OF_PLATDATA)
>>> + ret = conv_of_platdata(dev);
>>> + if (ret)
>>> + return ret;
>>> +#endif
>>> +
>>> + priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
>>> + debug("%s: pmugrf=%p\n", __func__, priv->pmugrf);
>>> +
>>> +#ifdef CONFIG_TPL_BUILD
>>> + pctl = regmap_get_range(plat->map, 0);
>>> + ddrphy = regmap_get_range(plat->map, 1);
>>> + msch = syscon_get_first_range(ROCKCHIP_SYSCON_MSCH);
>>> + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
>>> +
>>> + priv->pctl = pctl;
>>> + priv->phy = ddrphy;
>>> + priv->msch = msch;
>>> + priv->grf = grf;
>>> +
>>> + ret = rockchip_get_clk(&dev_clk);
>>> + if (ret)
>>> + return ret;
>>> + priv->ddr_clk.id = CLK_DDR;
>>> + ret = clk_request(dev_clk, &priv->ddr_clk);
>>> + if (ret)
>>> + return ret;
>>> +
>>> + cru = rockchip_get_cru();
>>> + priv->cru = cru;
>>> + if (IS_ERR(priv->cru))
>>> + return PTR_ERR(priv->cru);
>>> +
>>> + ret = setup_sdram(dev);
>>> + if (ret)
>>> + return ret;
>>> +#endif
>>> +
>>> + priv->info.base = 0;
>>> + priv->info.size =
>>> + rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg[2]);
>>> +
>>> + /*
>>> + * we use the 0x00000000~0xfdffffff space since 0xff000000~0xffffffff
>>> + * is SoC register space (i.e. reserved), and 0xfe000000~0xfeffffff is
>>> + * inaccessible for some IP controller.
>>> + */
>>> + priv->info.size = min(priv->info.size, (size_t)0xfe000000);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int rk3368_dmc_get_info(struct udevice *dev, struct ram_info *info)
>>> +{
>>> + struct dram_info *priv = dev_get_priv(dev);
>>> +
>>> + *info = priv->info;
>>> + return 0;
>>> +}
>>> +
>>> +static struct ram_ops rk3368_dmc_ops = {
>>> + .get_info = rk3368_dmc_get_info,
>>> +};
>>> +
>>> +
>>> +static const struct udevice_id rk3368_dmc_ids[] = {
>>> + { .compatible = "rockchip,rk3368-dmc" },
>>> + { }
>>> +};
>>> +
>>> +U_BOOT_DRIVER(dmc_rk3368) = {
>>> + .name = "rockchip_rk3368_dmc",
>>> + .id = UCLASS_RAM,
>>> + .of_match = rk3368_dmc_ids,
>>> + .ops = &rk3368_dmc_ops,
>>> + .probe = rk3368_dmc_probe,
>>> + .priv_auto_alloc_size = sizeof(struct dram_info),
>>> + .ofdata_to_platdata = rk3368_dmc_ofdata_to_platdata,
>>> + .probe = rk3368_dmc_probe,
>>> + .priv_auto_alloc_size = sizeof(struct dram_info),
>>> + .platdata_auto_alloc_size = sizeof(struct rk3368_sdram_params),
>>> +};
>>> diff --git a/include/dt-bindings/memory/rk3368-dmc.h b/include/dt-bindings/memory/rk3368-dmc.h
>>> new file mode 100644
>>> index 0000000..b06ffde
>>> --- /dev/null
>>> +++ b/include/dt-bindings/memory/rk3368-dmc.h
>>> @@ -0,0 +1,30 @@
>>> +#ifndef DT_BINDINGS_RK3368_DMC_H
>>> +#define DT_BINDINGS_RK3368_DMC_H
>>> +
>>> +#define DMC_MSCH_CBDR 0x0
>>> +#define DMC_MSCH_CBRD 0x1
>>> +#define DMC_MSCH_CRBD 0x2
>>> +
>>> +#define DDR3_800D 0
>>> +#define DDR3_800E 1
>>> +#define DDR3_1066E 2
>>> +#define DDR3_1066F 3
>>> +#define DDR3_1066G 4
>>> +#define DDR3_1333F 5
>>> +#define DDR3_1333G 6
>>> +#define DDR3_1333H 7
>>> +#define DDR3_1333J 8
>>> +#define DDR3_1600G 9
>>> +#define DDR3_1600H 10
>>> +#define DDR3_1600J 11
>>> +#define DDR3_1600K 12
>>> +#define DDR3_1866J 13
>>> +#define DDR3_1866K 14
>>> +#define DDR3_1866L 15
>>> +#define DDR3_1866M 16
>>> +#define DDR3_2133K 17
>>> +#define DDR3_2133L 18
>>> +#define DDR3_2133M 19
>>> +#define DDR3_2133N 20
>>> +
>>> +#endif
>
>
>
^ permalink raw reply [flat|nested] 95+ messages in thread
* [U-Boot] [PATCH v3 51/66] rockchip: rk3368: dts: add DMC node in rk3368.dtsi
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (49 preceding siblings ...)
2017-07-28 19:22 ` [U-Boot] [PATCH v3 50/66] rockchip: rk3368: add DRAM controller driver with DRAM initialisation Philipp Tomsich
@ 2017-07-28 19:22 ` Philipp Tomsich
2017-08-01 9:48 ` Simon Glass
2017-07-28 19:22 ` [U-Boot] [PATCH v3 52/66] rockchip: rk3368: spl: enable SPL_FRAMEWORK in rk3368_common.h Philipp Tomsich
` (14 subsequent siblings)
65 siblings, 1 reply; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:22 UTC (permalink / raw)
To: u-boot
For full SPL support, including DRAM initialisation, we need a few
nodes from the DTS: this commit adds the DMC (DRAM controller) node,
the service_msch (memory scheduler) node and marks GRF, PMUGRF and CRU
as 'u-boot,dm-pre-reloc'. In addition to this, we also include the
dt-binding for the DMC to allow DTS files including this DTSI to refer
to the symbolic constants for the DDR3 bin and for the
memory-schedule.
Note that the DMC contains both the memory regions for the
(Designware) protocol controller as well as the DDR PHY.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---
Changes in v3: None
Changes in v2:
- removes a 'u-boot,dm-pre-reloc' from dmc-node in rk3368.dtsi
arch/arm/dts/rk3368.dtsi | 25 +++++++++++++++++++------
1 file changed, 19 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/rk3368.dtsi b/arch/arm/dts/rk3368.dtsi
index 59c20da..0dad34d 100644
--- a/arch/arm/dts/rk3368.dtsi
+++ b/arch/arm/dts/rk3368.dtsi
@@ -46,6 +46,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/memory/rk3368-dmc.h>
/ {
compatible = "rockchip,rk3368";
@@ -227,6 +228,22 @@
#clock-cells = <0>;
};
+ dmc: dmc at ff610000 {
+ compatible = "rockchip,rk3368-dmc", "syscon";
+ rockchip,cru = <&cru>;
+ rockchip,grf = <&grf>;
+ rockchip,msch = <&service_msch>;
+ reg = <0 0xff610000 0 0x400
+ 0 0xff620000 0 0x400>;
+ };
+
+ service_msch: syscon at ffac0000 {
+ u-boot,dm-pre-reloc;
+ compatible = "rockchip,rk3368-msch", "syscon";
+ reg = <0x0 0xffac0000 0x0 0x2000>;
+ status = "okay";
+ };
+
sdmmc: dwmmc at ff0c0000 {
compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff0c0000 0x0 0x4000>;
@@ -546,12 +563,6 @@
status = "disabled";
};
- dmc: dmc at ff610000 {
- u-boot,dm-pre-reloc;
- compatible = "rockchip,rk3368-dmc", "syscon";
- reg = <0x0 0xff610000 0x0 0x1000>;
- };
-
i2c0: i2c at ff650000 {
compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
reg = <0x0 0xff650000 0x0 0x1000>;
@@ -658,6 +669,7 @@
};
cru: clock-controller at ff760000 {
+ u-boot,dm-pre-reloc;
compatible = "rockchip,rk3368-cru";
reg = <0x0 0xff760000 0x0 0x1000>;
rockchip,grf = <&grf>;
@@ -666,6 +678,7 @@
};
grf: syscon at ff770000 {
+ u-boot,dm-pre-reloc;
compatible = "rockchip,rk3368-grf", "syscon";
reg = <0x0 0xff770000 0x0 0x1000>;
};
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 51/66] rockchip: rk3368: dts: add DMC node in rk3368.dtsi
2017-07-28 19:22 ` [U-Boot] [PATCH v3 51/66] rockchip: rk3368: dts: add DMC node in rk3368.dtsi Philipp Tomsich
@ 2017-08-01 9:48 ` Simon Glass
0 siblings, 0 replies; 95+ messages in thread
From: Simon Glass @ 2017-08-01 9:48 UTC (permalink / raw)
To: u-boot
On 28 July 2017 at 13:22, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> For full SPL support, including DRAM initialisation, we need a few
> nodes from the DTS: this commit adds the DMC (DRAM controller) node,
> the service_msch (memory scheduler) node and marks GRF, PMUGRF and CRU
> as 'u-boot,dm-pre-reloc'. In addition to this, we also include the
> dt-binding for the DMC to allow DTS files including this DTSI to refer
> to the symbolic constants for the DDR3 bin and for the
> memory-schedule.
>
> Note that the DMC contains both the memory regions for the
> (Designware) protocol controller as well as the DDR PHY.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>
> ---
>
> Changes in v3: None
> Changes in v2:
> - removes a 'u-boot,dm-pre-reloc' from dmc-node in rk3368.dtsi
>
> arch/arm/dts/rk3368.dtsi | 25 +++++++++++++++++++------
> 1 file changed, 19 insertions(+), 6 deletions(-)
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 95+ messages in thread
* [U-Boot] [PATCH v3 52/66] rockchip: rk3368: spl: enable SPL_FRAMEWORK in rk3368_common.h
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (50 preceding siblings ...)
2017-07-28 19:22 ` [U-Boot] [PATCH v3 51/66] rockchip: rk3368: dts: add DMC node in rk3368.dtsi Philipp Tomsich
@ 2017-07-28 19:22 ` Philipp Tomsich
2017-07-28 19:22 ` [U-Boot] [PATCH v3 53/66] rockchip: rk3368: spl: add TPL support Philipp Tomsich
` (13 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:22 UTC (permalink / raw)
To: u-boot
To build TPL and SPL stages for the RK3368, we will also need to
enable the SPL_FRAMEWORK.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Version-changes: 2
- dropped duplicate definition (this in fact dropped one of the
patches in this series) of CONFIG_SYS_SDRAM_BASE from
rk3368_common.h
Reviewed-by: Simon Glass <sjg@chromium.org>
---
Changes in v3: None
Changes in v2: None
include/configs/rk3368_common.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h
index e35f4c0..678f40d 100644
--- a/include/configs/rk3368_common.h
+++ b/include/configs/rk3368_common.h
@@ -23,6 +23,7 @@
#define COUNTER_FREQUENCY 24000000
+#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_SYS_TEXT_BASE 0x00200000
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 53/66] rockchip: rk3368: spl: add TPL support
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (51 preceding siblings ...)
2017-07-28 19:22 ` [U-Boot] [PATCH v3 52/66] rockchip: rk3368: spl: enable SPL_FRAMEWORK in rk3368_common.h Philipp Tomsich
@ 2017-07-28 19:22 ` Philipp Tomsich
2017-08-01 9:48 ` Simon Glass
2017-07-28 19:22 ` [U-Boot] [PATCH v3 54/66] rockchip: spl: make spl-boot-order code reusable (split from rk3399) Philipp Tomsich
` (12 subsequent siblings)
65 siblings, 1 reply; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:22 UTC (permalink / raw)
To: u-boot
This adds the TPL support for the RK3368, including the u-boot-tpl.lds.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---
Changes in v3:
- removes the '#define DEBUG'
- uses the syscon API to access GRF and SGRF to avoid using hard-coded
addresses
Changes in v2:
- copies the enum for the IOMUX config of the debug UART into the TPL
support code, as the various constants are otherwise private to the
pinctrl code (and we can't include pinctrl in the TPL stage due to
size constraints/dependencies)
arch/arm/mach-rockchip/Makefile | 1 +
arch/arm/mach-rockchip/rk3368-board-tpl.c | 177 +++++++++++++++++++++++++++
arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds | 13 ++
3 files changed, 191 insertions(+)
create mode 100644 arch/arm/mach-rockchip/rk3368-board-tpl.c
create mode 100644 arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 633c91e..960f40f 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -12,6 +12,7 @@ obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o save_boot_param.o
obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o save_boot_param.o
obj-tpl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-tpl.o
+obj-tpl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-tpl.o
obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o
diff --git a/arch/arm/mach-rockchip/rk3368-board-tpl.c b/arch/arm/mach-rockchip/rk3368-board-tpl.c
new file mode 100644
index 0000000..2a91007
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3368-board-tpl.c
@@ -0,0 +1,177 @@
+/*
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <debug_uart.h>
+#include <dm.h>
+#include <ram.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/bootrom.h>
+#include <asm/arch/cru_rk3368.h>
+#include <asm/arch/grf_rk3368.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/timer.h>
+#include <syscon.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * The ARMv8 generic timer uses the STIMER1 as its clock-source.
+ * Set up the STIMER1 to free-running (i.e. auto-reload) to start
+ * the generic timer counting (if we don't do this, udelay will not
+ * work and block indefinitively).
+ */
+static void secure_timer_init(void)
+{
+ struct rk_timer * const stimer1 =
+ (struct rk_timer * const)0xff830020;
+ const u32 TIMER_EN = BIT(0);
+
+ writel(~0u, &stimer1->timer_load_count0);
+ writel(~0u, &stimer1->timer_load_count1);
+ writel(TIMER_EN, &stimer1->timer_ctrl_reg);
+}
+
+/*
+ * The SPL (and also the full U-Boot stage on the RK3368) will run in
+ * secure mode (i.e. EL3) and an ATF will eventually be booted before
+ * starting up the operating system... so we can initialize the SGRF
+ * here and rely on the ATF installing the final (secure) policy
+ * later.
+ */
+static inline uintptr_t sgrf_soc_con_addr(unsigned no)
+{
+ const uintptr_t SGRF_BASE =
+ (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
+
+ return SGRF_BASE + sizeof(u32) * no;
+}
+
+static inline uintptr_t sgrf_busdmac_addr(unsigned no)
+{
+ const uintptr_t SGRF_BASE =
+ (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
+ const uintptr_t SGRF_BUSDMAC_OFFSET = 0x100;
+ const uintptr_t SGRF_BUSDMAC_BASE = SGRF_BASE + SGRF_BUSDMAC_OFFSET;
+
+ return SGRF_BUSDMAC_BASE + sizeof(u32) * no;
+}
+
+static void sgrf_init(void)
+{
+ struct rk3368_cru * const cru =
+ (struct rk3368_cru * const)rockchip_get_cru();
+ const u16 SGRF_SOC_CON_SEC = GENMASK(15, 0);
+ const u16 SGRF_BUSDMAC_CON0_SEC = BIT(2);
+ const u16 SGRF_BUSDMAC_CON1_SEC = GENMASK(15, 12);
+
+ /* Set all configurable IP to 'non secure'-mode */
+ rk_setreg(sgrf_soc_con_addr(5), SGRF_SOC_CON_SEC);
+ rk_setreg(sgrf_soc_con_addr(6), SGRF_SOC_CON_SEC);
+ rk_setreg(sgrf_soc_con_addr(7), SGRF_SOC_CON_SEC);
+
+ /*
+ * From rockchip-uboot/arch/arm/cpu/armv8/rk33xx/cpu.c
+ * Original comment: "ddr space set no secure mode"
+ */
+ rk_clrreg(sgrf_soc_con_addr(8), SGRF_SOC_CON_SEC);
+ rk_clrreg(sgrf_soc_con_addr(9), SGRF_SOC_CON_SEC);
+ rk_clrreg(sgrf_soc_con_addr(10), SGRF_SOC_CON_SEC);
+
+ /* Set 'secure dma' to 'non secure'-mode */
+ rk_setreg(sgrf_busdmac_addr(0), SGRF_BUSDMAC_CON0_SEC);
+ rk_setreg(sgrf_busdmac_addr(1), SGRF_BUSDMAC_CON1_SEC);
+
+ dsb(); /* barrier */
+
+ rk_setreg(&cru->softrst_con[1], DMA1_SRST_REQ);
+ rk_setreg(&cru->softrst_con[4], DMA2_SRST_REQ);
+
+ dsb(); /* barrier */
+ udelay(10);
+
+ rk_clrreg(&cru->softrst_con[1], DMA1_SRST_REQ);
+ rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ);
+}
+
+void board_debug_uart_init(void)
+{
+ /*
+ * N.B.: This is called before the device-model has been
+ * initialised. For this reason, we can not access
+ * the GRF address range using the syscon API.
+ */
+ struct rk3368_grf * const grf =
+ (struct rk3368_grf * const)0xff770000;
+
+ enum {
+ GPIO2D1_MASK = GENMASK(3, 2),
+ GPIO2D1_GPIO = 0,
+ GPIO2D1_UART0_SOUT = (1 << 2),
+
+ GPIO2D0_MASK = GENMASK(1, 0),
+ GPIO2D0_GPIO = 0,
+ GPIO2D0_UART0_SIN = (1 << 0),
+ };
+
+#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
+ /* Enable early UART0 on the RK3368 */
+ rk_clrsetreg(&grf->gpio2d_iomux,
+ GPIO2D0_MASK, GPIO2D0_UART0_SIN);
+ rk_clrsetreg(&grf->gpio2d_iomux,
+ GPIO2D1_MASK, GPIO2D1_UART0_SOUT);
+#endif
+}
+
+void board_init_f(ulong dummy)
+{
+ struct udevice *dev;
+ int ret;
+
+#define EARLY_UART
+#ifdef EARLY_UART
+ /*
+ * Debug UART can be used from here if required:
+ *
+ * debug_uart_init();
+ * printch('a');
+ * printhex8(0x1234);
+ * printascii("string");
+ */
+ debug_uart_init();
+ printascii("U-Boot TPL board init\n");
+#endif
+
+ ret = spl_early_init();
+ if (ret) {
+ debug("spl_early_init() failed: %d\n", ret);
+ hang();
+ }
+
+ /* Make sure the ARMv8 generic timer counts */
+ secure_timer_init();
+ /* Reset security, so we can use DMA in the MMC drivers */
+ sgrf_init();
+
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ debug("DRAM init failed: %d\n", ret);
+ return;
+ }
+}
+
+void board_return_to_bootrom(void)
+{
+ back_to_bootrom();
+}
+
+u32 spl_boot_device(void)
+{
+ return BOOT_DEVICE_BOOTROM;
+}
+
diff --git a/arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds b/arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds
new file mode 100644
index 0000000..cc59844
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds
@@ -0,0 +1,13 @@
+/*
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#undef CONFIG_SPL_TEXT_BASE
+#define CONFIG_SPL_TEXT_BASE CONFIG_TPL_TEXT_BASE
+
+#undef CONFIG_SPL_MAX_SIZE
+#define CONFIG_SPL_MAX_SIZE CONFIG_TPL_MAX_SIZE
+
+#include "../../cpu/armv8/u-boot-spl.lds"
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 53/66] rockchip: rk3368: spl: add TPL support
2017-07-28 19:22 ` [U-Boot] [PATCH v3 53/66] rockchip: rk3368: spl: add TPL support Philipp Tomsich
@ 2017-08-01 9:48 ` Simon Glass
0 siblings, 0 replies; 95+ messages in thread
From: Simon Glass @ 2017-08-01 9:48 UTC (permalink / raw)
To: u-boot
On 28 July 2017 at 13:22, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> This adds the TPL support for the RK3368, including the u-boot-tpl.lds.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>
> ---
>
> Changes in v3:
> - removes the '#define DEBUG'
> - uses the syscon API to access GRF and SGRF to avoid using hard-coded
> addresses
>
> Changes in v2:
> - copies the enum for the IOMUX config of the debug UART into the TPL
> support code, as the various constants are otherwise private to the
> pinctrl code (and we can't include pinctrl in the TPL stage due to
> size constraints/dependencies)
>
> arch/arm/mach-rockchip/Makefile | 1 +
> arch/arm/mach-rockchip/rk3368-board-tpl.c | 177 +++++++++++++++++++++++++++
> arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds | 13 ++
> 3 files changed, 191 insertions(+)
> create mode 100644 arch/arm/mach-rockchip/rk3368-board-tpl.c
> create mode 100644 arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds
Reviewed-by: Simon Glass <sjg@chromium.org>
We still have the timer address, but it looks like you are trying to
drop that in the other series.
^ permalink raw reply [flat|nested] 95+ messages in thread
* [U-Boot] [PATCH v3 54/66] rockchip: spl: make spl-boot-order code reusable (split from rk3399)
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (52 preceding siblings ...)
2017-07-28 19:22 ` [U-Boot] [PATCH v3 53/66] rockchip: rk3368: spl: add TPL support Philipp Tomsich
@ 2017-07-28 19:22 ` Philipp Tomsich
2017-07-28 19:22 ` [U-Boot] [PATCH v3 55/66] rockchip: rk3368: spl: add SPL support Philipp Tomsich
` (11 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:22 UTC (permalink / raw)
To: u-boot
In order to reuse the support for the u-boot,spl-boot-order property
from the rk3399, we split it into a reusable module that can be
included by the SPL code for any of our boards.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
Changes in v3: None
Changes in v2:
- added in v2
arch/arm/mach-rockchip/Makefile | 2 +-
arch/arm/mach-rockchip/rk3399-board-spl.c | 104 ----------------------------
arch/arm/mach-rockchip/spl-boot-order.c | 108 ++++++++++++++++++++++++++++++
3 files changed, 109 insertions(+), 105 deletions(-)
create mode 100644 arch/arm/mach-rockchip/spl-boot-order.c
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 960f40f..c5d17f9 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -19,7 +19,7 @@ obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o
obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o
obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o
obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o
-obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o
+obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o spl-boot-order.o
ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o
diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c
index 710f7fe..a13b717 100644
--- a/arch/arm/mach-rockchip/rk3399-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3399-board-spl.c
@@ -8,9 +8,6 @@
#include <debug_uart.h>
#include <dm.h>
#include <fdtdec.h>
-#include <led.h>
-#include <malloc.h>
-#include <mmc.h>
#include <ram.h>
#include <spl.h>
#include <asm/gpio.h>
@@ -21,111 +18,10 @@
#include <asm/arch/sdram.h>
#include <asm/arch/timer.h>
#include <dm/pinctrl.h>
-#include <dm/root.h>
-#include <dm/test.h>
-#include <dm/util.h>
#include <power/regulator.h>
DECLARE_GLOBAL_DATA_PTR;
-#if CONFIG_IS_ENABLED(OF_CONTROL)
-static int spl_node_to_boot_device(int node)
-{
- struct udevice *parent;
-
- /*
- * This should eventually move into the SPL code, once SPL becomes
- * aware of the block-device layer. Until then (and to avoid unneeded
- * delays in getting this feature out, it lives at the board-level).
- */
- if (!uclass_get_device_by_of_offset(UCLASS_MMC, node, &parent)) {
- struct udevice *dev;
- struct blk_desc *desc = NULL;
-
- for (device_find_first_child(parent, &dev);
- dev;
- device_find_next_child(&dev)) {
- if (device_get_uclass_id(dev) == UCLASS_BLK) {
- desc = dev_get_uclass_platdata(dev);
- break;
- }
- }
-
- if (!desc)
- return -ENOENT;
-
- switch (desc->devnum) {
- case 0:
- return BOOT_DEVICE_MMC1;
- case 1:
- return BOOT_DEVICE_MMC2;
- default:
- return -ENOSYS;
- }
- }
-
- /*
- * SPL doesn't differentiate SPI flashes, so we keep the detection
- * brief and inaccurate... hopefully, the common SPL layer can be
- * extended with awareness of the BLK layer (and matching OF_CONTROL)
- * soon.
- */
- if (!uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node, &parent))
- return BOOT_DEVICE_SPI;
-
- return -1;
-}
-
-void board_boot_order(u32 *spl_boot_list)
-{
- const void *blob = gd->fdt_blob;
- int chosen_node = fdt_path_offset(blob, "/chosen");
- int idx = 0;
- int elem;
- int boot_device;
- int node;
- const char *conf;
-
- if (chosen_node < 0) {
- debug("%s: /chosen not found, using spl_boot_device()\n",
- __func__);
- spl_boot_list[0] = spl_boot_device();
- return;
- }
-
- for (elem = 0;
- (conf = fdt_stringlist_get(blob, chosen_node,
- "u-boot,spl-boot-order", elem, NULL));
- elem++) {
- /* First check if the list element is an alias */
- const char *alias = fdt_get_alias(blob, conf);
- if (alias)
- conf = alias;
-
- /* Try to resolve the config item (or alias) as a path */
- node = fdt_path_offset(blob, conf);
- if (node < 0) {
- debug("%s: could not find %s in FDT", __func__, conf);
- continue;
- }
-
- /* Try to map this back onto SPL boot devices */
- boot_device = spl_node_to_boot_device(node);
- if (boot_device < 0) {
- debug("%s: could not map node @%x to a boot-device\n",
- __func__, node);
- continue;
- }
-
- spl_boot_list[idx++] = boot_device;
- }
-
- /* If we had no matches, fall back to spl_boot_device */
- if (idx == 0)
- spl_boot_list[0] = spl_boot_device();
-}
-#endif
-
u32 spl_boot_device(void)
{
return BOOT_DEVICE_MMC1;
diff --git a/arch/arm/mach-rockchip/spl-boot-order.c b/arch/arm/mach-rockchip/spl-boot-order.c
new file mode 100644
index 0000000..4f78c72
--- /dev/null
+++ b/arch/arm/mach-rockchip/spl-boot-order.c
@@ -0,0 +1,108 @@
+/*
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <mmc.h>
+#include <spl.h>
+
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+static int spl_node_to_boot_device(int node)
+{
+ struct udevice *parent;
+
+ /*
+ * This should eventually move into the SPL code, once SPL becomes
+ * aware of the block-device layer. Until then (and to avoid unneeded
+ * delays in getting this feature out, it lives at the board-level).
+ */
+ if (!uclass_get_device_by_of_offset(UCLASS_MMC, node, &parent)) {
+ struct udevice *dev;
+ struct blk_desc *desc = NULL;
+
+ for (device_find_first_child(parent, &dev);
+ dev;
+ device_find_next_child(&dev)) {
+ if (device_get_uclass_id(dev) == UCLASS_BLK) {
+ desc = dev_get_uclass_platdata(dev);
+ break;
+ }
+ }
+
+ if (!desc)
+ return -ENOENT;
+
+ switch (desc->devnum) {
+ case 0:
+ return BOOT_DEVICE_MMC1;
+ case 1:
+ return BOOT_DEVICE_MMC2;
+ default:
+ return -ENOSYS;
+ }
+ }
+
+ /*
+ * SPL doesn't differentiate SPI flashes, so we keep the detection
+ * brief and inaccurate... hopefully, the common SPL layer can be
+ * extended with awareness of the BLK layer (and matching OF_CONTROL)
+ * soon.
+ */
+ if (!uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node, &parent))
+ return BOOT_DEVICE_SPI;
+
+ return -1;
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+ const void *blob = gd->fdt_blob;
+ int chosen_node = fdt_path_offset(blob, "/chosen");
+ int idx = 0;
+ int elem;
+ int boot_device;
+ int node;
+ const char *conf;
+
+ if (chosen_node < 0) {
+ debug("%s: /chosen not found, using spl_boot_device()\n",
+ __func__);
+ spl_boot_list[0] = spl_boot_device();
+ return;
+ }
+
+ for (elem = 0;
+ (conf = fdt_stringlist_get(blob, chosen_node,
+ "u-boot,spl-boot-order", elem, NULL));
+ elem++) {
+ /* First check if the list element is an alias */
+ const char *alias = fdt_get_alias(blob, conf);
+ if (alias)
+ conf = alias;
+
+ /* Try to resolve the config item (or alias) as a path */
+ node = fdt_path_offset(blob, conf);
+ if (node < 0) {
+ debug("%s: could not find %s in FDT", __func__, conf);
+ continue;
+ }
+
+ /* Try to map this back onto SPL boot devices */
+ boot_device = spl_node_to_boot_device(node);
+ if (boot_device < 0) {
+ debug("%s: could not map node @%x to a boot-device\n",
+ __func__, node);
+ continue;
+ }
+
+ spl_boot_list[idx++] = boot_device;
+ }
+
+ /* If we had no matches, fall back to spl_boot_device */
+ if (idx == 0)
+ spl_boot_list[0] = spl_boot_device();
+}
+#endif
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 55/66] rockchip: rk3368: spl: add SPL support
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (53 preceding siblings ...)
2017-07-28 19:22 ` [U-Boot] [PATCH v3 54/66] rockchip: spl: make spl-boot-order code reusable (split from rk3399) Philipp Tomsich
@ 2017-07-28 19:22 ` Philipp Tomsich
2017-07-28 19:22 ` [U-Boot] [PATCH v3 56/66] rockchip: rk3368: spl: mark SPL and TPL as supported for ROCKCHIP_RK3368 Philipp Tomsich
` (10 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:22 UTC (permalink / raw)
To: u-boot
Adds SPL support for the RK3368 (assuming that our TPL stage has
initialised DRAM and set up the memory firewall).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
Changes in v3: None
Changes in v2:
- reuses the support for configuring the boot order using the
u-boot,spl-boot-order property
- drops the initialisation of the debug_uart
- adds pinctrl-configuration for the preloader UART
arch/arm/mach-rockchip/Makefile | 2 +-
arch/arm/mach-rockchip/rk3368-board-spl.c | 98 +++++++++++++++++++++++++++++++
2 files changed, 99 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/mach-rockchip/rk3368-board-spl.c
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index c5d17f9..c3ed862 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -18,7 +18,7 @@ obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o
obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o
obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o
-obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o
+obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o spl-boot-order.o
obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o spl-boot-order.o
ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
diff --git a/arch/arm/mach-rockchip/rk3368-board-spl.c b/arch/arm/mach-rockchip/rk3368-board-spl.c
new file mode 100644
index 0000000..691db41
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3368-board-spl.c
@@ -0,0 +1,98 @@
+/*
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <ram.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/cru_rk3368.h>
+#include <asm/arch/grf_rk3368.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/periph.h>
+#include <asm/arch/timer.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * The ARMv8 generic timer uses the STIMER1 as its clock-source.
+ * Set up the STIMER1 to free-running (i.e. auto-reload) to start
+ * the generic timer counting (if we don't do this, udelay will not
+ * work and block indefinitively).
+ */
+static void secure_timer_init(void)
+{
+ struct rk_timer * const stimer1 =
+ (struct rk_timer * const)0xff830020;
+ const u32 TIMER_EN = BIT(0);
+
+ writel(~0u, &stimer1->timer_load_count0);
+ writel(~0u, &stimer1->timer_load_count1);
+ writel(TIMER_EN, &stimer1->timer_ctrl_reg);
+}
+
+void board_debug_uart_init(void)
+{
+}
+
+void board_init_f(ulong dummy)
+{
+ struct udevice *pinctrl;
+ struct udevice *dev;
+ int ret;
+
+ ret = spl_early_init();
+ if (ret) {
+ debug("spl_early_init() failed: %d\n", ret);
+ hang();
+ }
+
+ /* Make sure the ARMv8 generic timer counts */
+ secure_timer_init();
+
+ /* Set up our preloader console */
+ ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
+ if (ret) {
+ error("%s: pinctrl init failed: %d\n", __func__, ret);
+ hang();
+ }
+
+ ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART0);
+ if (ret) {
+ error("%s: failed to set up console UART\n", __func__);
+ hang();
+ }
+
+ preloader_console_init();
+
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ debug("DRAM init failed: %d\n", ret);
+ return;
+ }
+}
+
+u32 spl_boot_mode(const u32 boot_device)
+{
+ return MMCSD_MODE_RAW;
+}
+
+u32 spl_boot_device(void)
+{
+ return BOOT_DEVICE_MMC1;
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ /* Just empty function now - can't decide what to choose */
+ debug("%s: %s\n", __func__, name);
+
+ return 0;
+}
+#endif
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 56/66] rockchip: rk3368: spl: mark SPL and TPL as supported for ROCKCHIP_RK3368
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (54 preceding siblings ...)
2017-07-28 19:22 ` [U-Boot] [PATCH v3 55/66] rockchip: rk3368: spl: add SPL support Philipp Tomsich
@ 2017-07-28 19:22 ` Philipp Tomsich
2017-08-02 12:47 ` Andy Yan
2017-07-28 19:22 ` [U-Boot] [PATCH v3 57/66] rockchip: spi: enable support for the rk_spi driver for the RK3368 Philipp Tomsich
` (9 subsequent siblings)
65 siblings, 1 reply; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:22 UTC (permalink / raw)
To: u-boot
With SPL and TPL support for the RK3368 in place, mark SPL and TPL as
supported from Kconfig for the RK3368. As this is primarily tested on
the RK3368-uQ7, we'll leave it to board's individual defconfig to
enable.
Also enable DEBUG_UART_BOARD_INIT for the RK3368, so we get output
during the early boot-up, as we turn on TPL and SPL.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
Changes in v3: None
Changes in v2: None
arch/arm/mach-rockchip/Kconfig | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 8a89b51..8406e33 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -67,6 +67,13 @@ config ROCKCHIP_RK3328
config ROCKCHIP_RK3368
bool "Support Rockchip RK3368"
select ARM64
+ select SUPPORT_SPL
+ select SUPPORT_TPL
+ select SPL_SEPARATE_BSS
+ select SPL_SERIAL_SUPPORT
+ select TPL_SERIAL_SUPPORT
+ select ENABLE_ARM_SOC_BOOT0_HOOK
+ select DEBUG_UART_BOARD_INIT
select SYS_NS16550
help
The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 56/66] rockchip: rk3368: spl: mark SPL and TPL as supported for ROCKCHIP_RK3368
2017-07-28 19:22 ` [U-Boot] [PATCH v3 56/66] rockchip: rk3368: spl: mark SPL and TPL as supported for ROCKCHIP_RK3368 Philipp Tomsich
@ 2017-08-02 12:47 ` Andy Yan
2017-08-02 12:59 ` Dr. Philipp Tomsich
0 siblings, 1 reply; 95+ messages in thread
From: Andy Yan @ 2017-08-02 12:47 UTC (permalink / raw)
To: u-boot
Hi Philipp:
2017-07-29 3:22 GMT+08:00 Philipp Tomsich <
philipp.tomsich@theobroma-systems.com>:
> With SPL and TPL support for the RK3368 in place, mark SPL and TPL as
> supported from Kconfig for the RK3368. As this is primarily tested on
> the RK3368-uQ7, we'll leave it to board's individual defconfig to
> enable.
>
> Also enable DEBUG_UART_BOARD_INIT for the RK3368, so we get output
> during the early boot-up, as we turn on TPL and SPL.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
> arch/arm/mach-rockchip/Kconfig | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/
> Kconfig
> index 8a89b51..8406e33 100644
> --- a/arch/arm/mach-rockchip/Kconfig
> +++ b/arch/arm/mach-rockchip/Kconfig
> @@ -67,6 +67,13 @@ config ROCKCHIP_RK3328
> config ROCKCHIP_RK3368
> bool "Support Rockchip RK3368"
> select ARM64
> + select SUPPORT_SPL
> + select SUPPORT_TPL
> + select SPL_SEPARATE_BSS
> + select SPL_SERIAL_SUPPORT
> + select TPL_SERIAL_SUPPORT
>
These should depends on TPL/SPL, or we will get compile warnings like
bellow on non-SPL/TPL boards(px5 evb):
(ROCKCHIP_RK3368 && ROCKCHIP_RK3399 && X86_RUN_64BIT) selects
SPL_SEPARATE_BSS which has unmet direct dependencies (SPL)
+ select ENABLE_ARM_SOC_BOOT0_HOOK
> + select DEBUG_UART_BOARD_INIT
> select SYS_NS16550
> help
> The Rockchip RK3368 is a ARM-based SoC with a octa-core
> (organised
> --
> 2.1.4
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot
>
^ permalink raw reply [flat|nested] 95+ messages in thread
* [U-Boot] [PATCH v3 56/66] rockchip: rk3368: spl: mark SPL and TPL as supported for ROCKCHIP_RK3368
2017-08-02 12:47 ` Andy Yan
@ 2017-08-02 12:59 ` Dr. Philipp Tomsich
0 siblings, 0 replies; 95+ messages in thread
From: Dr. Philipp Tomsich @ 2017-08-02 12:59 UTC (permalink / raw)
To: u-boot
Looks like SPL_SEPARATE_BSS is special.
Guess, I’ll need to figure out how to best deal with that one (or fall back to defining it via defconfig until we can enable TPL/SPL for all RK3368 board).
I wonder how an implies would behave here...
> On 02 Aug 2017, at 14:47, Andy Yan <andyshrk@gmail.com> wrote:
>
> Hi Philipp:
>
> 2017-07-29 3:22 GMT+08:00 Philipp Tomsich <philipp.tomsich at theobroma-systems.com <mailto:philipp.tomsich@theobroma-systems.com>>:
> With SPL and TPL support for the RK3368 in place, mark SPL and TPL as
> supported from Kconfig for the RK3368. As this is primarily tested on
> the RK3368-uQ7, we'll leave it to board's individual defconfig to
> enable.
>
> Also enable DEBUG_UART_BOARD_INIT for the RK3368, so we get output
> during the early boot-up, as we turn on TPL and SPL.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich at theobroma-systems.com <mailto:philipp.tomsich@theobroma-systems.com>>
>
> Reviewed-by: Simon Glass <sjg at chromium.org <mailto:sjg@chromium.org>>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
> arch/arm/mach-rockchip/Kconfig | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
> index 8a89b51..8406e33 100644
> --- a/arch/arm/mach-rockchip/Kconfig
> +++ b/arch/arm/mach-rockchip/Kconfig
> @@ -67,6 +67,13 @@ config ROCKCHIP_RK3328
> config ROCKCHIP_RK3368
> bool "Support Rockchip RK3368"
> select ARM64
> + select SUPPORT_SPL
> + select SUPPORT_TPL
> + select SPL_SEPARATE_BSS
> + select SPL_SERIAL_SUPPORT
> + select TPL_SERIAL_SUPPORT
>
>
> These should depends on TPL/SPL, or we will get compile warnings like bellow on non-SPL/TPL boards(px5 evb):
> (ROCKCHIP_RK3368 && ROCKCHIP_RK3399 && X86_RUN_64BIT) selects SPL_SEPARATE_BSS which has unmet direct dependencies (SPL)
>
> + select ENABLE_ARM_SOC_BOOT0_HOOK
> + select DEBUG_UART_BOARD_INIT
> select SYS_NS16550
> help
> The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
> --
> 2.1.4
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de <mailto:U-Boot@lists.denx.de>
> https://lists.denx.de/listinfo/u-boot <https://lists.denx.de/listinfo/u-boot>
>
^ permalink raw reply [flat|nested] 95+ messages in thread
* [U-Boot] [PATCH v3 57/66] rockchip: spi: enable support for the rk_spi driver for the RK3368
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (55 preceding siblings ...)
2017-07-28 19:22 ` [U-Boot] [PATCH v3 56/66] rockchip: rk3368: spl: mark SPL and TPL as supported for ROCKCHIP_RK3368 Philipp Tomsich
@ 2017-07-28 19:22 ` Philipp Tomsich
2017-07-28 19:22 ` [U-Boot] [PATCH v3 58/66] rockchip: board: lion-rk3368: add support for the RK3368-uQ7 Philipp Tomsich
` (8 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:22 UTC (permalink / raw)
To: u-boot
For the RK3368, we can reuse the SPI driver (although we'll have to
eventually investigate whether it can be merged with the
designware_spi.c driver) also used for the RK3288 and RK3399.
This adds the necessary compatible string to support the RK3368.
Note that the assumption that GPLL will be clocked at 594MHz is not
true for the RK3368, but this will not lead to incorrect functioning
(just to a lower-than-expected SPI operating frequency): this has been
documented in the driver, so it doesn't cause any headaches when
someone next needs to touch the clock code of this driver.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Version-changes: 2
- added in this version
Reviewed-by: Simon Glass <sjg@chromium.org>
---
Changes in v3: None
Changes in v2: None
drivers/spi/rk_spi.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
index 7921ea0..c70d636 100644
--- a/drivers/spi/rk_spi.c
+++ b/drivers/spi/rk_spi.c
@@ -210,6 +210,14 @@ static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
static int rockchip_spi_calc_modclk(ulong max_freq)
{
+ /*
+ * While this is not strictly correct for the RK3368, as the
+ * GPLL will be 576MHz, things will still work, as the
+ * clk_set_rate(...) implementation in our clock-driver will
+ * chose the next closest rate not exceeding what we request
+ * based on the output of this function.
+ */
+
unsigned div;
const unsigned long gpll_hz = 594000000UL;
@@ -443,6 +451,7 @@ static const struct dm_spi_ops rockchip_spi_ops = {
static const struct udevice_id rockchip_spi_ids[] = {
{ .compatible = "rockchip,rk3288-spi" },
+ { .compatible = "rockchip,rk3368-spi" },
{ .compatible = "rockchip,rk3399-spi" },
{ }
};
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 58/66] rockchip: board: lion-rk3368: add support for the RK3368-uQ7
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (56 preceding siblings ...)
2017-07-28 19:22 ` [U-Boot] [PATCH v3 57/66] rockchip: spi: enable support for the rk_spi driver for the RK3368 Philipp Tomsich
@ 2017-07-28 19:22 ` Philipp Tomsich
2017-07-28 19:22 ` [U-Boot] [PATCH v3 59/66] spl: Kconfig: migrate $(SPL_TPL_)LDSCRIPT to Kconfig Philipp Tomsich
` (7 subsequent siblings)
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:22 UTC (permalink / raw)
To: u-boot
The RK3368-uQ7 (codenamed 'Lion') is a micro-Qseven (40mm x 70mm,
MXM-230 edge connector compatible with the Qseven specification)
form-factor system-on-module based on the octo-core Rockchip RK3368.
It is designed, supported and manufactured by Theobroma Systems.
It provides the following features:
- 8x Cortex-A53 (in 2 clusters of 4 cores each)
- (on-module) up to 4GB of DDR3 memory
- (on-module) SPI-NOR flash
- (on-module) eMMC
- Gigabit Ethernet (with an on-module KSZ9031 PHY)
- USB
- HDMI
- MIPI-DSI/single-channel LVDS (muxed on the 'LVDS-A' pin-group)
- various 'slow' interfaces (e.g. UART, SPI, I2C, I2S, ...)
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
Changes in v3:
- (after rebase) update defconfig
- (after rebase and defconfig update) lion_rk3368.h: remove
CONFIG_ENV_IS_NOWHERE
- moves remaining 'u-boot,dm-pre-reloc' to -u-boot.dtsi
- marks sgrf-node as pre-reloc
- defines SPL_LDSCRIPT and TPL_LDSCRIPT via defconfig
Changes in v2:
- marks pinctrl-node as 'u-boot,dm-pre-reloc' to ensure MMC2 (eMMC)
works in the SPL stage
- makes uart0 as 'u-boot,dm-pre-reloc' to allow initialising the
preloader console (instead of relying solely on the debug UART)
- adds support for SPI1 (and the on-module SPI flash)
- splits the a 'u-boot.dtsi' off the DTS file
- updates the defconfig for SPI and SPI flash support
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3368-lion-u-boot.dtsi | 88 ++++++++++
arch/arm/dts/rk3368-lion.dts | 195 +++++++++++++++++++++
arch/arm/dts/rk3368.dtsi | 4 -
arch/arm/mach-rockchip/rk3368/Kconfig | 21 +++
board/theobroma-systems/lion_rk3368/Kconfig | 15 ++
board/theobroma-systems/lion_rk3368/MAINTAINERS | 10 ++
board/theobroma-systems/lion_rk3368/Makefile | 7 +
board/theobroma-systems/lion_rk3368/README | 60 +++++++
.../theobroma-systems/lion_rk3368/fit_spl_atf.its | 51 ++++++
board/theobroma-systems/lion_rk3368/lion_rk3368.c | 25 +++
configs/lion-rk3368_defconfig | 93 ++++++++++
include/configs/lion_rk3368.h | 18 ++
13 files changed, 584 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/dts/rk3368-lion-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3368-lion.dts
create mode 100644 board/theobroma-systems/lion_rk3368/Kconfig
create mode 100644 board/theobroma-systems/lion_rk3368/MAINTAINERS
create mode 100644 board/theobroma-systems/lion_rk3368/Makefile
create mode 100644 board/theobroma-systems/lion_rk3368/README
create mode 100644 board/theobroma-systems/lion_rk3368/fit_spl_atf.its
create mode 100644 board/theobroma-systems/lion_rk3368/lion_rk3368.c
create mode 100644 configs/lion-rk3368_defconfig
create mode 100644 include/configs/lion_rk3368.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 132fa69..41cd9d0 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -42,6 +42,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-veyron-mickey.dtb \
rk3288-veyron-minnie.dtb \
rk3328-evb.dtb \
+ rk3368-lion.dtb \
rk3368-sheep.dtb \
rk3368-geekbox.dtb \
rk3368-px5-evb.dtb \
diff --git a/arch/arm/dts/rk3368-lion-u-boot.dtsi b/arch/arm/dts/rk3368-lion-u-boot.dtsi
new file mode 100644
index 0000000..2053fb1
--- /dev/null
+++ b/arch/arm/dts/rk3368-lion-u-boot.dtsi
@@ -0,0 +1,88 @@
+/*
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/ {
+ config {
+ u-boot,spl-payload-offset = <0x40000>; /* @ 256KB */
+ u-boot,mmc-env-offset = <0x4000>; /* @ 16KB */
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ u-boot,spl-boot-order = &emmc, &sdmmc;
+ };
+
+};
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
+
+&service_msch {
+ u-boot,dm-pre-reloc;
+};
+
+&dmc {
+ u-boot,dm-pre-reloc;
+
+ /*
+ * Validation of throughput using SPEC2000 shows the following
+ * relative performance for the different memory schedules:
+ * - CBDR: 30.1
+ * - CBRD: 29.8
+ * - CRBD: 29.9
+ * Note that the best performance for any given application workload
+ * may vary from the default configured here (e.g. 164.gzip is fastest
+ * with CBRD, whereas 252.eon and 186.crafty are fastest with CRBD).
+ *
+ * See doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt for
+ * details on the 'rockchip,memory-schedule' property and how it
+ * affects the physical-address to device-address mapping.
+ */
+ rockchip,memory-schedule = <DMC_MSCH_CBDR>;
+ rockchip,ddr-frequency = <800000000>;
+ rockchip,ddr-speed-bin = <DDR3_1600K>;
+
+ status = "okay";
+};
+
+&pmugrf {
+ u-boot,dm-pre-reloc;
+};
+
+&sgrf {
+ u-boot,dm-pre-reloc;
+};
+
+&cru {
+ u-boot,dm-pre-reloc;
+};
+
+&grf {
+ u-boot,dm-pre-reloc;
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+};
+
+&emmc {
+ u-boot,dm-pre-reloc;
+};
+
+&sdmmc {
+ u-boot,dm-pre-reloc;
+};
+
+&spi1 {
+ u-boot,dm-pre-reloc;
+
+ spiflash: w25q32dw at 0 {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+
diff --git a/arch/arm/dts/rk3368-lion.dts b/arch/arm/dts/rk3368-lion.dts
new file mode 100644
index 0000000..850db50
--- /dev/null
+++ b/arch/arm/dts/rk3368-lion.dts
@@ -0,0 +1,195 @@
+/*
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/dts-v1/;
+#include "rk3368.dtsi"
+#include "rk3368-lion-u-boot.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Theobroma Systems RK3368-uQ7 SoM";
+ compatible = "tsd,rk3368-uq7", "tsd,lion", "rockchip,rk3368";
+
+ aliases {
+ mmc0 = &emmc;
+ mmc1 = &sdmmc;
+ };
+
+ memory at 0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ ext_gmac: gmac-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "ext_gmac";
+ #clock-cells = <0>;
+ };
+
+ vcc_sys: vcc-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&emmc {
+ status = "okay";
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ clock-frequency = <150000000>;
+ disable-wp;
+ keep-power-in-suspend;
+ non-removable;
+ num-slots = <1>;
+ vmmc-supply = <&vcc33_io>;
+ vqmmc-supply = <&vcc18_io>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>;
+};
+
+&sdmmc {
+ status = "okay";
+};
+
+&gmac {
+ status = "okay";
+ phy-supply = <&vcc33_io>;
+ phy-mode = "rgmii";
+ clock_in_out = "input";
+ snps,reset-gpio = <&gpio3 11 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <2 10000 50000>;
+ assigned-clocks = <&cru SCLK_MAC>;
+ assigned-clock-parents = <&ext_gmac>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ tx_delay = <0x10>;
+ rx_delay = <0x10>;
+};
+
+&i2c0 {
+ status = "okay";
+
+ rk808: pmic at 1b {
+ compatible = "rockchip,rk808";
+ reg = <0x1b>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+ rockchip,system-power-controller;
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
+ vcc3-supply = <&vcc_sys>;
+ vcc4-supply = <&vcc_sys>;
+ vcc6-supply = <&vcc_sys>;
+ vcc7-supply = <&vcc_sys>;
+ vcc8-supply = <&vcc_sys>;
+ vcc9-supply = <&vcc_sys>;
+ vcc10-supply = <&vcc_sys>;
+ vcc11-supply = <&vcc_sys>;
+ vcc12-supply = <&vcc_sys>;
+ clock-output-names = "xin32k", "rk808-clkout2";
+ #clock-cells = <1>;
+
+ regulators {
+ vdd_cpu: DCDC_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vdd_cpu";
+ };
+
+ vdd_log: DCDC_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vdd_log";
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc_ddr";
+ };
+
+ vcc33_io: DCDC_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc33_io";
+ };
+
+ vcc33_video: LDO_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc33_video";
+ };
+
+ vdd10_pll: LDO_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-name = "vdd10_pll";
+ };
+
+ vcc18_io: LDO_REG4 {
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc18_io";
+ };
+
+ vdd10_video: LDO_REG6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-name = "vdd10_video";
+ };
+
+ vcc18_video: LDO_REG8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc18_video";
+ };
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&spi1 {
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ spiflash: w25q32dw at 0 {
+ compatible = "spi-flash";
+ reg = <0>;
+ spi-max-frequency = <49500000>;
+ spi-cpol;
+ spi-cpha;
+ };
+};
diff --git a/arch/arm/dts/rk3368.dtsi b/arch/arm/dts/rk3368.dtsi
index 0dad34d..22fb7e7 100644
--- a/arch/arm/dts/rk3368.dtsi
+++ b/arch/arm/dts/rk3368.dtsi
@@ -238,7 +238,6 @@
};
service_msch: syscon at ffac0000 {
- u-boot,dm-pre-reloc;
compatible = "rockchip,rk3368-msch", "syscon";
reg = <0x0 0xffac0000 0x0 0x2000>;
status = "okay";
@@ -658,7 +657,6 @@
};
pmugrf: syscon at ff738000 {
- u-boot,dm-pre-reloc;
compatible = "rockchip,rk3368-pmugrf", "syscon";
reg = <0x0 0xff738000 0x0 0x1000>;
};
@@ -669,7 +667,6 @@
};
cru: clock-controller at ff760000 {
- u-boot,dm-pre-reloc;
compatible = "rockchip,rk3368-cru";
reg = <0x0 0xff760000 0x0 0x1000>;
rockchip,grf = <&grf>;
@@ -678,7 +675,6 @@
};
grf: syscon at ff770000 {
- u-boot,dm-pre-reloc;
compatible = "rockchip,rk3368-grf", "syscon";
reg = <0x0 0xff770000 0x0 0x1000>;
};
diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig
index 6d32068..f8189f1 100644
--- a/arch/arm/mach-rockchip/rk3368/Kconfig
+++ b/arch/arm/mach-rockchip/rk3368/Kconfig
@@ -3,6 +3,26 @@ if ROCKCHIP_RK3368
choice
prompt "RK3368 board"
+config TARGET_LION_RK3368
+ bool "Theobroma Systems RK3368-uQ7 (Lion) module"
+ help
+ The RK3368-uQ7 is a micro-Qseven form-factor (40mm x 70mm,
+ MXM-230 connector) system-on-module designed by Theobroma
+ Systems for industrial applications.
+
+ It provides the following features:
+ - 8x Cortex-A53 (in 2 clusters of 4 cores each)
+ - (on-module) up to 4GB of DDR3 memory
+ - (on-module) SPI-NOR flash
+ - (on-module) eMMC
+ - Gigabit Ethernet (with an on-module KSZ9031 PHY)
+ - USB
+ - HDMI
+ - MIPI-DSI/single-channel LVDS (muxed on the 'LVDS-A' pin-group)
+ - various 'slow' interfaces (e.g. UART, SPI, I2C, I2S, ...)
+ - on-module STM32 providing CAN, RTC and fan-control
+ - (optional on-module) EAL4+-certified security module
+
config TARGET_SHEEP
bool "Sheep board"
help
@@ -25,6 +45,7 @@ endchoice
config SYS_SOC
default "rockchip"
+source "board/theobroma-systems/lion_rk3368/Kconfig"
source "board/rockchip/sheep_rk3368/Kconfig"
source "board/geekbuying/geekbox/Kconfig"
source "board/rockchip/evb_px5/Kconfig"
diff --git a/board/theobroma-systems/lion_rk3368/Kconfig b/board/theobroma-systems/lion_rk3368/Kconfig
new file mode 100644
index 0000000..d7aa487
--- /dev/null
+++ b/board/theobroma-systems/lion_rk3368/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_LION_RK3368
+
+config SYS_BOARD
+ default "lion_rk3368"
+
+config SYS_VENDOR
+ default "theobroma-systems"
+
+config SYS_CONFIG_NAME
+ default "lion_rk3368"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+
+endif
diff --git a/board/theobroma-systems/lion_rk3368/MAINTAINERS b/board/theobroma-systems/lion_rk3368/MAINTAINERS
new file mode 100644
index 0000000..857f784
--- /dev/null
+++ b/board/theobroma-systems/lion_rk3368/MAINTAINERS
@@ -0,0 +1,10 @@
+LION-RK3368 (RK3368-uQ7 system-on-module)
+M: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
+M: Klaus Goger <klaus.goger@theobroma-systems.com>
+S: Maintained
+F: board/theobroma-systems/lion_rk3368
+F: include/configs/lion_rk3368.h
+F: arch/arm/dts/rk3368-lion.dts
+F: configs/lion-rk3368_defconfig
+W: https://www.theobroma-systems.com/rk3368-uq7/tech-specs
+T: git git://git.theobroma-systems.com/lion-u-boot.git
diff --git a/board/theobroma-systems/lion_rk3368/Makefile b/board/theobroma-systems/lion_rk3368/Makefile
new file mode 100644
index 0000000..f13a20b
--- /dev/null
+++ b/board/theobroma-systems/lion_rk3368/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += lion_rk3368.o
diff --git a/board/theobroma-systems/lion_rk3368/README b/board/theobroma-systems/lion_rk3368/README
new file mode 100644
index 0000000..47304fc
--- /dev/null
+++ b/board/theobroma-systems/lion_rk3368/README
@@ -0,0 +1,60 @@
+Here is the step-by-step to boot to U-Boot on RK3368-uQ7
+
+Get the Source and build ATF
+============================
+
+ > git clone git://git.theobroma-systems.com/arm-trusted-firmware.git
+ > cd arm-trusted-firmware
+ > make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3368 bl31
+ > cp build/rk3368/release/bl31.bin ../u-boot/bl31-rk3368.bin
+
+Configure U-Boot
+================
+
+ > cd ../u-boot
+ > make lion-rk3368_defconfig
+
+Build the TPL/SPL stage
+=======================
+
+ > make CROSS_COMPILE=aarch64-unknown-elf- ARCH=arm
+ > tools/mkimage -n rk3368 -T rksd -d tpl/u-boot-tpl.bin spl-3368.img
+ > cat spl/u-boot-spl-dtb.bin >> spl-3368.img
+
+Build the full U-Boot and a FIT image including the ATF
+=======================================================
+
+ > make CROSS_COMPILE=aarch64-unknown-elf- ARCH=arm u-boot.itb
+
+Write to a SD-card
+==================
+
+ > dd if=spl-3368.img of=/dev/sdb seek=64
+ > dd if=u-boot.itb of=/dev/sdb seek=512
+
+
+If everything went according to plan, you should see the following
+output on UART0:
+
+<debug_uart> U-Boot TPL board init
+Trying to boot from BOOTROM
+Returning to boot ROM...
+Trying to boot from MMC1
+NOTICE: BL31: v1.3(release):v1.2-1320-gbf43a443
+NOTICE: BL31: Built : 18:04:47, Jul 5 2017
+
+
+U-Boot 2017.07-00158-g2395e99858 (Jul 18 2017 - 21:03:31 +0200)
+
+Model: Theobroma Systems RK3368-uQ7 SoM
+DRAM: 2 GiB
+MMC: dwmmc at ff0c0000: 1, dwmmc at ff0f0000: 0
+Using default environment
+
+In: serial at ff180000
+Out: serial at ff180000
+Err: serial at ff180000
+Net:
+Warning: ethernet at ff290000 (eth0) using random MAC address - d2:69:35:7e:d0:1e
+eth0: ethernet at ff290000
+Hit any key to stop autoboot: 2
diff --git a/board/theobroma-systems/lion_rk3368/fit_spl_atf.its b/board/theobroma-systems/lion_rk3368/fit_spl_atf.its
new file mode 100644
index 0000000..e7d98b9
--- /dev/null
+++ b/board/theobroma-systems/lion_rk3368/fit_spl_atf.its
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * Minimal dts for a SPL FIT image payload.
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/dts-v1/;
+
+/ {
+ description = "FIT image with U-Boot proper, ATF bl31, DTB";
+ #address-cells = <1>;
+
+ images {
+ uboot {
+ description = "U-Boot (64-bit)";
+ data = /incbin/("../../../u-boot-nodtb.bin");
+ type = "standalone";
+ arch = "arm64";
+ compression = "none";
+ load = <0x00200000>;
+ };
+ atf {
+ description = "ARM Trusted Firmware";
+ data = /incbin/("../../../bl31-rk3368.bin");
+ type = "firmware";
+ arch = "arm64";
+ compression = "none";
+ load = <0x00010000>;
+ entry = <0x00010000>;
+ };
+
+ fdt {
+ description = "RK3368-uQ7 (Lion) flat device-tree";
+ data = /incbin/("../../../u-boot.dtb");
+ type = "flat_dt";
+ compression = "none";
+ };
+ };
+
+ configurations {
+ default = "conf";
+ conf {
+ description = "Theobroma Systems RK3368-uQ7 (Puma) SoM";
+ firmware = "uboot";
+ loadables = "atf";
+ fdt = "fdt";
+ };
+ };
+};
diff --git a/board/theobroma-systems/lion_rk3368/lion_rk3368.c b/board/theobroma-systems/lion_rk3368/lion_rk3368.c
new file mode 100644
index 0000000..73b1488
--- /dev/null
+++ b/board/theobroma-systems/lion_rk3368/lion_rk3368.c
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <dm.h>
+#include <ram.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/grf_rk3368.h>
+#include <asm/arch/timer.h>
+#include <syscon.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int mach_cpu_init(void)
+{
+ return 0;
+}
+
+int board_init(void)
+{
+ return 0;
+}
diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig
new file mode 100644
index 0000000..701a78f
--- /dev/null
+++ b/configs/lion-rk3368_defconfig
@@ -0,0 +1,93 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ROCKCHIP_RK3368=y
+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_DEFAULT_DEVICE_TREE="rk3368-lion"
+CONFIG_SMBIOS_PRODUCT_NAME="sheep_rk3368"
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_SOURCE="board/theobroma-systems/lion_rk3368/fit_spl_atf.its"
+CONFIG_ENV_IS_IN_MMC=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_ARCH_EARLY_INIT_R=y
+CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot-spl.lds"
+CONFIG_SPL_BOOTROM_SUPPORT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
+CONFIG_SPL_ATF_SUPPORT=y
+CONFIG_SPL_ATF_TEXT_BASE=0x10000
+CONFIG_TPL=y
+CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds"
+CONFIG_TPL_BOOTROM_SUPPORT=y
+CONFIG_TPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_TPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent"
+CONFIG_TPL_OF_PLATDATA=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_TPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_TPL_SYSCON=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_TPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ9031=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_RGMII=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_ROCKCHIP_RK3368=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_TPL_RAM=y
+CONFIG_DEBUG_UART_BASE=0xFF180000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_ROCKCHIP_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_LZO=y
+CONFIG_ERRNO_STR=y
+CONFIG_SMBIOS_MANUFACTURER="rockchip"
diff --git a/include/configs/lion_rk3368.h b/include/configs/lion_rk3368.h
new file mode 100644
index 0000000..4118ffd
--- /dev/null
+++ b/include/configs/lion_rk3368.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIGS_LION_RK3368_H
+#define __CONFIGS_LION_RK3368_H
+
+#include <configs/rk3368_common.h>
+
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define KERNEL_LOAD_ADDR 0x280000
+#define DTB_LOAD_ADDR 0x5600000
+#define INITRD_LOAD_ADDR 0x5bf0000
+#define CONFIG_ENV_SIZE 0x2000
+
+#endif
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 59/66] spl: Kconfig: migrate $(SPL_TPL_)LDSCRIPT to Kconfig
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (57 preceding siblings ...)
2017-07-28 19:22 ` [U-Boot] [PATCH v3 58/66] rockchip: board: lion-rk3368: add support for the RK3368-uQ7 Philipp Tomsich
@ 2017-07-28 19:22 ` Philipp Tomsich
2017-08-01 9:48 ` Simon Glass
2017-07-28 19:22 ` [U-Boot] [PATCH v3 60/66] spl: moveconfig: migrate CONFIG_SPL_LDSCRIPT Philipp Tomsich
` (6 subsequent siblings)
65 siblings, 1 reply; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:22 UTC (permalink / raw)
To: u-boot
Now that we have split up SPL_LDSCRIPT into a SPL and TPL variant and
have started to use the TPL-variant for the RK3368, it's time to clean
up behind ourselves: move both variants into Kconfig and remove them
from the whitelist.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---
Changes in v3:
- moves SPL_LDSCRIPT and TPL_LDSCRIPT into Kconfig, as requested by
by Tom; this gets rid of the whitelist-entry for SPL_LDSCRIPT (which
qualifies as a preexisting condition) and of the newly created one
for TPL_LDSCRIPT
Changes in v2: None
common/spl/Kconfig | 18 ++++++++++++++++++
scripts/Makefile.spl | 9 ++++++++-
scripts/config_whitelist.txt | 2 --
3 files changed, 26 insertions(+), 3 deletions(-)
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 64f9e1f..b01d4f1 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -18,6 +18,15 @@ config SPL
if SPL
+config SPL_LDSCRIPT
+ string "Linker script for the SPL stage"
+ depends on SPL
+ help
+ The SPL stage will usually require a different linker-script
+ (as it runs from a different memory region) than the regular
+ U-Boot stage. Set this to the path of the linker-script to
+ be used for SPL.
+
config SPL_BOARD_INIT
bool "Call board-specific initialization in SPL"
help
@@ -707,6 +716,15 @@ config TPL
if TPL
+config TPL_LDSCRIPT
+ string "Linker script for the TPL stage"
+ depends on TPL
+ help
+ The TPL stage will usually require a different linker-script
+ (as it runs from a different memory region) than the regular
+ U-Boot stage. Set this to the path of the linker-script to
+ be used for TPL.
+
config TPL_BOOTROM_SUPPORT
bool "Support returning to the BOOTROM (from TPL)"
help
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 4a9a58f..167b2d9 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -103,9 +103,16 @@ u-boot-spl-platdata := $(obj)/dts/dt-platdata.o
endif
# Linker Script
-ifdef CONFIG_$(SPL_TPL_)LDSCRIPT
+# First test whether there's a linker-script for the specific stage defined...
+ifneq ($(CONFIG_$(SPL_TPL_)LDSCRIPT),)
# need to strip off double quotes
LDSCRIPT := $(addprefix $(srctree)/,$(CONFIG_$(SPL_TPL_)LDSCRIPT:"%"=%))
+else
+# ...then fall back to the generic SPL linker-script
+ifneq ($(CONFIG_SPL_LDSCRIPT),)
+# need to strip off double quotes
+LDSCRIPT := $(addprefix $(srctree)/,$(CONFIG_SPL_LDSCRIPT:"%"=%))
+endif
endif
ifeq ($(wildcard $(LDSCRIPT)),)
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index ee3fcd0..0e09a52 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -2252,7 +2252,6 @@ CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
CONFIG_SPL_INIT_MINIMAL
CONFIG_SPL_JR0_LIODN_NS
CONFIG_SPL_JR0_LIODN_S
-CONFIG_SPL_LDSCRIPT
CONFIG_SPL_LOAD_FIT_ADDRESS
CONFIG_SPL_MAX_FOOTPRINT
CONFIG_SPL_MAX_PEB_SIZE
@@ -4981,7 +4980,6 @@ CONFIG_TI_KEYSTONE_SERDES
CONFIG_TI_KSNAV
CONFIG_TI_SPI_MMAP
CONFIG_TMU_TIMER
-CONFIG_TPL_LDSCRIPT
CONFIG_TPL_MAX_SIZE
CONFIG_TPL_PAD_TO
CONFIG_TPL_STACK
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 59/66] spl: Kconfig: migrate $(SPL_TPL_)LDSCRIPT to Kconfig
2017-07-28 19:22 ` [U-Boot] [PATCH v3 59/66] spl: Kconfig: migrate $(SPL_TPL_)LDSCRIPT to Kconfig Philipp Tomsich
@ 2017-08-01 9:48 ` Simon Glass
0 siblings, 0 replies; 95+ messages in thread
From: Simon Glass @ 2017-08-01 9:48 UTC (permalink / raw)
To: u-boot
On 28 July 2017 at 13:22, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> Now that we have split up SPL_LDSCRIPT into a SPL and TPL variant and
> have started to use the TPL-variant for the RK3368, it's time to clean
> up behind ourselves: move both variants into Kconfig and remove them
> from the whitelist.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>
> ---
>
> Changes in v3:
> - moves SPL_LDSCRIPT and TPL_LDSCRIPT into Kconfig, as requested by
> by Tom; this gets rid of the whitelist-entry for SPL_LDSCRIPT (which
> qualifies as a preexisting condition) and of the newly created one
> for TPL_LDSCRIPT
>
> Changes in v2: None
>
> common/spl/Kconfig | 18 ++++++++++++++++++
> scripts/Makefile.spl | 9 ++++++++-
> scripts/config_whitelist.txt | 2 --
> 3 files changed, 26 insertions(+), 3 deletions(-)
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 95+ messages in thread
* [U-Boot] [PATCH v3 60/66] spl: moveconfig: migrate CONFIG_SPL_LDSCRIPT
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (58 preceding siblings ...)
2017-07-28 19:22 ` [U-Boot] [PATCH v3 59/66] spl: Kconfig: migrate $(SPL_TPL_)LDSCRIPT to Kconfig Philipp Tomsich
@ 2017-07-28 19:22 ` Philipp Tomsich
2017-07-28 19:52 ` Siarhei Siamashka
2017-07-28 19:22 ` [U-Boot] [PATCH v3 61/66] spl: support TPL_STACK, TPL_MAX_SIZE and TPL_TEXT_BASE via Kconfig Philipp Tomsich
` (5 subsequent siblings)
65 siblings, 1 reply; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:22 UTC (permalink / raw)
To: u-boot
With SPL_LDSCRIPT defined via Kconfig, we can run moveconfig... this
will touch every configuration that uses SPL, even if there was an
implicit resolution of the SPL_LDSCRIPT: now everything is explicit.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---
Changes in v3:
- moveconfig.py CONFIG_SPL_LDSCRIPT
(Note: I really don't know whether this is what we want, as it's
making the SPL_LDSCRIPT resolution explicit for every board...
then again, I understood Tom's comment that moving things into
Kconfig should be the priority...)
Changes in v2: None
configs/A10-OLinuXino-Lime_defconfig | 1 +
configs/A10s-OLinuXino-M_defconfig | 1 +
configs/A13-OLinuXinoM_defconfig | 1 +
configs/A13-OLinuXino_defconfig | 1 +
configs/A20-OLinuXino-Lime2_defconfig | 1 +
configs/A20-OLinuXino-Lime_defconfig | 1 +
configs/A20-OLinuXino_MICRO_defconfig | 1 +
configs/A20-Olimex-SOM-EVB_defconfig | 1 +
configs/A33-OLinuXino_defconfig | 1 +
configs/Ainol_AW1_defconfig | 1 +
configs/Ampe_A76_defconfig | 1 +
configs/Auxtek-T003_defconfig | 1 +
configs/Auxtek-T004_defconfig | 1 +
configs/Bananapi_M2_Ultra_defconfig | 1 +
configs/Bananapi_defconfig | 1 +
configs/Bananapro_defconfig | 1 +
configs/CHIP_defconfig | 1 +
configs/CHIP_pro_defconfig | 1 +
configs/CSQ_CS908_defconfig | 1 +
configs/Chuwi_V7_CW0825_defconfig | 1 +
configs/Colombus_defconfig | 1 +
configs/Cubieboard2_defconfig | 1 +
configs/Cubieboard4_defconfig | 1 +
configs/Cubieboard_defconfig | 1 +
configs/Cubietruck_defconfig | 1 +
configs/Cubietruck_plus_defconfig | 1 +
configs/Empire_electronix_d709_defconfig | 1 +
configs/Empire_electronix_m712_defconfig | 1 +
configs/Hummingbird_A31_defconfig | 1 +
configs/Hyundai_A7HD_defconfig | 1 +
configs/Itead_Ibox_A20_defconfig | 1 +
configs/Lamobo_R1_defconfig | 1 +
configs/Linksprite_pcDuino3_Nano_defconfig | 1 +
configs/Linksprite_pcDuino3_defconfig | 1 +
configs/Linksprite_pcDuino_defconfig | 1 +
configs/MK808C_defconfig | 1 +
configs/MSI_Primo73_defconfig | 1 +
configs/MSI_Primo81_defconfig | 1 +
configs/Marsboard_A10_defconfig | 1 +
configs/Mele_A1000G_quad_defconfig | 1 +
configs/Mele_A1000_defconfig | 1 +
configs/Mele_I7_defconfig | 1 +
configs/Mele_M3_defconfig | 1 +
configs/Mele_M5_defconfig | 1 +
configs/Mele_M9_defconfig | 1 +
configs/Merrii_A80_Optimus_defconfig | 1 +
configs/Mini-X_defconfig | 1 +
configs/Nintendo_NES_Classic_Edition_defconfig | 1 +
configs/Orangepi_defconfig | 1 +
configs/Orangepi_mini_defconfig | 1 +
configs/Sinlinx_SinA31s_defconfig | 1 +
configs/Sinlinx_SinA33_defconfig | 1 +
configs/Sinovoip_BPI_M2_Plus_defconfig | 1 +
configs/Sinovoip_BPI_M2_defconfig | 1 +
configs/Sinovoip_BPI_M3_defconfig | 1 +
configs/Sunchip_CX-A99_defconfig | 1 +
configs/UTOO_P66_defconfig | 1 +
configs/Wexler_TAB7200_defconfig | 1 +
configs/Wits_Pro_A20_DKT_defconfig | 1 +
configs/Wobo_i5_defconfig | 1 +
configs/Yones_Toptech_BD1078_defconfig | 1 +
configs/Yones_Toptech_BS1078_V2_defconfig | 1 +
configs/am335x_baltos_defconfig | 1 +
configs/am335x_boneblack_defconfig | 1 +
configs/am335x_boneblack_vboot_defconfig | 1 +
configs/am335x_evm_defconfig | 1 +
configs/am335x_evm_nor_defconfig | 1 +
configs/am335x_evm_spiboot_defconfig | 1 +
configs/am335x_evm_usbspl_defconfig | 1 +
configs/am335x_hs_evm_defconfig | 1 +
configs/am335x_igep003x_defconfig | 1 +
configs/am335x_shc_defconfig | 1 +
configs/am335x_shc_ict_defconfig | 1 +
configs/am335x_shc_netboot_defconfig | 1 +
configs/am335x_shc_prompt_defconfig | 1 +
configs/am335x_shc_sdboot_defconfig | 1 +
configs/am335x_shc_sdboot_prompt_defconfig | 1 +
configs/am335x_sl50_defconfig | 1 +
configs/am3517_crane_defconfig | 1 +
configs/am3517_evm_defconfig | 1 +
configs/am43xx_evm_defconfig | 1 +
configs/am43xx_evm_ethboot_defconfig | 1 +
configs/am43xx_evm_usbhost_boot_defconfig | 1 +
configs/am43xx_hs_evm_defconfig | 1 +
configs/am57xx_evm_defconfig | 1 +
configs/am57xx_evm_nodt_defconfig | 1 +
configs/am57xx_hs_evm_defconfig | 1 +
configs/apalis_imx6_defconfig | 1 +
configs/apf27_defconfig | 1 +
configs/apx4devkit_defconfig | 1 +
configs/arndale_defconfig | 1 +
configs/ba10_tv_box_defconfig | 1 +
configs/bg0900_defconfig | 1 +
configs/birdland_bav335a_defconfig | 1 +
configs/birdland_bav335b_defconfig | 1 +
configs/brppt1_mmc_defconfig | 1 +
configs/brppt1_nand_defconfig | 1 +
configs/brppt1_spi_defconfig | 1 +
configs/brxre1_defconfig | 1 +
configs/cairo_defconfig | 1 +
configs/cgtqmx6eval_defconfig | 1 +
configs/chiliboard_defconfig | 1 +
configs/chromebook_link64_defconfig | 5 +++--
configs/cl-som-am57x_defconfig | 1 +
configs/cm_fx6_defconfig | 1 +
configs/cm_t335_defconfig | 1 +
configs/cm_t35_defconfig | 1 +
configs/cm_t43_defconfig | 1 +
configs/cm_t54_defconfig | 3 ++-
configs/colibri_imx6_defconfig | 1 +
configs/colorfly_e708_q1_defconfig | 1 +
configs/controlcenterdc_defconfig | 2 +-
configs/da850_am18xxevm_defconfig | 1 +
configs/da850evm_defconfig | 1 +
configs/db-88f6820-gp_defconfig | 2 +-
configs/devkit8000_defconfig | 1 +
configs/difrnce_dit4350_defconfig | 1 +
configs/dra7xx_evm_defconfig | 3 ++-
configs/dra7xx_hs_evm_defconfig | 3 ++-
configs/draco_defconfig | 1 +
configs/dserve_dsrv9703c_defconfig | 1 +
configs/duovero_defconfig | 1 +
configs/eco5pk_defconfig | 1 +
configs/edminiv2_defconfig | 1 +
configs/etamin_defconfig | 1 +
configs/evb-rk3036_defconfig | 2 +-
configs/evb-rk3229_defconfig | 1 -
configs/firefly-rk3288_defconfig | 5 +----
configs/ga10h_v1_1_defconfig | 1 +
configs/gt90h_v4_defconfig | 1 +
configs/gwventana_emmc_defconfig | 1 +
configs/gwventana_gw5904_defconfig | 1 +
configs/gwventana_nand_defconfig | 1 +
configs/h8_homlet_v2_defconfig | 1 +
configs/i12-tvbox_defconfig | 1 +
configs/iNet_3F_defconfig | 1 +
configs/iNet_3W_defconfig | 1 +
configs/iNet_86VS_defconfig | 1 +
configs/iNet_D978_rev2_defconfig | 1 +
configs/icnova-a20-swac_defconfig | 1 +
configs/igep0020_defconfig | 1 +
configs/igep0030_defconfig | 1 +
configs/igep0032_defconfig | 1 +
configs/imx6qdl_icore_mmc_defconfig | 1 +
configs/imx6qdl_icore_nand_defconfig | 1 +
configs/imx6qdl_icore_rqs_defconfig | 1 +
configs/imx6ul_geam_mmc_defconfig | 1 +
configs/imx6ul_geam_nand_defconfig | 1 +
configs/imx6ul_isiot_emmc_defconfig | 1 +
configs/imx6ul_isiot_mmc_defconfig | 1 +
configs/imx6ul_isiot_nand_defconfig | 1 +
configs/inet1_defconfig | 1 +
configs/inet86dz_defconfig | 1 +
configs/inet97fv2_defconfig | 1 +
configs/inet98v_rev2_defconfig | 1 +
configs/inet9f_rev03_defconfig | 1 +
configs/inet_q972_defconfig | 1 +
configs/ipam390_defconfig | 1 +
configs/jesurun_q5_defconfig | 1 +
configs/kc1_defconfig | 1 +
configs/kylin-rk3036_defconfig | 2 +-
configs/liteboard_defconfig | 1 +
configs/ls1021aiot_sdcard_defconfig | 1 +
configs/ls1021aqds_nand_defconfig | 1 +
configs/ls1021aqds_sdcard_ifc_defconfig | 1 +
configs/ls1021aqds_sdcard_qspi_defconfig | 1 +
configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 1 +
configs/ls1021atwr_sdcard_ifc_defconfig | 1 +
configs/ls1021atwr_sdcard_qspi_defconfig | 1 +
configs/ls1043aqds_nand_defconfig | 1 +
configs/ls1043aqds_sdcard_ifc_defconfig | 1 +
configs/ls1043aqds_sdcard_qspi_defconfig | 1 +
configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 1 +
configs/ls1043ardb_nand_defconfig | 1 +
configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig | 1 +
configs/ls1043ardb_sdcard_defconfig | 1 +
configs/ls1046aqds_nand_defconfig | 1 +
configs/ls1046aqds_sdcard_ifc_defconfig | 1 +
configs/ls1046aqds_sdcard_qspi_defconfig | 1 +
configs/ls1046ardb_emmc_defconfig | 1 +
configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig | 1 +
configs/ls1046ardb_sdcard_defconfig | 1 +
configs/ls2080aqds_nand_defconfig | 1 +
configs/ls2080aqds_sdcard_defconfig | 1 +
configs/ls2080ardb_nand_defconfig | 1 +
configs/m28evk_defconfig | 1 +
configs/ma5d4evk_defconfig | 1 +
configs/mccmon6_nor_defconfig | 1 +
configs/mccmon6_sd_defconfig | 1 +
configs/mcx_defconfig | 1 +
configs/microblaze-generic_defconfig | 1 +
configs/mixtile_loftq_defconfig | 1 +
configs/mk802_a10s_defconfig | 1 +
configs/mk802_defconfig | 1 +
configs/mk802ii_defconfig | 1 +
configs/mt_ventoux_defconfig | 1 +
configs/mx23_olinuxino_defconfig | 1 +
configs/mx23evk_defconfig | 1 +
configs/mx28evk_auart_console_defconfig | 1 +
configs/mx28evk_defconfig | 1 +
configs/mx28evk_nand_defconfig | 1 +
configs/mx28evk_spi_defconfig | 1 +
configs/mx31pdk_defconfig | 1 +
configs/mx6cuboxi_defconfig | 1 +
configs/mx6sabreauto_defconfig | 1 +
configs/mx6sabresd_defconfig | 1 +
configs/mx6slevk_spl_defconfig | 1 +
configs/mx6sxsabresd_spl_defconfig | 1 +
configs/mx6ul_14x14_evk_defconfig | 1 +
configs/mx6ul_9x9_evk_defconfig | 1 +
configs/nanopi_m1_defconfig | 1 +
configs/nanopi_m1_plus_defconfig | 1 +
configs/nanopi_neo_air_defconfig | 1 +
configs/nanopi_neo_defconfig | 1 +
configs/novena_defconfig | 1 +
configs/omap3_beagle_defconfig | 1 +
configs/omap3_evm_defconfig | 1 +
configs/omap3_ha_defconfig | 1 +
configs/omap3_logic_defconfig | 1 +
configs/omap3_overo_defconfig | 1 +
configs/omap4_panda_defconfig | 1 +
configs/omap4_sdp4430_defconfig | 1 +
configs/omap5_uevm_defconfig | 3 ++-
configs/omapl138_lcdk_defconfig | 1 +
configs/opos6uldev_defconfig | 1 +
configs/orangepi_2_defconfig | 1 +
configs/orangepi_lite_defconfig | 1 +
configs/orangepi_one_defconfig | 1 +
configs/orangepi_pc_defconfig | 1 +
configs/orangepi_pc_plus_defconfig | 1 +
configs/orangepi_plus2e_defconfig | 1 +
configs/orangepi_plus_defconfig | 1 +
configs/orangepi_zero_defconfig | 1 +
configs/origen_defconfig | 1 +
configs/ot1200_spl_defconfig | 1 +
configs/parrot_r16_defconfig | 1 +
configs/pcm051_rev1_defconfig | 1 +
configs/pcm051_rev3_defconfig | 1 +
configs/pcm058_defconfig | 1 +
configs/peach-pi_defconfig | 1 +
configs/peach-pit_defconfig | 1 +
configs/pengwyn_defconfig | 1 +
configs/pepper_defconfig | 1 +
configs/picosam9g45_defconfig | 1 +
configs/platinum_picon_defconfig | 1 +
configs/platinum_titanium_defconfig | 1 +
configs/polaroid_mid2407pxe03_defconfig | 1 +
configs/polaroid_mid2809pxe04_defconfig | 1 +
configs/pov_protab2_ips9_defconfig | 1 +
configs/puma-rk3399_defconfig | 8 ++++----
configs/pxm2_defconfig | 1 +
configs/q8_a13_tablet_defconfig | 1 +
configs/q8_a23_tablet_800x480_defconfig | 1 +
configs/q8_a33_tablet_1024x600_defconfig | 1 +
configs/q8_a33_tablet_800x480_defconfig | 1 +
configs/qemu-x86_64_defconfig | 1 +
configs/r7-tv-dongle_defconfig | 1 +
configs/rastaban_defconfig | 1 +
configs/rut_defconfig | 1 +
configs/sama5d2_xplained_mmc_defconfig | 1 +
configs/sama5d3_xplained_mmc_defconfig | 1 +
configs/sama5d3xek_mmc_defconfig | 1 +
configs/sama5d4_xplained_mmc_defconfig | 1 +
configs/sama5d4ek_mmc_defconfig | 1 +
configs/sansa_fuze_plus_defconfig | 1 +
configs/sc_sps_1_defconfig | 1 +
configs/smartweb_defconfig | 1 +
configs/smdk5250_defconfig | 1 +
configs/smdk5420_defconfig | 1 +
configs/smdkv310_defconfig | 1 +
configs/sniper_defconfig | 1 +
configs/snow_defconfig | 1 +
configs/spring_defconfig | 1 +
configs/sun8i_a23_evb_defconfig | 1 +
configs/sunxi_Gemei_G9_defconfig | 1 +
configs/tao3530_defconfig | 1 +
configs/thuban_defconfig | 1 +
configs/ti814x_evm_defconfig | 1 +
configs/ti816x_evm_defconfig | 1 +
configs/topic_miami_defconfig | 1 +
configs/topic_miamilite_defconfig | 1 +
configs/topic_miamiplus_defconfig | 1 +
configs/tricorder_defconfig | 1 +
configs/tricorder_flash_defconfig | 1 +
configs/ts4600_defconfig | 1 +
configs/twister_defconfig | 1 +
configs/udoo_defconfig | 1 +
configs/udoo_neo_defconfig | 1 +
configs/wandboard_defconfig | 1 +
configs/woodburn_sd_defconfig | 1 +
configs/x600_defconfig | 1 +
configs/xfi3_defconfig | 1 +
configs/xpress_spl_defconfig | 1 +
configs/zc5202_defconfig | 1 +
configs/zc5601_defconfig | 1 +
configs/zynq_microzed_defconfig | 1 +
configs/zynq_picozed_defconfig | 1 +
configs/zynq_zc702_defconfig | 1 +
configs/zynq_zc706_defconfig | 1 +
configs/zynq_zc770_xm010_defconfig | 1 +
configs/zynq_zc770_xm011_defconfig | 1 +
configs/zynq_zc770_xm012_defconfig | 1 +
configs/zynq_zc770_xm013_defconfig | 1 +
configs/zynq_zed_defconfig | 1 +
configs/zynq_zybo_defconfig | 1 +
include/configs/am335x_evm.h | 2 --
include/configs/am335x_igep003x.h | 1 -
include/configs/am335x_shc.h | 2 --
include/configs/am335x_sl50.h | 2 --
include/configs/am3517_crane.h | 1 -
include/configs/am3517_evm.h | 1 -
include/configs/am43xx_evm.h | 2 --
include/configs/apf27.h | 1 -
include/configs/at91sam9m10g45ek.h | 1 -
include/configs/at91sam9n12ek.h | 1 -
include/configs/at91sam9x5ek.h | 1 -
include/configs/baltos.h | 2 --
include/configs/bav335x.h | 2 --
include/configs/bur_am335x_common.h | 1 -
include/configs/chiliboard.h | 2 --
include/configs/cm_t335.h | 1 -
include/configs/cm_t35.h | 1 -
include/configs/cm_t43.h | 2 --
include/configs/da850evm.h | 1 -
include/configs/edminiv2.h | 1 -
include/configs/exynos5-common.h | 1 -
include/configs/imx6_spl.h | 1 -
include/configs/ipam390.h | 1 -
include/configs/kc1.h | 2 --
include/configs/ls1021aiot.h | 1 -
include/configs/ls1021aqds.h | 2 --
include/configs/ls1021atwr.h | 1 -
include/configs/ls1043a_common.h | 2 --
include/configs/ls1046a_common.h | 2 --
include/configs/ls2080a_common.h | 1 -
include/configs/ma5d4evk.h | 1 -
include/configs/mcx.h | 1 -
include/configs/microblaze-generic.h | 2 --
include/configs/mx31pdk.h | 1 -
include/configs/mxs.h | 1 -
include/configs/omap3_evm.h | 1 -
include/configs/omapl138_lcdk.h | 1 -
include/configs/origen.h | 1 -
include/configs/pcm051.h | 2 --
include/configs/pengwyn.h | 2 --
include/configs/pepper.h | 1 -
include/configs/picosam9g45.h | 1 -
include/configs/rk3368_common.h | 2 --
include/configs/sama5d2_xplained.h | 1 -
include/configs/sama5d3_xplained.h | 1 -
include/configs/sama5d3xek.h | 1 -
include/configs/sama5d4_xplained.h | 1 -
include/configs/sama5d4ek.h | 1 -
include/configs/siemens-am33x-common.h | 2 --
include/configs/smartweb.h | 1 -
include/configs/smdkv310.h | 1 -
include/configs/sniper.h | 2 --
include/configs/sunxi-common.h | 4 ----
include/configs/tam3517-common.h | 1 -
include/configs/tao3530.h | 1 -
include/configs/ti814x_evm.h | 1 -
include/configs/ti816x_evm.h | 2 --
include/configs/ti_omap3_common.h | 1 -
include/configs/ti_omap4_common.h | 1 -
include/configs/ti_omap5_common.h | 1 -
include/configs/tricorder.h | 1 -
include/configs/woodburn_sd.h | 1 -
include/configs/x600.h | 1 -
include/configs/zynq-common.h | 2 --
369 files changed, 313 insertions(+), 106 deletions(-)
diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig
index 9143022..7d45c1d 100644
--- a/configs/A10-OLinuXino-Lime_defconfig
+++ b/configs/A10-OLinuXino-Lime_defconfig
@@ -11,6 +11,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-olinuxino-lime"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/A10s-OLinuXino-M_defconfig b/configs/A10s-OLinuXino-M_defconfig
index af6f5bc..e78ddf2 100644
--- a/configs/A10s-OLinuXino-M_defconfig
+++ b/configs/A10s-OLinuXino-M_defconfig
@@ -9,6 +9,7 @@ CONFIG_USB1_VBUS_PIN="PB10"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-olinuxino-micro"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/A13-OLinuXinoM_defconfig b/configs/A13-OLinuXinoM_defconfig
index 530a60e..e3a7049 100644
--- a/configs/A13-OLinuXinoM_defconfig
+++ b/configs/A13-OLinuXinoM_defconfig
@@ -13,6 +13,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino-micro"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig
index 15c6879..3768900 100644
--- a/configs/A13-OLinuXino_defconfig
+++ b/configs/A13-OLinuXino_defconfig
@@ -15,6 +15,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig
index f7b600b..fac0919 100644
--- a/configs/A20-OLinuXino-Lime2_defconfig
+++ b/configs/A20-OLinuXino-Lime2_defconfig
@@ -11,6 +11,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime2"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/A20-OLinuXino-Lime_defconfig b/configs/A20-OLinuXino-Lime_defconfig
index 182a8f5..38cf2cf 100644
--- a/configs/A20-OLinuXino-Lime_defconfig
+++ b/configs/A20-OLinuXino-Lime_defconfig
@@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig
index ae98e41..3ecd41c 100644
--- a/configs/A20-OLinuXino_MICRO_defconfig
+++ b/configs/A20-OLinuXino_MICRO_defconfig
@@ -12,6 +12,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-micro"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig
index 61fe5e6..16a657c 100644
--- a/configs/A20-Olimex-SOM-EVB_defconfig
+++ b/configs/A20-Olimex-SOM-EVB_defconfig
@@ -13,6 +13,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olimex-som-evb"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/A33-OLinuXino_defconfig b/configs/A33-OLinuXino_defconfig
index e959240..553ede0 100644
--- a/configs/A33-OLinuXino_defconfig
+++ b/configs/A33-OLinuXino_defconfig
@@ -16,6 +16,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-olinuxino"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/Ainol_AW1_defconfig b/configs/Ainol_AW1_defconfig
index 0e5023a..a2e0fbd 100644
--- a/configs/Ainol_AW1_defconfig
+++ b/configs/Ainol_AW1_defconfig
@@ -14,6 +14,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-ainol-aw1"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/Ampe_A76_defconfig b/configs/Ampe_A76_defconfig
index f3f599d..206c728 100644
--- a/configs/Ampe_A76_defconfig
+++ b/configs/Ampe_A76_defconfig
@@ -15,6 +15,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-ampe-a76"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/Auxtek-T003_defconfig b/configs/Auxtek-T003_defconfig
index f152414..f684fd7 100644
--- a/configs/Auxtek-T003_defconfig
+++ b/configs/Auxtek-T003_defconfig
@@ -8,6 +8,7 @@ CONFIG_VIDEO_COMPOSITE=y
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-auxtek-t003"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/Auxtek-T004_defconfig b/configs/Auxtek-T004_defconfig
index 3f24a06..e662959 100644
--- a/configs/Auxtek-T004_defconfig
+++ b/configs/Auxtek-T004_defconfig
@@ -6,6 +6,7 @@ CONFIG_USB1_VBUS_PIN="PG13"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-auxtek-t004"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/Bananapi_M2_Ultra_defconfig b/configs/Bananapi_M2_Ultra_defconfig
index 8c409fa..ab82b6b 100644
--- a/configs/Bananapi_M2_Ultra_defconfig
+++ b/configs/Bananapi_M2_Ultra_defconfig
@@ -10,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-r40-bananapi-m2-ultra"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig
index 352a18e..fc2a43a 100644
--- a/configs/Bananapi_defconfig
+++ b/configs/Bananapi_defconfig
@@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapi"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig
index 4218d5a..83cd6c4 100644
--- a/configs/Bananapro_defconfig
+++ b/configs/Bananapro_defconfig
@@ -11,6 +11,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapro"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/CHIP_defconfig b/configs/CHIP_defconfig
index e45ff3a..8fd7603 100644
--- a/configs/CHIP_defconfig
+++ b/configs/CHIP_defconfig
@@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-r8-chip"
# CONFIG_ENV_IS_IN_MMC is not set
CONFIG_ENV_IS_NOWHERE=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_DFU=y
diff --git a/configs/CHIP_pro_defconfig b/configs/CHIP_pro_defconfig
index f9033bc..fd99399 100644
--- a/configs/CHIP_pro_defconfig
+++ b/configs/CHIP_pro_defconfig
@@ -11,6 +11,7 @@ CONFIG_ENV_IS_IN_UBI=y
CONFIG_ENV_UBI_PART="UBI"
CONFIG_ENV_UBI_VOLUME="uboot-env"
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_LOADB is not set
diff --git a/configs/CSQ_CS908_defconfig b/configs/CSQ_CS908_defconfig
index a6fcbf5..7579b91 100644
--- a/configs/CSQ_CS908_defconfig
+++ b/configs/CSQ_CS908_defconfig
@@ -7,6 +7,7 @@ CONFIG_USB2_VBUS_PIN=""
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-cs908"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/Chuwi_V7_CW0825_defconfig b/configs/Chuwi_V7_CW0825_defconfig
index 684213e..49eb491 100644
--- a/configs/Chuwi_V7_CW0825_defconfig
+++ b/configs/Chuwi_V7_CW0825_defconfig
@@ -14,6 +14,7 @@ CONFIG_VIDEO_LCD_PANEL_HITACHI_TX18D42VM=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-chuwi-v7-cw0825"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig
index 1359281..1d15a66 100644
--- a/configs/Colombus_defconfig
+++ b/configs/Colombus_defconfig
@@ -17,6 +17,7 @@ CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804=y
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-colombus"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/Cubieboard2_defconfig b/configs/Cubieboard2_defconfig
index dc2722a..95ffd6d 100644
--- a/configs/Cubieboard2_defconfig
+++ b/configs/Cubieboard2_defconfig
@@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubieboard2"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/Cubieboard4_defconfig b/configs/Cubieboard4_defconfig
index 97cef1f..3421a81 100644
--- a/configs/Cubieboard4_defconfig
+++ b/configs/Cubieboard4_defconfig
@@ -12,6 +12,7 @@ CONFIG_USB3_VBUS_PIN="PH15"
CONFIG_AXP_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="sun9i-a80-cubieboard4"
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/Cubieboard_defconfig b/configs/Cubieboard_defconfig
index f83a691..ea44a75 100644
--- a/configs/Cubieboard_defconfig
+++ b/configs/Cubieboard_defconfig
@@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-cubieboard"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig
index cbd535c..936454f 100644
--- a/configs/Cubietruck_defconfig
+++ b/configs/Cubietruck_defconfig
@@ -13,6 +13,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubietruck"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/Cubietruck_plus_defconfig b/configs/Cubietruck_plus_defconfig
index 1a59e93..9bd85d0 100644
--- a/configs/Cubietruck_plus_defconfig
+++ b/configs/Cubietruck_plus_defconfig
@@ -15,6 +15,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-cubietruck-plus"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONSOLE_MUX=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/Empire_electronix_d709_defconfig b/configs/Empire_electronix_d709_defconfig
index 032056b..c50cc55 100644
--- a/configs/Empire_electronix_d709_defconfig
+++ b/configs/Empire_electronix_d709_defconfig
@@ -16,6 +16,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-empire-electronix-d709"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/Empire_electronix_m712_defconfig b/configs/Empire_electronix_m712_defconfig
index 8437da3..34cf6ac 100644
--- a/configs/Empire_electronix_m712_defconfig
+++ b/configs/Empire_electronix_m712_defconfig
@@ -15,6 +15,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-empire-electronix-m712"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/Hummingbird_A31_defconfig b/configs/Hummingbird_A31_defconfig
index 6f9b103..d392d5b 100644
--- a/configs/Hummingbird_A31_defconfig
+++ b/configs/Hummingbird_A31_defconfig
@@ -9,6 +9,7 @@ CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN="PH25"
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-hummingbird"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/Hyundai_A7HD_defconfig b/configs/Hyundai_A7HD_defconfig
index b7bd437..856743f 100644
--- a/configs/Hyundai_A7HD_defconfig
+++ b/configs/Hyundai_A7HD_defconfig
@@ -15,6 +15,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-hyundai-a7hd"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/Itead_Ibox_A20_defconfig b/configs/Itead_Ibox_A20_defconfig
index bab25b4..059459f 100644
--- a/configs/Itead_Ibox_A20_defconfig
+++ b/configs/Itead_Ibox_A20_defconfig
@@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-itead-ibox"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/Lamobo_R1_defconfig b/configs/Lamobo_R1_defconfig
index 2ec0847..a798ae0 100644
--- a/configs/Lamobo_R1_defconfig
+++ b/configs/Lamobo_R1_defconfig
@@ -10,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-lamobo-r1"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/Linksprite_pcDuino3_Nano_defconfig b/configs/Linksprite_pcDuino3_Nano_defconfig
index 1e61cd2..9117d1e 100644
--- a/configs/Linksprite_pcDuino3_Nano_defconfig
+++ b/configs/Linksprite_pcDuino3_Nano_defconfig
@@ -10,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3-nano"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig
index 6f4a02f..16eb3a7 100644
--- a/configs/Linksprite_pcDuino3_defconfig
+++ b/configs/Linksprite_pcDuino3_defconfig
@@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/Linksprite_pcDuino_defconfig b/configs/Linksprite_pcDuino_defconfig
index e33a9c1..c6f69c1 100644
--- a/configs/Linksprite_pcDuino_defconfig
+++ b/configs/Linksprite_pcDuino_defconfig
@@ -6,6 +6,7 @@ CONFIG_USB2_VBUS_PIN=""
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-pcduino"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/MK808C_defconfig b/configs/MK808C_defconfig
index e4a2dd7..f6c1264 100644
--- a/configs/MK808C_defconfig
+++ b/configs/MK808C_defconfig
@@ -5,6 +5,7 @@ CONFIG_DRAM_CLK=384
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-mk808c"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/MSI_Primo73_defconfig b/configs/MSI_Primo73_defconfig
index bd4cc03..34796c9 100644
--- a/configs/MSI_Primo73_defconfig
+++ b/configs/MSI_Primo73_defconfig
@@ -10,6 +10,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-primo73"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/MSI_Primo81_defconfig b/configs/MSI_Primo81_defconfig
index 08a7db2..0cc0953 100644
--- a/configs/MSI_Primo81_defconfig
+++ b/configs/MSI_Primo81_defconfig
@@ -13,6 +13,7 @@ CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828=y
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-primo81"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/Marsboard_A10_defconfig b/configs/Marsboard_A10_defconfig
index 516a16f..e95eb9a 100644
--- a/configs/Marsboard_A10_defconfig
+++ b/configs/Marsboard_A10_defconfig
@@ -5,6 +5,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-marsboard"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/Mele_A1000G_quad_defconfig b/configs/Mele_A1000G_quad_defconfig
index 5b1b5f5..7fcbe6e 100644
--- a/configs/Mele_A1000G_quad_defconfig
+++ b/configs/Mele_A1000G_quad_defconfig
@@ -8,6 +8,7 @@ CONFIG_USB2_VBUS_PIN=""
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mele-a1000g-quad"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/Mele_A1000_defconfig b/configs/Mele_A1000_defconfig
index 0c9e8d1..ecd3d30 100644
--- a/configs/Mele_A1000_defconfig
+++ b/configs/Mele_A1000_defconfig
@@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-a1000"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/Mele_I7_defconfig b/configs/Mele_I7_defconfig
index b609697..12163c6 100644
--- a/configs/Mele_I7_defconfig
+++ b/configs/Mele_I7_defconfig
@@ -7,6 +7,7 @@ CONFIG_USB2_VBUS_PIN=""
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-i7"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/Mele_M3_defconfig b/configs/Mele_M3_defconfig
index 08e8c2d..22b6b32 100644
--- a/configs/Mele_M3_defconfig
+++ b/configs/Mele_M3_defconfig
@@ -9,6 +9,7 @@ CONFIG_VIDEO_COMPOSITE=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m3"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/Mele_M5_defconfig b/configs/Mele_M5_defconfig
index 400a165..7e09bfd 100644
--- a/configs/Mele_M5_defconfig
+++ b/configs/Mele_M5_defconfig
@@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m5"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/Mele_M9_defconfig b/configs/Mele_M9_defconfig
index dc7901f..b57fc9b 100644
--- a/configs/Mele_M9_defconfig
+++ b/configs/Mele_M9_defconfig
@@ -7,6 +7,7 @@ CONFIG_USB2_VBUS_PIN=""
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-m9"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/Merrii_A80_Optimus_defconfig b/configs/Merrii_A80_Optimus_defconfig
index 8bc751c..af878a2 100644
--- a/configs/Merrii_A80_Optimus_defconfig
+++ b/configs/Merrii_A80_Optimus_defconfig
@@ -12,6 +12,7 @@ CONFIG_USB3_VBUS_PIN="PH5"
CONFIG_AXP_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="sun9i-a80-optimus"
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/Mini-X_defconfig b/configs/Mini-X_defconfig
index 811c941..81f1e99 100644
--- a/configs/Mini-X_defconfig
+++ b/configs/Mini-X_defconfig
@@ -6,6 +6,7 @@ CONFIG_VIDEO_COMPOSITE=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mini-xplus"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/Nintendo_NES_Classic_Edition_defconfig b/configs/Nintendo_NES_Classic_Edition_defconfig
index f9d8da1..993aba2 100644
--- a/configs/Nintendo_NES_Classic_Edition_defconfig
+++ b/configs/Nintendo_NES_Classic_Edition_defconfig
@@ -11,6 +11,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-r16-nintendo-nes-classic-edition"
# CONFIG_ENV_IS_IN_MMC is not set
CONFIG_ENV_IS_NOWHERE=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/Orangepi_defconfig b/configs/Orangepi_defconfig
index ed3e678..8ae3a20 100644
--- a/configs/Orangepi_defconfig
+++ b/configs/Orangepi_defconfig
@@ -12,6 +12,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig
index 56f405c..5019076 100644
--- a/configs/Orangepi_mini_defconfig
+++ b/configs/Orangepi_mini_defconfig
@@ -14,6 +14,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi-mini"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/Sinlinx_SinA31s_defconfig b/configs/Sinlinx_SinA31s_defconfig
index 7f815a3..7439410 100644
--- a/configs/Sinlinx_SinA31s_defconfig
+++ b/configs/Sinlinx_SinA31s_defconfig
@@ -11,6 +11,7 @@ CONFIG_USB2_VBUS_PIN=""
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-sina31s"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig
index d1b5b22..f25a707 100644
--- a/configs/Sinlinx_SinA33_defconfig
+++ b/configs/Sinlinx_SinA33_defconfig
@@ -14,6 +14,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-sinlinx-sina33"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_DFU=y
diff --git a/configs/Sinovoip_BPI_M2_Plus_defconfig b/configs/Sinovoip_BPI_M2_Plus_defconfig
index 651a2ff..4dbe78b 100644
--- a/configs/Sinovoip_BPI_M2_Plus_defconfig
+++ b/configs/Sinovoip_BPI_M2_Plus_defconfig
@@ -9,6 +9,7 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-bananapi-m2-plus"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/Sinovoip_BPI_M2_defconfig b/configs/Sinovoip_BPI_M2_defconfig
index a2cadbc..14053f7 100644
--- a/configs/Sinovoip_BPI_M2_defconfig
+++ b/configs/Sinovoip_BPI_M2_defconfig
@@ -7,6 +7,7 @@ CONFIG_USB2_VBUS_PIN=""
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-sinovoip-bpi-m2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/Sinovoip_BPI_M3_defconfig b/configs/Sinovoip_BPI_M3_defconfig
index 45eadcb..a8a56b6 100644
--- a/configs/Sinovoip_BPI_M3_defconfig
+++ b/configs/Sinovoip_BPI_M3_defconfig
@@ -16,6 +16,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-sinovoip-bpi-m3"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONSOLE_MUX=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/Sunchip_CX-A99_defconfig b/configs/Sunchip_CX-A99_defconfig
index 0641b1f..234b30f 100644
--- a/configs/Sunchip_CX-A99_defconfig
+++ b/configs/Sunchip_CX-A99_defconfig
@@ -12,6 +12,7 @@ CONFIG_USB3_VBUS_PIN="PL8"
CONFIG_DEFAULT_DEVICE_TREE="sun9i-a80-cx-a99"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/UTOO_P66_defconfig b/configs/UTOO_P66_defconfig
index 99b15ea..e701328 100644
--- a/configs/UTOO_P66_defconfig
+++ b/configs/UTOO_P66_defconfig
@@ -20,6 +20,7 @@ CONFIG_VIDEO_LCD_TL059WV5C0=y
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-utoo-p66"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/Wexler_TAB7200_defconfig b/configs/Wexler_TAB7200_defconfig
index f80233a..cc3f9df 100644
--- a/configs/Wexler_TAB7200_defconfig
+++ b/configs/Wexler_TAB7200_defconfig
@@ -13,6 +13,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-wexler-tab7200"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/Wits_Pro_A20_DKT_defconfig b/configs/Wits_Pro_A20_DKT_defconfig
index 2a2f26d..6a1ebe3 100644
--- a/configs/Wits_Pro_A20_DKT_defconfig
+++ b/configs/Wits_Pro_A20_DKT_defconfig
@@ -12,6 +12,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-wits-pro-a20-dkt"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/Wobo_i5_defconfig b/configs/Wobo_i5_defconfig
index 90f391f..8439881 100644
--- a/configs/Wobo_i5_defconfig
+++ b/configs/Wobo_i5_defconfig
@@ -7,6 +7,7 @@ CONFIG_USB1_VBUS_PIN="PG12"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-wobo-i5"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/Yones_Toptech_BD1078_defconfig b/configs/Yones_Toptech_BD1078_defconfig
index 9612712..7f07e27 100644
--- a/configs/Yones_Toptech_BD1078_defconfig
+++ b/configs/Yones_Toptech_BD1078_defconfig
@@ -19,6 +19,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-yones-toptech-bd1078"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/Yones_Toptech_BS1078_V2_defconfig b/configs/Yones_Toptech_BS1078_V2_defconfig
index 3cbf41e..b95a8a1 100644
--- a/configs/Yones_Toptech_BS1078_V2_defconfig
+++ b/configs/Yones_Toptech_BS1078_V2_defconfig
@@ -16,6 +16,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-yones-toptech-bs1078-v2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig
index 09e028f..c516932 100644
--- a/configs/am335x_baltos_defconfig
+++ b/configs/am335x_baltos_defconfig
@@ -20,6 +20,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_STACK_R=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
diff --git a/configs/am335x_boneblack_defconfig b/configs/am335x_boneblack_defconfig
index 516ad70..107c0df 100644
--- a/configs/am335x_boneblack_defconfig
+++ b/configs/am335x_boneblack_defconfig
@@ -11,6 +11,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_STACK_R=y
CONFIG_SPL_MUSB_NEW_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig
index 33da1fa..c332ed2 100644
--- a/configs/am335x_boneblack_vboot_defconfig
+++ b/configs/am335x_boneblack_vboot_defconfig
@@ -14,6 +14,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_STACK_R=y
CONFIG_SPL_MUSB_NEW_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index 4ea5617..c11d99f 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -12,6 +12,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_STACK_R=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_MUSB_NEW_SUPPORT=y
diff --git a/configs/am335x_evm_nor_defconfig b/configs/am335x_evm_nor_defconfig
index 49040a6..c5c129b 100644
--- a/configs/am335x_evm_nor_defconfig
+++ b/configs/am335x_evm_nor_defconfig
@@ -10,6 +10,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_STACK_R=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_MUSB_NEW_SUPPORT=y
diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig
index 5cbfa8e..68df873 100644
--- a/configs/am335x_evm_spiboot_defconfig
+++ b/configs/am335x_evm_spiboot_defconfig
@@ -14,6 +14,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_STACK_R=y
CONFIG_SPL_MUSB_NEW_SUPPORT=y
CONFIG_FASTBOOT=y
diff --git a/configs/am335x_evm_usbspl_defconfig b/configs/am335x_evm_usbspl_defconfig
index 51d1042..2195640 100644
--- a/configs/am335x_evm_usbspl_defconfig
+++ b/configs/am335x_evm_usbspl_defconfig
@@ -11,6 +11,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_STACK_R=y
CONFIG_SPL_MUSB_NEW_SUPPORT=y
CONFIG_SPL_NET_SUPPORT=y
diff --git a/configs/am335x_hs_evm_defconfig b/configs/am335x_hs_evm_defconfig
index 2b1acb7..6e3c84d 100644
--- a/configs/am335x_hs_evm_defconfig
+++ b/configs/am335x_hs_evm_defconfig
@@ -17,6 +17,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_STACK_R=y
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_SPL_MTD_SUPPORT=y
diff --git a/configs/am335x_igep003x_defconfig b/configs/am335x_igep003x_defconfig
index 2e7962f..7121d95 100644
--- a/configs/am335x_igep003x_defconfig
+++ b/configs/am335x_igep003x_defconfig
@@ -19,6 +19,7 @@ CONFIG_ENV_IS_IN_UBI=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_STACK_R=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
diff --git a/configs/am335x_shc_defconfig b/configs/am335x_shc_defconfig
index 9b4802e..98eccc0 100644
--- a/configs/am335x_shc_defconfig
+++ b/configs/am335x_shc_defconfig
@@ -16,6 +16,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_STACK_R=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
diff --git a/configs/am335x_shc_ict_defconfig b/configs/am335x_shc_ict_defconfig
index 637306d..a319bf5 100644
--- a/configs/am335x_shc_ict_defconfig
+++ b/configs/am335x_shc_ict_defconfig
@@ -17,6 +17,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_STACK_R=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
diff --git a/configs/am335x_shc_netboot_defconfig b/configs/am335x_shc_netboot_defconfig
index 5c0c912..93193f6 100644
--- a/configs/am335x_shc_netboot_defconfig
+++ b/configs/am335x_shc_netboot_defconfig
@@ -17,6 +17,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_STACK_R=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_EXT_SUPPORT=y
diff --git a/configs/am335x_shc_prompt_defconfig b/configs/am335x_shc_prompt_defconfig
index e5903de..b0913e1 100644
--- a/configs/am335x_shc_prompt_defconfig
+++ b/configs/am335x_shc_prompt_defconfig
@@ -16,6 +16,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_STACK_R=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
diff --git a/configs/am335x_shc_sdboot_defconfig b/configs/am335x_shc_sdboot_defconfig
index c8f7632..3052f7b 100644
--- a/configs/am335x_shc_sdboot_defconfig
+++ b/configs/am335x_shc_sdboot_defconfig
@@ -17,6 +17,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_STACK_R=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
diff --git a/configs/am335x_shc_sdboot_prompt_defconfig b/configs/am335x_shc_sdboot_prompt_defconfig
index c8f7632..3052f7b 100644
--- a/configs/am335x_shc_sdboot_prompt_defconfig
+++ b/configs/am335x_shc_sdboot_prompt_defconfig
@@ -17,6 +17,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_STACK_R=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig
index 5d5c68e..27bbb26 100644
--- a/configs/am335x_sl50_defconfig
+++ b/configs/am335x_sl50_defconfig
@@ -17,6 +17,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_STACK_R=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_EXT_SUPPORT=y
diff --git a/configs/am3517_crane_defconfig b/configs/am3517_crane_defconfig
index 2102956..4d7058f 100644
--- a/configs/am3517_crane_defconfig
+++ b/configs/am3517_crane_defconfig
@@ -6,6 +6,7 @@ CONFIG_TARGET_AM3517_CRANE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="AM3517_CRANE # "
diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig
index eddeb5e..c20680a 100644
--- a/configs/am3517_evm_defconfig
+++ b/configs/am3517_evm_defconfig
@@ -8,6 +8,7 @@ CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
index 7a7a0b0..04727d4 100644
--- a/configs/am43xx_evm_defconfig
+++ b/configs/am43xx_evm_defconfig
@@ -11,6 +11,7 @@ CONFIG_ENV_IS_IN_FAT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_STACK_R=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
diff --git a/configs/am43xx_evm_ethboot_defconfig b/configs/am43xx_evm_ethboot_defconfig
index 9892653..fdf380f 100644
--- a/configs/am43xx_evm_ethboot_defconfig
+++ b/configs/am43xx_evm_ethboot_defconfig
@@ -6,6 +6,7 @@ CONFIG_ENV_IS_IN_FAT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
CONFIG_SPL_ETH_SUPPORT=y
CONFIG_SPL_MTD_SUPPORT=y
diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig
index f4c0f84..5252bc8 100644
--- a/configs/am43xx_evm_usbhost_boot_defconfig
+++ b/configs/am43xx_evm_usbhost_boot_defconfig
@@ -11,6 +11,7 @@ CONFIG_ENV_IS_IN_FAT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_STACK_R=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig
index 5306c26..4ff45a2 100644
--- a/configs/am43xx_hs_evm_defconfig
+++ b/configs/am43xx_hs_evm_defconfig
@@ -19,6 +19,7 @@ CONFIG_ENV_IS_IN_FAT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_STACK_R=y
CONFIG_SPL_ETH_SUPPORT=y
CONFIG_SPL_MTD_SUPPORT=y
diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index d6e293c..8242171 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -17,6 +17,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SEPARATE_BSS=y
diff --git a/configs/am57xx_evm_nodt_defconfig b/configs/am57xx_evm_nodt_defconfig
index 0a898de..de96894 100644
--- a/configs/am57xx_evm_nodt_defconfig
+++ b/configs/am57xx_evm_nodt_defconfig
@@ -10,6 +10,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
index 50a19b3..ae3e05a 100644
--- a/configs/am57xx_hs_evm_defconfig
+++ b/configs/am57xx_hs_evm_defconfig
@@ -23,6 +23,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SEPARATE_BSS=y
diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig
index 4d88e70..a0703d0 100644
--- a/configs/apalis_imx6_defconfig
+++ b/configs/apalis_imx6_defconfig
@@ -15,6 +15,7 @@ CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/apf27_defconfig b/configs/apf27_defconfig
index 6d7c198..2d599d5 100644
--- a/configs/apf27_defconfig
+++ b/configs/apf27_defconfig
@@ -8,6 +8,7 @@ CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=5
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/$(ARCH)/cpu/u-boot-spl.lds"
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="BIOS> "
# CONFIG_CMD_IMLS is not set
diff --git a/configs/apx4devkit_defconfig b/configs/apx4devkit_defconfig
index f5b18e0..a80bb55 100644
--- a/configs/apx4devkit_defconfig
+++ b/configs/apx4devkit_defconfig
@@ -11,6 +11,7 @@ CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/arndale_defconfig b/configs/arndale_defconfig
index 66ffefd..e45e658 100644
--- a/configs/arndale_defconfig
+++ b/configs/arndale_defconfig
@@ -11,6 +11,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="board/samsung/common/exynos-uboot-spl.lds"
CONFIG_SYS_PROMPT="ARNDALE # "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MMC=y
diff --git a/configs/ba10_tv_box_defconfig b/configs/ba10_tv_box_defconfig
index ad066fd..4c0896d 100644
--- a/configs/ba10_tv_box_defconfig
+++ b/configs/ba10_tv_box_defconfig
@@ -9,6 +9,7 @@ CONFIG_VIDEO_COMPOSITE=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-ba10-tvbox"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/bg0900_defconfig b/configs/bg0900_defconfig
index 01012c8..f653557 100644
--- a/configs/bg0900_defconfig
+++ b/configs/bg0900_defconfig
@@ -11,6 +11,7 @@ CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
diff --git a/configs/birdland_bav335a_defconfig b/configs/birdland_bav335a_defconfig
index c5d15c6..f504b5f 100644
--- a/configs/birdland_bav335a_defconfig
+++ b/configs/birdland_bav335a_defconfig
@@ -17,6 +17,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MUSB_NEW_SUPPORT=y
diff --git a/configs/birdland_bav335b_defconfig b/configs/birdland_bav335b_defconfig
index 31e077c..5475157 100644
--- a/configs/birdland_bav335b_defconfig
+++ b/configs/birdland_bav335b_defconfig
@@ -17,6 +17,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MUSB_NEW_SUPPORT=y
diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig
index 4aded16..13df6d7 100644
--- a/configs/brppt1_mmc_defconfig
+++ b/configs/brppt1_mmc_defconfig
@@ -21,6 +21,7 @@ CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
diff --git a/configs/brppt1_nand_defconfig b/configs/brppt1_nand_defconfig
index e128fb4..2dd789d 100644
--- a/configs/brppt1_nand_defconfig
+++ b/configs/brppt1_nand_defconfig
@@ -21,6 +21,7 @@ CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
diff --git a/configs/brppt1_spi_defconfig b/configs/brppt1_spi_defconfig
index 1e156ca..cf7e785 100644
--- a/configs/brppt1_spi_defconfig
+++ b/configs/brppt1_spi_defconfig
@@ -24,6 +24,7 @@ CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
diff --git a/configs/brxre1_defconfig b/configs/brxre1_defconfig
index 3dac8a9..6bb87ee 100644
--- a/configs/brxre1_defconfig
+++ b/configs/brxre1_defconfig
@@ -19,6 +19,7 @@ CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
diff --git a/configs/cairo_defconfig b/configs/cairo_defconfig
index 5d26532..7bbf466 100644
--- a/configs/cairo_defconfig
+++ b/configs/cairo_defconfig
@@ -6,6 +6,7 @@ CONFIG_BOOTDELAY=-2
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/cgtqmx6eval_defconfig b/configs/cgtqmx6eval_defconfig
index e20e5f8..22cc140 100644
--- a/configs/cgtqmx6eval_defconfig
+++ b/configs/cgtqmx6eval_defconfig
@@ -20,6 +20,7 @@ CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
# CONFIG_SYS_STDIO_DEREGISTER is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/chiliboard_defconfig b/configs/chiliboard_defconfig
index e14ef5d..53a6b9f 100644
--- a/configs/chiliboard_defconfig
+++ b/configs/chiliboard_defconfig
@@ -15,6 +15,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=1
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_STACK_R=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
diff --git a/configs/chromebook_link64_defconfig b/configs/chromebook_link64_defconfig
index 11ceb76..b8bc70f 100644
--- a/configs/chromebook_link64_defconfig
+++ b/configs/chromebook_link64_defconfig
@@ -58,6 +58,8 @@ CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
CONFIG_BLK=y
CONFIG_CPU=y
CONFIG_DM_I2C=y
@@ -70,14 +72,13 @@ CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
-CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_SYS_NS16550=y
CONFIG_ICH_SPI=y
CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
CONFIG_TPM_TIS_LPC=y
CONFIG_USB=y
CONFIG_DM_USB=y
diff --git a/configs/cl-som-am57x_defconfig b/configs/cl-som-am57x_defconfig
index 0d1f614..17cce30 100644
--- a/configs/cl-som-am57x_defconfig
+++ b/configs/cl-som-am57x_defconfig
@@ -6,6 +6,7 @@ CONFIG_TARGET_CL_SOM_AM57X=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot# "
diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig
index c96285b..e55c3db 100644
--- a/configs/cm_fx6_defconfig
+++ b/configs/cm_fx6_defconfig
@@ -16,6 +16,7 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x80
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/cm_t335_defconfig b/configs/cm_t335_defconfig
index 8176a65..656d055 100644
--- a/configs/cm_t335_defconfig
+++ b/configs/cm_t335_defconfig
@@ -15,6 +15,7 @@ CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MTD_SUPPORT=y
diff --git a/configs/cm_t35_defconfig b/configs/cm_t35_defconfig
index ba76463..33cdff6 100644
--- a/configs/cm_t35_defconfig
+++ b/configs/cm_t35_defconfig
@@ -7,6 +7,7 @@ CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="CM-T3x # "
diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig
index a9f3af4..ec50fe1 100644
--- a/configs/cm_t43_defconfig
+++ b/configs/cm_t43_defconfig
@@ -16,6 +16,7 @@ CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x480
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
diff --git a/configs/cm_t54_defconfig b/configs/cm_t54_defconfig
index 4aed572..c738c49 100644
--- a/configs/cm_t54_defconfig
+++ b/configs/cm_t54_defconfig
@@ -10,6 +10,7 @@ CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
CONFIG_SPL_SATA_SUPPORT=y
CONFIG_HUSH_PARSER=y
@@ -39,8 +40,8 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
-CONFIG_MMC_OMAP_HS=y
CONFIG_SCSI=y
+CONFIG_MMC_OMAP_HS=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig
index a23975f..94af0b7 100644
--- a/configs/colibri_imx6_defconfig
+++ b/configs/colibri_imx6_defconfig
@@ -15,6 +15,7 @@ CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/colorfly_e708_q1_defconfig b/configs/colorfly_e708_q1_defconfig
index c0ed30e..f1d6494 100644
--- a/configs/colorfly_e708_q1_defconfig
+++ b/configs/colorfly_e708_q1_defconfig
@@ -16,6 +16,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-colorfly-e708-q1"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/controlcenterdc_defconfig b/configs/controlcenterdc_defconfig
index af79b6c..62c6546 100644
--- a/configs/controlcenterdc_defconfig
+++ b/configs/controlcenterdc_defconfig
@@ -35,6 +35,7 @@ CONFIG_CMD_EXT4=y
CONFIG_EFI_PARTITION=y
CONFIG_OF_BOARD_FIXUP=y
CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_SCSI=y
CONFIG_DM_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
@@ -45,7 +46,6 @@ CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_MV=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SCSI=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
CONFIG_DEBUG_UART_SHIFT=2
diff --git a/configs/da850_am18xxevm_defconfig b/configs/da850_am18xxevm_defconfig
index e3320e6..507f1f6 100644
--- a/configs/da850_am18xxevm_defconfig
+++ b/configs/da850_am18xxevm_defconfig
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="board/$(BOARDDIR)/u-boot-spl-da850evm.lds"
CONFIG_SPL_BOARD_INIT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig
index a49ef71..02bfebd 100644
--- a/configs/da850evm_defconfig
+++ b/configs/da850evm_defconfig
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="board/$(BOARDDIR)/u-boot-spl-da850evm.lds"
CONFIG_SPL_BOARD_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot > "
diff --git a/configs/db-88f6820-gp_defconfig b/configs/db-88f6820-gp_defconfig
index 6c6083d..5f072c5 100644
--- a/configs/db-88f6820-gp_defconfig
+++ b/configs/db-88f6820-gp_defconfig
@@ -38,6 +38,7 @@ CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_SCSI=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_MV=y
@@ -45,7 +46,6 @@ CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PCI=y
-CONFIG_SCSI=y
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART_CLOCK=250000000
CONFIG_DEBUG_UART_SHIFT=2
diff --git a/configs/devkit8000_defconfig b/configs/devkit8000_defconfig
index f5e5317..2e1a4a4 100644
--- a/configs/devkit8000_defconfig
+++ b/configs/devkit8000_defconfig
@@ -5,6 +5,7 @@ CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMI is not set
diff --git a/configs/difrnce_dit4350_defconfig b/configs/difrnce_dit4350_defconfig
index 629507e..1cedf97 100644
--- a/configs/difrnce_dit4350_defconfig
+++ b/configs/difrnce_dit4350_defconfig
@@ -15,6 +15,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-difrnce-dit4350"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index 979f3ec..2180399 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -17,6 +17,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SEPARATE_BSS=y
@@ -45,6 +46,7 @@ CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_DM_SCSI=y
CONFIG_DWC_AHCI=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
@@ -68,7 +70,6 @@ CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_REGULATOR_PALMAS=y
CONFIG_DM_REGULATOR_LP873X=y
-CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig
index 8292bdf..d2d8ad4 100644
--- a/configs/dra7xx_hs_evm_defconfig
+++ b/configs/dra7xx_hs_evm_defconfig
@@ -23,6 +23,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SEPARATE_BSS=y
@@ -48,6 +49,7 @@ CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
+CONFIG_DM_SCSI=y
CONFIG_DWC_AHCI=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
@@ -71,7 +73,6 @@ CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_REGULATOR_PALMAS=y
CONFIG_DM_REGULATOR_LP873X=y
-CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
diff --git a/configs/draco_defconfig b/configs/draco_defconfig
index 763e96b..b040d1d 100644
--- a/configs/draco_defconfig
+++ b/configs/draco_defconfig
@@ -22,6 +22,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/dserve_dsrv9703c_defconfig b/configs/dserve_dsrv9703c_defconfig
index c92fdb1..436a9a8 100644
--- a/configs/dserve_dsrv9703c_defconfig
+++ b/configs/dserve_dsrv9703c_defconfig
@@ -14,6 +14,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-dserve-dsrv9703c"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/duovero_defconfig b/configs/duovero_defconfig
index ced8156..bf8c15b 100644
--- a/configs/duovero_defconfig
+++ b/configs/duovero_defconfig
@@ -9,6 +9,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
# CONFIG_SPL_I2C_SUPPORT is not set
CONFIG_SYS_PROMPT="duovero # "
# CONFIG_CMD_IMLS is not set
diff --git a/configs/eco5pk_defconfig b/configs/eco5pk_defconfig
index 0bcc75b..c4f274a 100644
--- a/configs/eco5pk_defconfig
+++ b/configs/eco5pk_defconfig
@@ -5,6 +5,7 @@ CONFIG_TARGET_ECO5PK=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ECO5-PK # "
diff --git a/configs/edminiv2_defconfig b/configs/edminiv2_defconfig
index 847c6c2..88f2a40 100644
--- a/configs/edminiv2_defconfig
+++ b/configs/edminiv2_defconfig
@@ -10,6 +10,7 @@ CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="$(CPUDIR)/orion5x/u-boot-spl.lds"
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/etamin_defconfig b/configs/etamin_defconfig
index ab3ef75..c8b57af 100644
--- a/configs/etamin_defconfig
+++ b/configs/etamin_defconfig
@@ -22,6 +22,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig
index 7ba75fd..f6affc3 100644
--- a/configs/evb-rk3036_defconfig
+++ b/configs/evb-rk3036_defconfig
@@ -7,8 +7,8 @@ CONFIG_ROCKCHIP_RK3036=y
CONFIG_TARGET_EVB_RK3036=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk"
-CONFIG_SPL_SYS_MALLOC_F_LEN=0x0
CONFIG_DEBUG_UART=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x0
CONFIG_ENV_IS_NOWHERE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig
index 8b9a288..75bc383 100644
--- a/configs/evb-rk3229_defconfig
+++ b/configs/evb-rk3229_defconfig
@@ -4,7 +4,6 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_ROCKCHIP_RK322X=y
-CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y
CONFIG_TARGET_EVB_RK3229=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3229-evb"
diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
index f0569a6..ab8deb6 100644
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig
@@ -41,6 +41,7 @@ CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_DM_KEYBOARD=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_MMC_DW=y
@@ -76,7 +77,3 @@ CONFIG_CONSOLE_SCROLL_LINES=10
CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_DM_KEYBOARD=y
-CONFIG_SYS_USB_EVENT_POLL=y
-CONFIG_SYS_STDIO_DEREGISTER=y
diff --git a/configs/ga10h_v1_1_defconfig b/configs/ga10h_v1_1_defconfig
index 8e1c9f7..70db429 100644
--- a/configs/ga10h_v1_1_defconfig
+++ b/configs/ga10h_v1_1_defconfig
@@ -17,6 +17,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-ga10h-v1.1"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/gt90h_v4_defconfig b/configs/gt90h_v4_defconfig
index 8f6469d..40b6ca8 100644
--- a/configs/gt90h_v4_defconfig
+++ b/configs/gt90h_v4_defconfig
@@ -16,6 +16,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-gt90h-v4"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig
index cdf3e92..a674f51 100644
--- a/configs/gwventana_emmc_defconfig
+++ b/configs/gwventana_emmc_defconfig
@@ -22,6 +22,7 @@ CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_DMA_SUPPORT=y
diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig
index c5b5232..be22669 100644
--- a/configs/gwventana_gw5904_defconfig
+++ b/configs/gwventana_gw5904_defconfig
@@ -22,6 +22,7 @@ CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_DMA_SUPPORT=y
diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig
index 2de3355..62697eb 100644
--- a/configs/gwventana_nand_defconfig
+++ b/configs/gwventana_nand_defconfig
@@ -23,6 +23,7 @@ CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_DMA_SUPPORT=y
diff --git a/configs/h8_homlet_v2_defconfig b/configs/h8_homlet_v2_defconfig
index 368233a..eecb882 100644
--- a/configs/h8_homlet_v2_defconfig
+++ b/configs/h8_homlet_v2_defconfig
@@ -11,6 +11,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-allwinner-h8homlet-v2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONSOLE_MUX=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/i12-tvbox_defconfig b/configs/i12-tvbox_defconfig
index 4245491..b5bf64a 100644
--- a/configs/i12-tvbox_defconfig
+++ b/configs/i12-tvbox_defconfig
@@ -7,6 +7,7 @@ CONFIG_VIDEO_COMPOSITE=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-i12-tvbox"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/iNet_3F_defconfig b/configs/iNet_3F_defconfig
index 231b2b9..6210263 100644
--- a/configs/iNet_3F_defconfig
+++ b/configs/iNet_3F_defconfig
@@ -14,6 +14,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet-3f"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/iNet_3W_defconfig b/configs/iNet_3W_defconfig
index a366abe..247222e 100644
--- a/configs/iNet_3W_defconfig
+++ b/configs/iNet_3W_defconfig
@@ -14,6 +14,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet-3w"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/iNet_86VS_defconfig b/configs/iNet_86VS_defconfig
index ed8650b..88ee0c7 100644
--- a/configs/iNet_86VS_defconfig
+++ b/configs/iNet_86VS_defconfig
@@ -13,6 +13,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-inet-86vs"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/iNet_D978_rev2_defconfig b/configs/iNet_D978_rev2_defconfig
index 62e4f1b..1ee7ed3 100644
--- a/configs/iNet_D978_rev2_defconfig
+++ b/configs/iNet_D978_rev2_defconfig
@@ -17,6 +17,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-inet-d978-rev2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/icnova-a20-swac_defconfig b/configs/icnova-a20-swac_defconfig
index 6f79c58..ae084ac 100644
--- a/configs/icnova-a20-swac_defconfig
+++ b/configs/icnova-a20-swac_defconfig
@@ -13,6 +13,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-icnova-swac"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_UNZIP=y
diff --git a/configs/igep0020_defconfig b/configs/igep0020_defconfig
index 7f8663e..f294e9c 100644
--- a/configs/igep0020_defconfig
+++ b/configs/igep0020_defconfig
@@ -11,6 +11,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_ONENAND_SUPPORT=y
diff --git a/configs/igep0030_defconfig b/configs/igep0030_defconfig
index 7719cd6..2393e39 100644
--- a/configs/igep0030_defconfig
+++ b/configs/igep0030_defconfig
@@ -11,6 +11,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_ONENAND_SUPPORT=y
diff --git a/configs/igep0032_defconfig b/configs/igep0032_defconfig
index 758b795..7fa9632 100644
--- a/configs/igep0032_defconfig
+++ b/configs/igep0032_defconfig
@@ -10,6 +10,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_ONENAND_SUPPORT=y
diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig
index d1a2756..c16f631 100644
--- a/configs/imx6qdl_icore_mmc_defconfig
+++ b/configs/imx6qdl_icore_mmc_defconfig
@@ -18,6 +18,7 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="icorem6qdl> "
diff --git a/configs/imx6qdl_icore_nand_defconfig b/configs/imx6qdl_icore_nand_defconfig
index 52f691a..4ed7263 100644
--- a/configs/imx6qdl_icore_nand_defconfig
+++ b/configs/imx6qdl_icore_nand_defconfig
@@ -16,6 +16,7 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="icorem6qdl> "
diff --git a/configs/imx6qdl_icore_rqs_defconfig b/configs/imx6qdl_icore_rqs_defconfig
index 80205fe..c9c6e19 100644
--- a/configs/imx6qdl_icore_rqs_defconfig
+++ b/configs/imx6qdl_icore_rqs_defconfig
@@ -16,6 +16,7 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="icorem6qdl-rqs> "
diff --git a/configs/imx6ul_geam_mmc_defconfig b/configs/imx6ul_geam_mmc_defconfig
index c956f07..d1d001d 100644
--- a/configs/imx6ul_geam_mmc_defconfig
+++ b/configs/imx6ul_geam_mmc_defconfig
@@ -16,6 +16,7 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="geam6ul> "
diff --git a/configs/imx6ul_geam_nand_defconfig b/configs/imx6ul_geam_nand_defconfig
index 1f0cc60..a0f29f8 100644
--- a/configs/imx6ul_geam_nand_defconfig
+++ b/configs/imx6ul_geam_nand_defconfig
@@ -15,6 +15,7 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="geam6ul> "
diff --git a/configs/imx6ul_isiot_emmc_defconfig b/configs/imx6ul_isiot_emmc_defconfig
index 467a18c..58a3740 100644
--- a/configs/imx6ul_isiot_emmc_defconfig
+++ b/configs/imx6ul_isiot_emmc_defconfig
@@ -16,6 +16,7 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="isiotmx6ul> "
diff --git a/configs/imx6ul_isiot_mmc_defconfig b/configs/imx6ul_isiot_mmc_defconfig
index 4bb75f7..073e56f 100644
--- a/configs/imx6ul_isiot_mmc_defconfig
+++ b/configs/imx6ul_isiot_mmc_defconfig
@@ -16,6 +16,7 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="isiotmx6ul> "
diff --git a/configs/imx6ul_isiot_nand_defconfig b/configs/imx6ul_isiot_nand_defconfig
index fce0b0d..43c4d34 100644
--- a/configs/imx6ul_isiot_nand_defconfig
+++ b/configs/imx6ul_isiot_nand_defconfig
@@ -15,6 +15,7 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="isiotmx6ul> "
diff --git a/configs/inet1_defconfig b/configs/inet1_defconfig
index d1bebc2..994e8f3 100644
--- a/configs/inet1_defconfig
+++ b/configs/inet1_defconfig
@@ -14,6 +14,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet1"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/inet86dz_defconfig b/configs/inet86dz_defconfig
index 7940d97..e0ad6051 100644
--- a/configs/inet86dz_defconfig
+++ b/configs/inet86dz_defconfig
@@ -16,6 +16,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-inet86dz"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/inet97fv2_defconfig b/configs/inet97fv2_defconfig
index 4f1a7b5..0e1c149 100644
--- a/configs/inet97fv2_defconfig
+++ b/configs/inet97fv2_defconfig
@@ -13,6 +13,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet97fv2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/inet98v_rev2_defconfig b/configs/inet98v_rev2_defconfig
index 2afe3be..1281187 100644
--- a/configs/inet98v_rev2_defconfig
+++ b/configs/inet98v_rev2_defconfig
@@ -15,6 +15,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-inet-98v-rev2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/inet9f_rev03_defconfig b/configs/inet9f_rev03_defconfig
index ae732fa..f0baa26 100644
--- a/configs/inet9f_rev03_defconfig
+++ b/configs/inet9f_rev03_defconfig
@@ -13,6 +13,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet9f-rev03"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/inet_q972_defconfig b/configs/inet_q972_defconfig
index d436005..8619309 100644
--- a/configs/inet_q972_defconfig
+++ b/configs/inet_q972_defconfig
@@ -15,6 +15,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PH13"
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-inet-q972"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/ipam390_defconfig b/configs/ipam390_defconfig
index 4709084..215ed9d 100644
--- a/configs/ipam390_defconfig
+++ b/configs/ipam390_defconfig
@@ -12,6 +12,7 @@ CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="board/$(BOARDDIR)/u-boot-spl-ipam390.lds"
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/jesurun_q5_defconfig b/configs/jesurun_q5_defconfig
index 822d56b..c9d6770 100644
--- a/configs/jesurun_q5_defconfig
+++ b/configs/jesurun_q5_defconfig
@@ -8,6 +8,7 @@ CONFIG_VIDEO_COMPOSITE=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-jesurun-q5"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/kc1_defconfig b/configs/kc1_defconfig
index c680bb1..4c007e9 100644
--- a/configs/kc1_defconfig
+++ b/configs/kc1_defconfig
@@ -6,6 +6,7 @@ CONFIG_TARGET_KC1=y
CONFIG_ENV_IS_NOWHERE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=2
diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig
index e725e10..2ee83b8 100644
--- a/configs/kylin-rk3036_defconfig
+++ b/configs/kylin-rk3036_defconfig
@@ -7,8 +7,8 @@ CONFIG_ROCKCHIP_RK3036=y
CONFIG_TARGET_KYLIN_RK3036=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk"
-CONFIG_ENV_IS_IN_MMC=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x0
+CONFIG_ENV_IS_IN_MMC=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_STACK_R=y
# CONFIG_CMD_IMLS is not set
diff --git a/configs/liteboard_defconfig b/configs/liteboard_defconfig
index 2be4819..4080457 100644
--- a/configs/liteboard_defconfig
+++ b/configs/liteboard_defconfig
@@ -13,6 +13,7 @@ CONFIG_BOOTDELAY=1
CONFIG_DEFAULT_FDT_FILE="imx6ul-liteboard.dtb"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig
index b1d1fad..b1b92e9 100644
--- a/configs/ls1021aiot_sdcard_defconfig
+++ b/configs/ls1021aiot_sdcard_defconfig
@@ -5,6 +5,7 @@ CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/$(ARCH)/cpu/u-boot-spl.lds"
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_CMD_GPT=y
diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig
index 2107709..fd457b6 100644
--- a/configs/ls1021aqds_nand_defconfig
+++ b/configs/ls1021aqds_nand_defconfig
@@ -20,6 +20,7 @@ CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/$(ARCH)/cpu/u-boot-spl.lds"
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig
index c36a632..f9d6c92 100644
--- a/configs/ls1021aqds_sdcard_ifc_defconfig
+++ b/configs/ls1021aqds_sdcard_ifc_defconfig
@@ -18,6 +18,7 @@ CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/$(ARCH)/cpu/u-boot-spl.lds"
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig
index ae55f00..d44f828 100644
--- a/configs/ls1021aqds_sdcard_qspi_defconfig
+++ b/configs/ls1021aqds_sdcard_qspi_defconfig
@@ -18,6 +18,7 @@ CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/$(ARCH)/cpu/u-boot-spl.lds"
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
index d13652a..40ab81e 100644
--- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
@@ -19,6 +19,7 @@ CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/$(ARCH)/cpu/u-boot-spl.lds"
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_CRYPTO_SUPPORT=y
diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig
index b87a6d3..aa75457 100644
--- a/configs/ls1021atwr_sdcard_ifc_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_defconfig
@@ -19,6 +19,7 @@ CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/$(ARCH)/cpu/u-boot-spl.lds"
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig
index 9ab9e25..2553494 100644
--- a/configs/ls1021atwr_sdcard_qspi_defconfig
+++ b/configs/ls1021atwr_sdcard_qspi_defconfig
@@ -19,6 +19,7 @@ CONFIG_SILENT_CONSOLE=y
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/$(ARCH)/cpu/u-boot-spl.lds"
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig
index c0b1170..159b2b1 100644
--- a/configs/ls1043aqds_nand_defconfig
+++ b/configs/ls1043aqds_nand_defconfig
@@ -15,6 +15,7 @@ CONFIG_NAND_BOOT=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot-spl.lds"
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig
index f328dbd..cfd1618 100644
--- a/configs/ls1043aqds_sdcard_ifc_defconfig
+++ b/configs/ls1043aqds_sdcard_ifc_defconfig
@@ -15,6 +15,7 @@ CONFIG_SD_BOOT=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot-spl.lds"
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig
index af06553..217e135 100644
--- a/configs/ls1043aqds_sdcard_qspi_defconfig
+++ b/configs/ls1043aqds_sdcard_qspi_defconfig
@@ -15,6 +15,7 @@ CONFIG_SD_BOOT=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot-spl.lds"
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
index 957f2c7..29aff02 100644
--- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
@@ -15,6 +15,7 @@ CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot-spl.lds"
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
CONFIG_SPL_CRYPTO_SUPPORT=y
diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig
index c055097e..d343d4a 100644
--- a/configs/ls1043ardb_nand_defconfig
+++ b/configs/ls1043ardb_nand_defconfig
@@ -15,6 +15,7 @@ CONFIG_NAND_BOOT=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot-spl.lds"
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
index 4e959bf..f67bb66 100644
--- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
@@ -15,6 +15,7 @@ CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot-spl.lds"
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
CONFIG_SPL_CRYPTO_SUPPORT=y
diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig
index 93704f7..49ac6a7 100644
--- a/configs/ls1043ardb_sdcard_defconfig
+++ b/configs/ls1043ardb_sdcard_defconfig
@@ -16,6 +16,7 @@ CONFIG_SD_BOOT=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot-spl.lds"
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig
index a7ae7e5..b8badd7 100644
--- a/configs/ls1046aqds_nand_defconfig
+++ b/configs/ls1046aqds_nand_defconfig
@@ -9,6 +9,7 @@ CONFIG_NAND_BOOT=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot-spl.lds"
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig
index 274f91e..f8243c2 100644
--- a/configs/ls1046aqds_sdcard_ifc_defconfig
+++ b/configs/ls1046aqds_sdcard_ifc_defconfig
@@ -9,6 +9,7 @@ CONFIG_SD_BOOT=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot-spl.lds"
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig
index fd916a5..4d51896 100644
--- a/configs/ls1046aqds_sdcard_qspi_defconfig
+++ b/configs/ls1046aqds_sdcard_qspi_defconfig
@@ -9,6 +9,7 @@ CONFIG_SD_BOOT=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot-spl.lds"
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig
index 5fac89b..b52137f 100644
--- a/configs/ls1046ardb_emmc_defconfig
+++ b/configs/ls1046ardb_emmc_defconfig
@@ -9,6 +9,7 @@ CONFIG_SD_BOOT=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot-spl.lds"
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
index 5162c2c..547d989 100644
--- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
@@ -9,6 +9,7 @@ CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL"
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot-spl.lds"
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
CONFIG_SPL_CRYPTO_SUPPORT=y
diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig
index 904116c..3ba8cf3 100644
--- a/configs/ls1046ardb_sdcard_defconfig
+++ b/configs/ls1046ardb_sdcard_defconfig
@@ -10,6 +10,7 @@ CONFIG_SD_BOOT=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot-spl.lds"
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig
index b8c6e6a..4d05139 100644
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -15,6 +15,7 @@ CONFIG_NAND_BOOT=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot-spl.lds"
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/ls2080aqds_sdcard_defconfig b/configs/ls2080aqds_sdcard_defconfig
index 64682b0..54e8168 100644
--- a/configs/ls2080aqds_sdcard_defconfig
+++ b/configs/ls2080aqds_sdcard_defconfig
@@ -15,6 +15,7 @@ CONFIG_SD_BOOT=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot-spl.lds"
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig
index c4a56be..47652f0 100644
--- a/configs/ls2080ardb_nand_defconfig
+++ b/configs/ls2080ardb_nand_defconfig
@@ -15,6 +15,7 @@ CONFIG_NAND_BOOT=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot-spl.lds"
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
diff --git a/configs/m28evk_defconfig b/configs/m28evk_defconfig
index 5fc5dd3..fe45078 100644
--- a/configs/m28evk_defconfig
+++ b/configs/m28evk_defconfig
@@ -15,6 +15,7 @@ CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
diff --git a/configs/ma5d4evk_defconfig b/configs/ma5d4evk_defconfig
index c18f759..eba3a37 100644
--- a/configs/ma5d4evk_defconfig
+++ b/configs/ma5d4evk_defconfig
@@ -15,6 +15,7 @@ CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-at91/armv7/u-boot-spl.lds"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
diff --git a/configs/mccmon6_nor_defconfig b/configs/mccmon6_nor_defconfig
index 449804b..732990a 100644
--- a/configs/mccmon6_nor_defconfig
+++ b/configs/mccmon6_nor_defconfig
@@ -8,6 +8,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_nor.cfg,MX6QDL"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_NOR_SUPPORT=y
diff --git a/configs/mccmon6_sd_defconfig b/configs/mccmon6_sd_defconfig
index 653f258..f7ea557 100644
--- a/configs/mccmon6_sd_defconfig
+++ b/configs/mccmon6_sd_defconfig
@@ -9,6 +9,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/liebherr/mccmon6/mon6_imximage_sd.cfg,MX6QDL"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_NOR_SUPPORT=y
diff --git a/configs/mcx_defconfig b/configs/mcx_defconfig
index 5a9d7cc..8bb8a55 100644
--- a/configs/mcx_defconfig
+++ b/configs/mcx_defconfig
@@ -9,6 +9,7 @@ CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="mcx # "
diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig
index 3d84cf2..8d1eae4 100644
--- a/configs/microblaze-generic_defconfig
+++ b/configs/microblaze-generic_defconfig
@@ -14,6 +14,7 @@ CONFIG_FIT_VERBOSE=y
CONFIG_BOOTDELAY=-1
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/microblaze/cpu/u-boot-spl.lds"
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_NOR_SUPPORT=y
diff --git a/configs/mixtile_loftq_defconfig b/configs/mixtile_loftq_defconfig
index 6264b3a..fd19b23 100644
--- a/configs/mixtile_loftq_defconfig
+++ b/configs/mixtile_loftq_defconfig
@@ -9,6 +9,7 @@ CONFIG_USB2_VBUS_PIN=""
CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mixtile-loftq"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/mk802_a10s_defconfig b/configs/mk802_a10s_defconfig
index 69e9cfd..f37bd62 100644
--- a/configs/mk802_a10s_defconfig
+++ b/configs/mk802_a10s_defconfig
@@ -7,6 +7,7 @@ CONFIG_USB1_VBUS_PIN="PB10"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-mk802"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/mk802_defconfig b/configs/mk802_defconfig
index da9728a..eedd382 100644
--- a/configs/mk802_defconfig
+++ b/configs/mk802_defconfig
@@ -5,6 +5,7 @@ CONFIG_USB2_VBUS_PIN="PH12"
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/mk802ii_defconfig b/configs/mk802ii_defconfig
index c55f1f3..97a0e68 100644
--- a/configs/mk802ii_defconfig
+++ b/configs/mk802ii_defconfig
@@ -4,6 +4,7 @@ CONFIG_MACH_SUN4I=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802ii"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/mt_ventoux_defconfig b/configs/mt_ventoux_defconfig
index ef7d153..39186e5 100644
--- a/configs/mt_ventoux_defconfig
+++ b/configs/mt_ventoux_defconfig
@@ -8,6 +8,7 @@ CONFIG_BOOTDELAY=10
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="mt_ventoux => "
diff --git a/configs/mx23_olinuxino_defconfig b/configs/mx23_olinuxino_defconfig
index 169cd6a..c88506f 100644
--- a/configs/mx23_olinuxino_defconfig
+++ b/configs/mx23_olinuxino_defconfig
@@ -10,6 +10,7 @@ CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/mx23evk_defconfig b/configs/mx23evk_defconfig
index c70035d..03b1ec2 100644
--- a/configs/mx23evk_defconfig
+++ b/configs/mx23evk_defconfig
@@ -13,6 +13,7 @@ CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
diff --git a/configs/mx28evk_auart_console_defconfig b/configs/mx28evk_auart_console_defconfig
index 4945947..b3986ef 100644
--- a/configs/mx28evk_auart_console_defconfig
+++ b/configs/mx28evk_auart_console_defconfig
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
diff --git a/configs/mx28evk_defconfig b/configs/mx28evk_defconfig
index b85b8b5..4504bf5 100644
--- a/configs/mx28evk_defconfig
+++ b/configs/mx28evk_defconfig
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
diff --git a/configs/mx28evk_nand_defconfig b/configs/mx28evk_nand_defconfig
index 43d7599..f61d7cb 100644
--- a/configs/mx28evk_nand_defconfig
+++ b/configs/mx28evk_nand_defconfig
@@ -13,6 +13,7 @@ CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
diff --git a/configs/mx28evk_spi_defconfig b/configs/mx28evk_spi_defconfig
index 80b9ad2..1e68cac 100644
--- a/configs/mx28evk_spi_defconfig
+++ b/configs/mx28evk_spi_defconfig
@@ -13,6 +13,7 @@ CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
diff --git a/configs/mx31pdk_defconfig b/configs/mx31pdk_defconfig
index 5b8523a..716bcf6 100644
--- a/configs/mx31pdk_defconfig
+++ b/configs/mx31pdk_defconfig
@@ -8,6 +8,7 @@ CONFIG_SPL_NAND_SUPPORT=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=1
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/$(ARCH)/cpu/u-boot-spl.lds"
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_SPI=y
diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig
index f0b6679..d202af9 100644
--- a/configs/mx6cuboxi_defconfig
+++ b/configs/mx6cuboxi_defconfig
@@ -17,6 +17,7 @@ CONFIG_ENV_IS_IN_MMC=y
# CONFIG_SYS_STDIO_DEREGISTER is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig
index 27577d6..dfc6c2f 100644
--- a/configs/mx6sabreauto_defconfig
+++ b/configs/mx6sabreauto_defconfig
@@ -16,6 +16,7 @@ CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig
index 627bf52..27be145 100644
--- a/configs/mx6sabresd_defconfig
+++ b/configs/mx6sabresd_defconfig
@@ -16,6 +16,7 @@ CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
diff --git a/configs/mx6slevk_spl_defconfig b/configs/mx6slevk_spl_defconfig
index a241ade..bde648b 100644
--- a/configs/mx6slevk_spl_defconfig
+++ b/configs/mx6slevk_spl_defconfig
@@ -14,6 +14,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/mx6sxsabresd_spl_defconfig b/configs/mx6sxsabresd_spl_defconfig
index 90daa96..48623f9 100644
--- a/configs/mx6sxsabresd_spl_defconfig
+++ b/configs/mx6sxsabresd_spl_defconfig
@@ -15,6 +15,7 @@ CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig
index 87419cd..a0a442a 100644
--- a/configs/mx6ul_14x14_evk_defconfig
+++ b/configs/mx6ul_14x14_evk_defconfig
@@ -16,6 +16,7 @@ CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig
index c58f6dc..719384d 100644
--- a/configs/mx6ul_9x9_evk_defconfig
+++ b/configs/mx6ul_9x9_evk_defconfig
@@ -16,6 +16,7 @@ CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/nanopi_m1_defconfig b/configs/nanopi_m1_defconfig
index 498496b..4414332 100644
--- a/configs/nanopi_m1_defconfig
+++ b/configs/nanopi_m1_defconfig
@@ -7,6 +7,7 @@ CONFIG_DRAM_ODT_EN=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-m1"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/nanopi_m1_plus_defconfig b/configs/nanopi_m1_plus_defconfig
index d7a908d..eadbf3b 100644
--- a/configs/nanopi_m1_plus_defconfig
+++ b/configs/nanopi_m1_plus_defconfig
@@ -9,6 +9,7 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-m1-plus"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/nanopi_neo_air_defconfig b/configs/nanopi_neo_air_defconfig
index a73640e..bc5331a 100644
--- a/configs/nanopi_neo_air_defconfig
+++ b/configs/nanopi_neo_air_defconfig
@@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-neo-air"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONSOLE_MUX=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/nanopi_neo_defconfig b/configs/nanopi_neo_defconfig
index 8b55497..49d42c9 100644
--- a/configs/nanopi_neo_defconfig
+++ b/configs/nanopi_neo_defconfig
@@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-neo"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONSOLE_MUX=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/novena_defconfig b/configs/novena_defconfig
index 23c186b..f171504 100644
--- a/configs/novena_defconfig
+++ b/configs/novena_defconfig
@@ -19,6 +19,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
diff --git a/configs/omap3_beagle_defconfig b/configs/omap3_beagle_defconfig
index 72a4ef1..09d8635 100644
--- a/configs/omap3_beagle_defconfig
+++ b/configs/omap3_beagle_defconfig
@@ -7,6 +7,7 @@ CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
# CONFIG_CMD_IMLS is not set
diff --git a/configs/omap3_evm_defconfig b/configs/omap3_evm_defconfig
index d7bbf2d..4266561 100644
--- a/configs/omap3_evm_defconfig
+++ b/configs/omap3_evm_defconfig
@@ -5,6 +5,7 @@ CONFIG_TARGET_OMAP3_EVM=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="OMAP3_EVM # "
diff --git a/configs/omap3_ha_defconfig b/configs/omap3_ha_defconfig
index c51309c..45745b4 100644
--- a/configs/omap3_ha_defconfig
+++ b/configs/omap3_ha_defconfig
@@ -6,6 +6,7 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_BOARD_OMAP3_HA"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMI is not set
diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig
index 58b5ecd..36e8ef6 100644
--- a/configs/omap3_logic_defconfig
+++ b/configs/omap3_logic_defconfig
@@ -10,6 +10,7 @@ CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_MTD_SUPPORT=y
diff --git a/configs/omap3_overo_defconfig b/configs/omap3_overo_defconfig
index be2447b..3403116 100644
--- a/configs/omap3_overo_defconfig
+++ b/configs/omap3_overo_defconfig
@@ -7,6 +7,7 @@ CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_MTD_SUPPORT=y
diff --git a/configs/omap4_panda_defconfig b/configs/omap4_panda_defconfig
index 22fe337..933bff1 100644
--- a/configs/omap4_panda_defconfig
+++ b/configs/omap4_panda_defconfig
@@ -9,6 +9,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
# CONFIG_SPL_EXT_SUPPORT is not set
# CONFIG_SPL_I2C_SUPPORT is not set
CONFIG_SPL_OS_BOOT=y
diff --git a/configs/omap4_sdp4430_defconfig b/configs/omap4_sdp4430_defconfig
index 04198e5..dc91b07 100644
--- a/configs/omap4_sdp4430_defconfig
+++ b/configs/omap4_sdp4430_defconfig
@@ -12,6 +12,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
# CONFIG_SPL_I2C_SUPPORT is not set
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
diff --git a/configs/omap5_uevm_defconfig b/configs/omap5_uevm_defconfig
index 635bdf7..c036a85 100644
--- a/configs/omap5_uevm_defconfig
+++ b/configs/omap5_uevm_defconfig
@@ -9,6 +9,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
@@ -33,10 +34,10 @@ CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ISO_PARTITION=y
+CONFIG_SCSI=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_MMC_OMAP_HS=y
-CONFIG_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig
index 282725f..bacf123 100644
--- a/configs/omapl138_lcdk_defconfig
+++ b/configs/omapl138_lcdk_defconfig
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="board/$(BOARDDIR)/u-boot-spl-da850evm.lds"
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xb5
CONFIG_HUSH_PARSER=y
diff --git a/configs/opos6uldev_defconfig b/configs/opos6uldev_defconfig
index b9dab54..0dfea80 100644
--- a/configs/opos6uldev_defconfig
+++ b/configs/opos6uldev_defconfig
@@ -17,6 +17,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_DEFAULT_FDT_FILE="imx6ul-opos6uldev.dtb"
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/orangepi_2_defconfig b/configs/orangepi_2_defconfig
index dffba8c..d80e5ba 100644
--- a/configs/orangepi_2_defconfig
+++ b/configs/orangepi_2_defconfig
@@ -9,6 +9,7 @@ CONFIG_USB1_VBUS_PIN="PG13"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/orangepi_lite_defconfig b/configs/orangepi_lite_defconfig
index 448a161..0e51ca6 100644
--- a/configs/orangepi_lite_defconfig
+++ b/configs/orangepi_lite_defconfig
@@ -7,6 +7,7 @@ CONFIG_DRAM_ODT_EN=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-lite"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/orangepi_one_defconfig b/configs/orangepi_one_defconfig
index 97d0e06..05ab73f 100644
--- a/configs/orangepi_one_defconfig
+++ b/configs/orangepi_one_defconfig
@@ -7,6 +7,7 @@ CONFIG_DRAM_ODT_EN=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-one"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig
index af7568f..2bd0df0 100644
--- a/configs/orangepi_pc_defconfig
+++ b/configs/orangepi_pc_defconfig
@@ -7,6 +7,7 @@ CONFIG_DRAM_ODT_EN=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/orangepi_pc_plus_defconfig b/configs/orangepi_pc_plus_defconfig
index 935e96d..0c68397 100644
--- a/configs/orangepi_pc_plus_defconfig
+++ b/configs/orangepi_pc_plus_defconfig
@@ -8,6 +8,7 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc-plus"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/orangepi_plus2e_defconfig b/configs/orangepi_plus2e_defconfig
index 3301ca0..bf269ca 100644
--- a/configs/orangepi_plus2e_defconfig
+++ b/configs/orangepi_plus2e_defconfig
@@ -9,6 +9,7 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus2e"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig
index 34c5750..1ed7264 100644
--- a/configs/orangepi_plus_defconfig
+++ b/configs/orangepi_plus_defconfig
@@ -11,6 +11,7 @@ CONFIG_SATAPWR="PG11"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/orangepi_zero_defconfig b/configs/orangepi_zero_defconfig
index c650ce8..1f3a6bc 100644
--- a/configs/orangepi_zero_defconfig
+++ b/configs/orangepi_zero_defconfig
@@ -10,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-orangepi-zero"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONSOLE_MUX=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/origen_defconfig b/configs/origen_defconfig
index 573c9e2..08864e4 100644
--- a/configs/origen_defconfig
+++ b/configs/origen_defconfig
@@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="exynos4210-origen"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="board/samsung/common/exynos-uboot-spl.lds"
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="ORIGEN # "
CONFIG_CMD_BOOTZ=y
diff --git a/configs/ot1200_spl_defconfig b/configs/ot1200_spl_defconfig
index 50be468..5560327 100644
--- a/configs/ot1200_spl_defconfig
+++ b/configs/ot1200_spl_defconfig
@@ -13,6 +13,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
diff --git a/configs/parrot_r16_defconfig b/configs/parrot_r16_defconfig
index 76e4e34..faddf5c 100644
--- a/configs/parrot_r16_defconfig
+++ b/configs/parrot_r16_defconfig
@@ -12,6 +12,7 @@ CONFIG_AXP_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-r16-parrot"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/pcm051_rev1_defconfig b/configs/pcm051_rev1_defconfig
index 6571876..d643fba 100644
--- a/configs/pcm051_rev1_defconfig
+++ b/configs/pcm051_rev1_defconfig
@@ -16,6 +16,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_ETH_SUPPORT=y
CONFIG_SPL_EXT_SUPPORT=y
diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig
index a622359..07e9092 100644
--- a/configs/pcm051_rev3_defconfig
+++ b/configs/pcm051_rev3_defconfig
@@ -16,6 +16,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_ETH_SUPPORT=y
CONFIG_SPL_EXT_SUPPORT=y
diff --git a/configs/pcm058_defconfig b/configs/pcm058_defconfig
index dc3fed7..7977fa0 100644
--- a/configs/pcm058_defconfig
+++ b/configs/pcm058_defconfig
@@ -17,6 +17,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig
index b84c3de..b225817 100644
--- a/configs/peach-pi_defconfig
+++ b/configs/peach-pi_defconfig
@@ -10,6 +10,7 @@ CONFIG_FIT_BEST_MATCH=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SILENT_CONSOLE=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="board/samsung/common/exynos-uboot-spl.lds"
CONFIG_SYS_PROMPT="Peach-Pi # "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MMC=y
diff --git a/configs/peach-pit_defconfig b/configs/peach-pit_defconfig
index a0f443e..85d1bed 100644
--- a/configs/peach-pit_defconfig
+++ b/configs/peach-pit_defconfig
@@ -10,6 +10,7 @@ CONFIG_FIT_BEST_MATCH=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SILENT_CONSOLE=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="board/samsung/common/exynos-uboot-spl.lds"
CONFIG_SYS_PROMPT="Peach-Pit # "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MMC=y
diff --git a/configs/pengwyn_defconfig b/configs/pengwyn_defconfig
index f94f0f9..9c7ab02 100644
--- a/configs/pengwyn_defconfig
+++ b/configs/pengwyn_defconfig
@@ -16,6 +16,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_ETH_SUPPORT=y
CONFIG_SPL_EXT_SUPPORT=y
diff --git a/configs/pepper_defconfig b/configs/pepper_defconfig
index 106be0d..7133c1f 100644
--- a/configs/pepper_defconfig
+++ b/configs/pepper_defconfig
@@ -14,6 +14,7 @@ CONFIG_ENV_IS_NOWHERE=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
diff --git a/configs/picosam9g45_defconfig b/configs/picosam9g45_defconfig
index 326158d..3824bd6 100644
--- a/configs/picosam9g45_defconfig
+++ b/configs/picosam9g45_defconfig
@@ -17,6 +17,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-at91/arm926ejs/u-boot-spl.lds"
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
# CONFIG_CMD_BDI is not set
diff --git a/configs/platinum_picon_defconfig b/configs/platinum_picon_defconfig
index d39d686..c600f02 100644
--- a/configs/platinum_picon_defconfig
+++ b/configs/platinum_picon_defconfig
@@ -14,6 +14,7 @@ CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
diff --git a/configs/platinum_titanium_defconfig b/configs/platinum_titanium_defconfig
index 356c6ed..79f0913 100644
--- a/configs/platinum_titanium_defconfig
+++ b/configs/platinum_titanium_defconfig
@@ -14,6 +14,7 @@ CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
diff --git a/configs/polaroid_mid2407pxe03_defconfig b/configs/polaroid_mid2407pxe03_defconfig
index d48a507..fef4e55 100644
--- a/configs/polaroid_mid2407pxe03_defconfig
+++ b/configs/polaroid_mid2407pxe03_defconfig
@@ -16,6 +16,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-polaroid-mid2407pxe03"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/polaroid_mid2809pxe04_defconfig b/configs/polaroid_mid2809pxe04_defconfig
index 72fe096..c416624 100644
--- a/configs/polaroid_mid2809pxe04_defconfig
+++ b/configs/polaroid_mid2809pxe04_defconfig
@@ -16,6 +16,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-polaroid-mid2809pxe04"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/pov_protab2_ips9_defconfig b/configs/pov_protab2_ips9_defconfig
index d4af808..6345946 100644
--- a/configs/pov_protab2_ips9_defconfig
+++ b/configs/pov_protab2_ips9_defconfig
@@ -14,6 +14,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-pov-protab2-ips9"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig
index 404fbd6..4202f6e 100644
--- a/configs/puma-rk3399_defconfig
+++ b/configs/puma-rk3399_defconfig
@@ -84,13 +84,13 @@ CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_STORAGE=y
-CONFIG_DM_VIDEO=y
-CONFIG_DISPLAY=y
-CONFIG_VIDEO_ROCKCHIP=y
-CONFIG_DISPLAY_ROCKCHIP_HDMI=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="Theobroma Systems"
CONFIG_G_DNL_VENDOR_NUM=0x2294
CONFIG_G_DNL_PRODUCT_NUM=0x3399
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_DISPLAY_ROCKCHIP_HDMI=y
CONFIG_ERRNO_STR=y
diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig
index ac2d4bb..04dbbd0 100644
--- a/configs/pxm2_defconfig
+++ b/configs/pxm2_defconfig
@@ -25,6 +25,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/q8_a13_tablet_defconfig b/configs/q8_a13_tablet_defconfig
index 5115739..34e0708 100644
--- a/configs/q8_a13_tablet_defconfig
+++ b/configs/q8_a13_tablet_defconfig
@@ -15,6 +15,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-q8-tablet"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/q8_a23_tablet_800x480_defconfig b/configs/q8_a23_tablet_800x480_defconfig
index 1762fe4..9119d23 100644
--- a/configs/q8_a23_tablet_800x480_defconfig
+++ b/configs/q8_a23_tablet_800x480_defconfig
@@ -16,6 +16,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-q8-tablet"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/q8_a33_tablet_1024x600_defconfig b/configs/q8_a33_tablet_1024x600_defconfig
index d42b597..39b515d 100644
--- a/configs/q8_a33_tablet_1024x600_defconfig
+++ b/configs/q8_a33_tablet_1024x600_defconfig
@@ -16,6 +16,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-q8-tablet"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/q8_a33_tablet_800x480_defconfig b/configs/q8_a33_tablet_800x480_defconfig
index 5b6dfe0..74ca72c 100644
--- a/configs/q8_a33_tablet_800x480_defconfig
+++ b/configs/q8_a33_tablet_800x480_defconfig
@@ -16,6 +16,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-q8-tablet"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig
index fc1c70d..aee1caf 100644
--- a/configs/qemu-x86_64_defconfig
+++ b/configs/qemu-x86_64_defconfig
@@ -71,6 +71,7 @@ CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
CONFIG_SYS_NS16550=y
CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/r7-tv-dongle_defconfig b/configs/r7-tv-dongle_defconfig
index 4817e6c..105ef01 100644
--- a/configs/r7-tv-dongle_defconfig
+++ b/configs/r7-tv-dongle_defconfig
@@ -6,6 +6,7 @@ CONFIG_USB1_VBUS_PIN="PG13"
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-r7-tv-dongle"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/rastaban_defconfig b/configs/rastaban_defconfig
index cc40f91..cebefe0 100644
--- a/configs/rastaban_defconfig
+++ b/configs/rastaban_defconfig
@@ -22,6 +22,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/rut_defconfig b/configs/rut_defconfig
index 9220458..359c437 100644
--- a/configs/rut_defconfig
+++ b/configs/rut_defconfig
@@ -26,6 +26,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_ARCH_EARLY_INIT_R=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig
index e9a65cc..f2c1113 100644
--- a/configs/sama5d2_xplained_mmc_defconfig
+++ b/configs/sama5d2_xplained_mmc_defconfig
@@ -18,6 +18,7 @@ CONFIG_ENV_IS_IN_FAT=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-at91/armv7/u-boot-spl.lds"
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig
index acd7499..f121316 100644
--- a/configs/sama5d3_xplained_mmc_defconfig
+++ b/configs/sama5d3_xplained_mmc_defconfig
@@ -18,6 +18,7 @@ CONFIG_ENV_IS_IN_FAT=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-at91/armv7/u-boot-spl.lds"
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig
index 1836e53..66a376a 100644
--- a/configs/sama5d3xek_mmc_defconfig
+++ b/configs/sama5d3xek_mmc_defconfig
@@ -20,6 +20,7 @@ CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-at91/armv7/u-boot-spl.lds"
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig
index 094e5e1..f0119da 100644
--- a/configs/sama5d4_xplained_mmc_defconfig
+++ b/configs/sama5d4_xplained_mmc_defconfig
@@ -18,6 +18,7 @@ CONFIG_ENV_IS_IN_FAT=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-at91/armv7/u-boot-spl.lds"
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig
index a3909a0..23bfa3e 100644
--- a/configs/sama5d4ek_mmc_defconfig
+++ b/configs/sama5d4ek_mmc_defconfig
@@ -20,6 +20,7 @@ CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-at91/armv7/u-boot-spl.lds"
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
diff --git a/configs/sansa_fuze_plus_defconfig b/configs/sansa_fuze_plus_defconfig
index 0da8d52..f6228b5 100644
--- a/configs/sansa_fuze_plus_defconfig
+++ b/configs/sansa_fuze_plus_defconfig
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMTEST=y
diff --git a/configs/sc_sps_1_defconfig b/configs/sc_sps_1_defconfig
index 4320421..ac3b7ec 100644
--- a/configs/sc_sps_1_defconfig
+++ b/configs/sc_sps_1_defconfig
@@ -11,6 +11,7 @@ CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig
index b111cf7..9b55c94 100644
--- a/configs/smartweb_defconfig
+++ b/configs/smartweb_defconfig
@@ -17,6 +17,7 @@ CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-at91/arm926ejs/u-boot-spl.lds"
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot# "
CONFIG_AUTOBOOT_KEYED=y
diff --git a/configs/smdk5250_defconfig b/configs/smdk5250_defconfig
index 356600f..90cb97d 100644
--- a/configs/smdk5250_defconfig
+++ b/configs/smdk5250_defconfig
@@ -13,6 +13,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="board/samsung/common/exynos-uboot-spl.lds"
CONFIG_SYS_PROMPT="SMDK5250 # "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MMC=y
diff --git a/configs/smdk5420_defconfig b/configs/smdk5420_defconfig
index 6a2ea20..8c138a4 100644
--- a/configs/smdk5420_defconfig
+++ b/configs/smdk5420_defconfig
@@ -11,6 +11,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="board/samsung/common/exynos-uboot-spl.lds"
CONFIG_SYS_PROMPT="SMDK5420 # "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MMC=y
diff --git a/configs/smdkv310_defconfig b/configs/smdkv310_defconfig
index 5e9f181..0a811f9 100644
--- a/configs/smdkv310_defconfig
+++ b/configs/smdkv310_defconfig
@@ -4,6 +4,7 @@ CONFIG_ARCH_EXYNOS4=y
CONFIG_IDENT_STRING=" for SMDKC210/V310"
CONFIG_DEFAULT_DEVICE_TREE="exynos4210-smdkv310"
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="board/samsung/common/exynos-uboot-spl.lds"
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="SMDKV310 # "
CONFIG_CMD_BOOTZ=y
diff --git a/configs/sniper_defconfig b/configs/sniper_defconfig
index f56274e..c42ee00 100644
--- a/configs/sniper_defconfig
+++ b/configs/sniper_defconfig
@@ -6,6 +6,7 @@ CONFIG_TARGET_SNIPER=y
CONFIG_ENV_IS_NOWHERE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=2
diff --git a/configs/snow_defconfig b/configs/snow_defconfig
index 5a197d1..d0234e4 100644
--- a/configs/snow_defconfig
+++ b/configs/snow_defconfig
@@ -13,6 +13,7 @@ CONFIG_FIT_BEST_MATCH=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SILENT_CONSOLE=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="board/samsung/common/exynos-uboot-spl.lds"
CONFIG_SYS_PROMPT="snow # "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MMC=y
diff --git a/configs/spring_defconfig b/configs/spring_defconfig
index 9384d9e..533f03d 100644
--- a/configs/spring_defconfig
+++ b/configs/spring_defconfig
@@ -13,6 +13,7 @@ CONFIG_FIT_BEST_MATCH=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SILENT_CONSOLE=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="board/samsung/common/exynos-uboot-spl.lds"
CONFIG_SYS_PROMPT="spring # "
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MMC=y
diff --git a/configs/sun8i_a23_evb_defconfig b/configs/sun8i_a23_evb_defconfig
index 49ba431..1019522 100644
--- a/configs/sun8i_a23_evb_defconfig
+++ b/configs/sun8i_a23_evb_defconfig
@@ -9,6 +9,7 @@ CONFIG_USB1_VBUS_PIN="PH7"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-evb"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
diff --git a/configs/sunxi_Gemei_G9_defconfig b/configs/sunxi_Gemei_G9_defconfig
index 903def1..dda6213 100644
--- a/configs/sunxi_Gemei_G9_defconfig
+++ b/configs/sunxi_Gemei_G9_defconfig
@@ -11,6 +11,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-gemei-g9"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/tao3530_defconfig b/configs/tao3530_defconfig
index a572db2..0835e11 100644
--- a/configs/tao3530_defconfig
+++ b/configs/tao3530_defconfig
@@ -5,6 +5,7 @@ CONFIG_TARGET_TAO3530=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=3
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="TAO-3530 # "
diff --git a/configs/thuban_defconfig b/configs/thuban_defconfig
index e4e99be..b28c923 100644
--- a/configs/thuban_defconfig
+++ b/configs/thuban_defconfig
@@ -22,6 +22,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/ti814x_evm_defconfig b/configs/ti814x_evm_defconfig
index d314e50..802adc4 100644
--- a/configs/ti814x_evm_defconfig
+++ b/configs/ti814x_evm_defconfig
@@ -16,6 +16,7 @@ CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_YMODEM_SUPPORT=y
diff --git a/configs/ti816x_evm_defconfig b/configs/ti816x_evm_defconfig
index 959f079..3dbd1c6 100644
--- a/configs/ti816x_evm_defconfig
+++ b/configs/ti816x_evm_defconfig
@@ -20,6 +20,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_STACK_R=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig
index 1873791..c84c1a9 100644
--- a/configs/topic_miami_defconfig
+++ b/configs/topic_miami_defconfig
@@ -10,6 +10,7 @@ CONFIG_ENV_IS_NOWHERE=y
CONFIG_BOOTDELAY=0
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-zynq/u-boot-spl.lds"
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="zynq-uboot> "
# CONFIG_CMD_IMLS is not set
diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig
index db859a7..df7ed70 100644
--- a/configs/topic_miamilite_defconfig
+++ b/configs/topic_miamilite_defconfig
@@ -10,6 +10,7 @@ CONFIG_ENV_IS_NOWHERE=y
CONFIG_BOOTDELAY=0
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-zynq/u-boot-spl.lds"
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="zynq-uboot> "
# CONFIG_CMD_IMLS is not set
diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig
index 93e0292..62c3863 100644
--- a/configs/topic_miamiplus_defconfig
+++ b/configs/topic_miamiplus_defconfig
@@ -10,6 +10,7 @@ CONFIG_ENV_IS_NOWHERE=y
CONFIG_BOOTDELAY=0
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-zynq/u-boot-spl.lds"
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="zynq-uboot> "
# CONFIG_CMD_IMLS is not set
diff --git a/configs/tricorder_defconfig b/configs/tricorder_defconfig
index dc3a572..36edb08 100644
--- a/configs/tricorder_defconfig
+++ b/configs/tricorder_defconfig
@@ -5,6 +5,7 @@ CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=0
CONFIG_SILENT_CONSOLE=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="OMAP3 Tricorder # "
# CONFIG_CMD_IMI is not set
diff --git a/configs/tricorder_flash_defconfig b/configs/tricorder_flash_defconfig
index 6e45252..3a8cdd7 100644
--- a/configs/tricorder_flash_defconfig
+++ b/configs/tricorder_flash_defconfig
@@ -6,6 +6,7 @@ CONFIG_ENV_IS_NOWHERE=y
CONFIG_BOOTDELAY=0
CONFIG_SILENT_CONSOLE=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
diff --git a/configs/ts4600_defconfig b/configs/ts4600_defconfig
index c155425..fac4b45 100644
--- a/configs/ts4600_defconfig
+++ b/configs/ts4600_defconfig
@@ -9,6 +9,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
diff --git a/configs/twister_defconfig b/configs/twister_defconfig
index 7d80a41..641968c 100644
--- a/configs/twister_defconfig
+++ b/configs/twister_defconfig
@@ -5,6 +5,7 @@ CONFIG_TARGET_TWISTER=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_BOOTDELAY=10
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/udoo_defconfig b/configs/udoo_defconfig
index 794e00c..3b42bab 100644
--- a/configs/udoo_defconfig
+++ b/configs/udoo_defconfig
@@ -13,6 +13,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/udoo_neo_defconfig b/configs/udoo_neo_defconfig
index ecc03fc..80f98ef 100644
--- a/configs/udoo_neo_defconfig
+++ b/configs/udoo_neo_defconfig
@@ -13,6 +13,7 @@ CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_EXT_SUPPORT=y
# CONFIG_CMD_IMLS is not set
diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig
index 68916a4..fa7bf0a 100644
--- a/configs/wandboard_defconfig
+++ b/configs/wandboard_defconfig
@@ -18,6 +18,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_IMLS is not set
diff --git a/configs/woodburn_sd_defconfig b/configs/woodburn_sd_defconfig
index 996247b..8e22b9e 100644
--- a/configs/woodburn_sd_defconfig
+++ b/configs/woodburn_sd_defconfig
@@ -11,6 +11,7 @@ CONFIG_ENV_IS_IN_FLASH=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/arm1136/u-boot-spl.lds"
CONFIG_SPL_BOARD_INIT=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100
diff --git a/configs/x600_defconfig b/configs/x600_defconfig
index d766614..7332911 100644
--- a/configs/x600_defconfig
+++ b/configs/x600_defconfig
@@ -12,6 +12,7 @@ CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds"
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="X600> "
diff --git a/configs/xfi3_defconfig b/configs/xfi3_defconfig
index 5a49db2..d4791a7 100644
--- a/configs/xfi3_defconfig
+++ b/configs/xfi3_defconfig
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
diff --git a/configs/xpress_spl_defconfig b/configs/xpress_spl_defconfig
index 9991725..b709a6f 100644
--- a/configs/xpress_spl_defconfig
+++ b/configs/xpress_spl_defconfig
@@ -14,6 +14,7 @@ CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/zc5202_defconfig b/configs/zc5202_defconfig
index d61ed77..66984e7 100644
--- a/configs/zc5202_defconfig
+++ b/configs/zc5202_defconfig
@@ -17,6 +17,7 @@ CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="imx6q-zc5202.dtb"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_CMD_MMC=y
diff --git a/configs/zc5601_defconfig b/configs/zc5601_defconfig
index 8b7b4a9..f897f3f 100644
--- a/configs/zc5601_defconfig
+++ b/configs/zc5601_defconfig
@@ -17,6 +17,7 @@ CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="imx6q-zc5601.dtb"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-omap2/u-boot-spl.lds"
CONFIG_SPL_EXT_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_CMD_MMC=y
diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig
index ec8eafb..aa8c7cb 100644
--- a/configs/zynq_microzed_defconfig
+++ b/configs/zynq_microzed_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-zynq/u-boot-spl.lds"
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig
index f5155b2..ff3ab66 100644
--- a/configs/zynq_picozed_defconfig
+++ b/configs/zynq_picozed_defconfig
@@ -5,6 +5,7 @@ CONFIG_DEFAULT_DEVICE_TREE="zynq-picozed"
CONFIG_ENV_IS_NOWHERE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-zynq/u-boot-spl.lds"
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig
index b850af9..fc45503 100644
--- a/configs/zynq_zc702_defconfig
+++ b/configs/zynq_zc702_defconfig
@@ -10,6 +10,7 @@ CONFIG_FIT_VERBOSE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-zynq/u-boot-spl.lds"
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig
index 35722e9..c7af974 100644
--- a/configs/zynq_zc706_defconfig
+++ b/configs/zynq_zc706_defconfig
@@ -9,6 +9,7 @@ CONFIG_FIT_VERBOSE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-zynq/u-boot-spl.lds"
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig
index 9023b2e..8f61f50 100644
--- a/configs/zynq_zc770_xm010_defconfig
+++ b/configs/zynq_zc770_xm010_defconfig
@@ -9,6 +9,7 @@ CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM010"
CONFIG_ENV_IS_IN_SPI_FLASH=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-zynq/u-boot-spl.lds"
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig
index 581998c..58b694c 100644
--- a/configs/zynq_zc770_xm011_defconfig
+++ b/configs/zynq_zc770_xm011_defconfig
@@ -10,6 +10,7 @@ CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM011"
CONFIG_ENV_IS_NOWHERE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-zynq/u-boot-spl.lds"
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig
index 4cf15d5..a2566bc 100644
--- a/configs/zynq_zc770_xm012_defconfig
+++ b/configs/zynq_zc770_xm012_defconfig
@@ -10,6 +10,7 @@ CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM012"
CONFIG_ENV_IS_IN_FLASH=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-zynq/u-boot-spl.lds"
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig
index ed016dd..21eae88 100644
--- a/configs/zynq_zc770_xm013_defconfig
+++ b/configs/zynq_zc770_xm013_defconfig
@@ -10,6 +10,7 @@ CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM013"
CONFIG_ENV_IS_NOWHERE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-zynq/u-boot-spl.lds"
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig
index 762d475..84e8c4c 100644
--- a/configs/zynq_zed_defconfig
+++ b/configs/zynq_zed_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-zynq/u-boot-spl.lds"
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig
index 4392361..f251df9 100644
--- a/configs/zynq_zybo_defconfig
+++ b/configs/zynq_zybo_defconfig
@@ -10,6 +10,7 @@ CONFIG_FIT_VERBOSE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-zynq/u-boot-spl.lds"
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index c7329cc..bfc484d 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -191,8 +191,6 @@
#define CONFIG_SYS_BOOTCOUNT_BE
/* USB gadget RNDIS */
-
-#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
#endif
#ifdef CONFIG_NAND
diff --git a/include/configs/am335x_igep003x.h b/include/configs/am335x_igep003x.h
index 4721b42..ae72543 100644
--- a/include/configs/am335x_igep003x.h
+++ b/include/configs/am335x_igep003x.h
@@ -125,7 +125,6 @@
#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(SPL),-(UBI)"
/* SPL */
-#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
/* UBI configuration */
#define CONFIG_SPL_UBI 1
diff --git a/include/configs/am335x_shc.h b/include/configs/am335x_shc.h
index f3b7767..d84d268 100644
--- a/include/configs/am335x_shc.h
+++ b/include/configs/am335x_shc.h
@@ -247,8 +247,6 @@
/* SPL */
-#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
-
#ifndef CONFIG_SPL_USBETH_SUPPORT
#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
#endif
diff --git a/include/configs/am335x_sl50.h b/include/configs/am335x_sl50.h
index 75f9bef..7ea135e 100644
--- a/include/configs/am335x_sl50.h
+++ b/include/configs/am335x_sl50.h
@@ -78,8 +78,6 @@
#define CONFIG_BOOTCOUNT_AM33XX
#define CONFIG_SYS_BOOTCOUNT_BE
-#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
-
#ifndef CONFIG_SPL_USBETH_SUPPORT
#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
#endif
diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h
index 77d9ba1..7adaf4f 100644
--- a/include/configs/am3517_crane.h
+++ b/include/configs/am3517_crane.h
@@ -262,7 +262,6 @@
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
-#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
/* NAND boot config */
#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index 26036c4..00a4668 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -309,6 +309,5 @@
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
-#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
#endif /* __CONFIG_H */
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index a91b7df..567a496 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -75,8 +75,6 @@
#define FAT_ENV_DEVICE_AND_PART "0:1"
#define FAT_ENV_FILE "uboot.env"
-#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
-
/* SPL USB Support */
#if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD)
diff --git a/include/configs/apf27.h b/include/configs/apf27.h
index b122fe6..5fa950e 100644
--- a/include/configs/apf27.h
+++ b/include/configs/apf27.h
@@ -27,7 +27,6 @@
* SPL
*/
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
#define CONFIG_SPL_MAX_SIZE 2048
#define CONFIG_SPL_TEXT_BASE 0xA0000000
diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h
index 8b00370..be4a012 100644
--- a/include/configs/at91sam9m10g45ek.h
+++ b/include/configs/at91sam9m10g45ek.h
@@ -150,7 +150,6 @@
#define CONFIG_SYS_SPL_MALLOC_START 0x70080000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000
-#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h
index e4ff019..3f6bee4 100644
--- a/include/configs/at91sam9n12ek.h
+++ b/include/configs/at91sam9n12ek.h
@@ -200,7 +200,6 @@
#define CONFIG_SYS_MCKR_CSS 0x1302
#ifdef CONFIG_SYS_USE_MMC
-#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h
index 7e8a9e9..3dbc905 100644
--- a/include/configs/at91sam9x5ek.h
+++ b/include/configs/at91sam9x5ek.h
@@ -190,7 +190,6 @@
#define CONFIG_SYS_MCKR_CSS 0x1302
#ifdef CONFIG_SYS_USE_MMC
-#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
diff --git a/include/configs/baltos.h b/include/configs/baltos.h
index 17b3a15..3df6e04 100644
--- a/include/configs/baltos.h
+++ b/include/configs/baltos.h
@@ -243,8 +243,6 @@
/* General network SPL, both CPSW and USB gadget RNDIS */
#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL"*/
-#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
-
#ifdef CONFIG_NAND
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_NAND_OMAP_GPMC_PREFETCH
diff --git a/include/configs/bav335x.h b/include/configs/bav335x.h
index fafab8e..7b6ca13 100644
--- a/include/configs/bav335x.h
+++ b/include/configs/bav335x.h
@@ -344,8 +344,6 @@ DEFAULT_LINUX_BOOT_ENV \
#define CONFIG_SYS_BOOTCOUNT_BE
/* USB gadget RNDIS */
-
-#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
#endif
#ifdef CONFIG_NAND
diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h
index 8d0e0ea..f54bb91 100644
--- a/include/configs/bur_am335x_common.h
+++ b/include/configs/bur_am335x_common.h
@@ -104,6 +104,5 @@
#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
/* General parts of the framework, required. */
-#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
#endif /* ! __BUR_AM335X_COMMON_H__ */
diff --git a/include/configs/chiliboard.h b/include/configs/chiliboard.h
index 82be3a1..f42130e 100644
--- a/include/configs/chiliboard.h
+++ b/include/configs/chiliboard.h
@@ -129,8 +129,6 @@
#define CONFIG_BOOTCOUNT_AM33XX
#define CONFIG_SYS_BOOTCOUNT_BE
-#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
-
/* NAND: device related configs */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h
index a1b8e14..552e239 100644
--- a/include/configs/cm_t335.h
+++ b/include/configs/cm_t335.h
@@ -99,7 +99,6 @@
#define CONFIG_SYS_I2C_EEPROM_BUS 0
/* SPL */
-#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
/* Network. */
#define CONFIG_PHY_GIGE
diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index 99d4800..6851cf6 100644
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -264,7 +264,6 @@
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_OMAP3_ID_NAND
-#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
/* NAND boot config */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h
index f6e0743..bcf9daa 100644
--- a/include/configs/cm_t43.h
+++ b/include/configs/cm_t43.h
@@ -101,8 +101,6 @@
#define CONFIG_ENV_OFFSET (768 * 1024)
#define CONFIG_ENV_SPI_MAX_HZ 48000000
-#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x80200000\0" \
"fdtaddr=0x81200000\0" \
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index c610ff3..21d85e7 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -298,7 +298,6 @@
CONFIG_SYS_MALLOC_LEN)
#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
#define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-da850evm.lds"
#define CONFIG_SPL_STACK 0x8001ff00
#define CONFIG_SPL_TEXT_BASE 0x80000000
#define CONFIG_SPL_MAX_FOOTPRINT 32768
diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h
index 31364c2..235b746 100644
--- a/include/configs/edminiv2.h
+++ b/include/configs/edminiv2.h
@@ -24,7 +24,6 @@
#define CONFIG_SPL_BSS_MAX_SIZE 0x0001ffff
#define CONFIG_SYS_SPL_MALLOC_START 0x00040000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001ffff
-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/orion5x/u-boot-spl.lds"
#define CONFIG_SYS_UBOOT_BASE 0xfff90000
#define CONFIG_SYS_UBOOT_START 0x00800000
#define CONFIG_SYS_TEXT_BASE 0x00800000
diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h
index 378219d..66fb231 100644
--- a/include/configs/exynos5-common.h
+++ b/include/configs/exynos5-common.h
@@ -49,7 +49,6 @@
#define CONFIG_SUPPORT_EMMC_BOOT
/* specific .lds file */
-#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds"
/* Boot Argument Buffer Size */
/* memtest works on */
diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h
index 9537112..cdb3a37 100644
--- a/include/configs/imx6_spl.h
+++ b/include/configs/imx6_spl.h
@@ -24,7 +24,6 @@
* and some padding thus 'our' max size is really 0x00908000 - 0x00918000
* or 64KB
*/
-#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
#define CONFIG_SPL_TEXT_BASE 0x00908000
#define CONFIG_SPL_MAX_SIZE 0x10000
#define CONFIG_SPL_STACK 0x0091FFB8
diff --git a/include/configs/ipam390.h b/include/configs/ipam390.h
index 7f1f3cc..8e10883 100644
--- a/include/configs/ipam390.h
+++ b/include/configs/ipam390.h
@@ -269,7 +269,6 @@
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
CONFIG_SYS_MALLOC_LEN)
#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
-#define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-ipam390.lds"
#define CONFIG_SPL_STACK 0x8001ff00
#define CONFIG_SPL_TEXT_BASE 0x80000000
#define CONFIG_SPL_MAX_SIZE 0x20000
diff --git a/include/configs/kc1.h b/include/configs/kc1.h
index f040d0b..eb1b63e 100644
--- a/include/configs/kc1.h
+++ b/include/configs/kc1.h
@@ -89,8 +89,6 @@
#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
#define CONFIG_SYS_SPL_MALLOC_SIZE (1024 * 1024)
-#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
-
/*
* Console
*/
diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h
index 1f2eb52..42bd783 100644
--- a/include/configs/ls1021aiot.h
+++ b/include/configs/ls1021aiot.h
@@ -77,7 +77,6 @@
#define CONFIG_SYS_FSL_PBL_RCW \
board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_ENV_SUPPORT
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 251a66e..48e500c 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -52,7 +52,6 @@ unsigned long get_board_ddr_clk(void);
board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
#endif
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
#define CONFIG_SPL_TEXT_BASE 0x10000000
#define CONFIG_SPL_MAX_SIZE 0x1a000
@@ -75,7 +74,6 @@ unsigned long get_board_ddr_clk(void);
#ifdef CONFIG_NAND_BOOT
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
#define CONFIG_SPL_TEXT_BASE 0x10000000
#define CONFIG_SPL_MAX_SIZE 0x1a000
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index b9e5cdb..56d359d 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -96,7 +96,6 @@
board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
#endif
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
#ifdef CONFIG_SECURE_BOOT
/*
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 32f7162..bc40ec0 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -66,7 +66,6 @@
/* SD boot SPL */
#ifdef CONFIG_SD_BOOT
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0x10000000
@@ -98,7 +97,6 @@
#ifdef CONFIG_NAND_BOOT
#define CONFIG_SPL_PBL_PAD
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0x10000000
#define CONFIG_SPL_MAX_SIZE 0x1a000
diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h
index 1b91676..1ad6600 100644
--- a/include/configs/ls1046a_common.h
+++ b/include/configs/ls1046a_common.h
@@ -64,7 +64,6 @@
/* SD boot SPL */
#ifdef CONFIG_SD_BOOT
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
@@ -104,7 +103,6 @@
#ifdef CONFIG_NAND_BOOT
#define CONFIG_SPL_PBL_PAD
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 6ae5586..582bc1a 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -233,7 +233,6 @@ unsigned long long get_qixis_addr(void);
#define CONFIG_SPL_BSS_START_ADDR 0x80100000
#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_MAX_SIZE 0x16000
#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
diff --git a/include/configs/ma5d4evk.h b/include/configs/ma5d4evk.h
index 2744efb..0a115e0 100644
--- a/include/configs/ma5d4evk.h
+++ b/include/configs/ma5d4evk.h
@@ -215,7 +215,6 @@
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000
#define CONFIG_SYS_USE_MMC
-#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
diff --git a/include/configs/mcx.h b/include/configs/mcx.h
index 73fdfbd..3ce8dde 100644
--- a/include/configs/mcx.h
+++ b/include/configs/mcx.h
@@ -288,7 +288,6 @@
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
-#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
index aa007e2..5036b1c 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -258,8 +258,6 @@
#define CONFIG_CMD_SPL
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_LDSCRIPT "arch/microblaze/cpu/u-boot-spl.lds"
-
#ifdef CONFIG_SYS_FLASH_BASE
# define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE
#endif
diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h
index 7ed9012..3fa666a 100644
--- a/include/configs/mx31pdk.h
+++ b/include/configs/mx31pdk.h
@@ -26,7 +26,6 @@
#define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
#define CONFIG_SPL_MAX_SIZE 2048
#define CONFIG_SPL_TEXT_BASE 0x87dc0000
diff --git a/include/configs/mxs.h b/include/configs/mxs.h
index 041dcde..804b9e1 100644
--- a/include/configs/mxs.h
+++ b/include/configs/mxs.h
@@ -46,7 +46,6 @@
/* SPL */
#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs"
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
/* Memory sizes */
#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index 15eb08b..303d119 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -314,7 +314,6 @@
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
#define CONFIG_SPL_OMAP3_ID_NAND
-#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
/*
* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
index 2c17840..694f485 100644
--- a/include/configs/omapl138_lcdk.h
+++ b/include/configs/omapl138_lcdk.h
@@ -313,7 +313,6 @@
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
CONFIG_SYS_MALLOC_LEN)
#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
-#define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-da850evm.lds"
#define CONFIG_SPL_STACK 0x8001ff00
#define CONFIG_SPL_TEXT_BASE 0x80000000
#define CONFIG_SPL_MAX_FOOTPRINT 32768
diff --git a/include/configs/origen.h b/include/configs/origen.h
index c363653..69f6930 100644
--- a/include/configs/origen.h
+++ b/include/configs/origen.h
@@ -95,7 +95,6 @@
#define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
#define CONFIG_ENV_OFFSET (RESERVE_BLOCK_SIZE + BL1_SIZE)
-#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds"
#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024)
#define CONFIG_SYS_INIT_SP_ADDR 0x02040000
diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h
index ce80e7e..585f370 100644
--- a/include/configs/pcm051.h
+++ b/include/configs/pcm051.h
@@ -117,8 +117,6 @@
/* CPU */
-#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
-
#ifdef CONFIG_SPI_BOOT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h
index c77c82a..d305985 100644
--- a/include/configs/pengwyn.h
+++ b/include/configs/pengwyn.h
@@ -199,6 +199,4 @@
/* CPSW support */
-#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
-
#endif /* ! __CONFIG_PENGWYN_H */
diff --git a/include/configs/pepper.h b/include/configs/pepper.h
index ff3cd74..afeb297 100644
--- a/include/configs/pepper.h
+++ b/include/configs/pepper.h
@@ -85,6 +85,5 @@
#define CONFIG_PHY_RESET_DELAY 1000
/* SPL */
-#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
#endif /* __CONFIG_PEPPER_H */
diff --git a/include/configs/picosam9g45.h b/include/configs/picosam9g45.h
index 88f841d..3327515 100644
--- a/include/configs/picosam9g45.h
+++ b/include/configs/picosam9g45.h
@@ -152,7 +152,6 @@
#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000
-#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h
index 678f40d..513adab 100644
--- a/include/configs/rk3368_common.h
+++ b/include/configs/rk3368_common.h
@@ -35,8 +35,6 @@
#define CONFIG_SPL_BSS_START_ADDR 0x400000
#define CONFIG_SPL_BSS_MAX_SIZE 0x20000
-#define CONFIG_TPL_LDSCRIPT \
- "arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds"
#define CONFIG_TPL_TEXT_BASE 0xff8c1000
#define CONFIG_TPL_MAX_SIZE 0x7000
#define CONFIG_TPL_STACK 0xff8cffff
diff --git a/include/configs/sama5d2_xplained.h b/include/configs/sama5d2_xplained.h
index 42fb1e1..b990d40 100644
--- a/include/configs/sama5d2_xplained.h
+++ b/include/configs/sama5d2_xplained.h
@@ -82,7 +82,6 @@
#define CONFIG_SYS_MONITOR_LEN (512 << 10)
#ifdef CONFIG_SYS_USE_MMC
-#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h
index 76533e3..abedddb 100644
--- a/include/configs/sama5d3_xplained.h
+++ b/include/configs/sama5d3_xplained.h
@@ -90,7 +90,6 @@
#define CONFIG_SYS_MONITOR_LEN (512 << 10)
#ifdef CONFIG_SYS_USE_MMC
-#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h
index a5a0f7c..b1e1dd3 100644
--- a/include/configs/sama5d3xek.h
+++ b/include/configs/sama5d3xek.h
@@ -123,7 +123,6 @@
#define CONFIG_SYS_MONITOR_LEN (512 << 10)
#ifdef CONFIG_SYS_USE_MMC
-#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h
index f1cf65f..727988f 100644
--- a/include/configs/sama5d4_xplained.h
+++ b/include/configs/sama5d4_xplained.h
@@ -78,7 +78,6 @@
#define CONFIG_SYS_MONITOR_LEN (512 << 10)
#ifdef CONFIG_SYS_USE_MMC
-#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h
index 09a9757..b1eeb31 100644
--- a/include/configs/sama5d4ek.h
+++ b/include/configs/sama5d4ek.h
@@ -76,7 +76,6 @@
#define CONFIG_SYS_MONITOR_LEN (512 << 10)
#ifdef CONFIG_SYS_USE_MMC
-#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index 22f070d..4247315 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -121,8 +121,6 @@
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
-#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
-
#define CONFIG_SPL_NAND_AM33XX_BCH
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h
index bccb432..ca7408a 100644
--- a/include/configs/smartweb.h
+++ b/include/configs/smartweb.h
@@ -231,7 +231,6 @@
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
CONFIG_SPL_BSS_MAX_SIZE)
#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
-#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14)
#define CONFIG_SYS_USE_NANDFLASH 1
diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h
index 9986a3b..79bd3a2 100644
--- a/include/configs/smdkv310.h
+++ b/include/configs/smdkv310.h
@@ -79,7 +79,6 @@
#define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
#define CONFIG_ENV_OFFSET (RESERVE_BLOCK_SIZE + BL1_SIZE)
-#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds"
#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024)
#define CONFIG_SYS_INIT_SP_ADDR 0x02040000
diff --git a/include/configs/sniper.h b/include/configs/sniper.h
index 669ce85..f5e74c3 100644
--- a/include/configs/sniper.h
+++ b/include/configs/sniper.h
@@ -86,8 +86,6 @@
#define CONFIG_SYS_SPL_MALLOC_SIZE (1024 * 1024)
#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
-#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
-
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index fefd58f..474da22 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -202,10 +202,6 @@
#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
-#ifndef CONFIG_ARM64
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
-#endif
-
#define CONFIG_SPL_PAD_TO 32768 /* decimal for 'dd' */
diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h
index a9991fc..179c63f 100644
--- a/include/configs/tam3517-common.h
+++ b/include/configs/tam3517-common.h
@@ -176,7 +176,6 @@
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
-#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h
index 38f5bd0..efeb2e1 100644
--- a/include/configs/tao3530.h
+++ b/include/configs/tao3530.h
@@ -246,7 +246,6 @@
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_OMAP3_ID_NAND
-#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
/* NAND boot config */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h
index b5f8177..f0866f7 100644
--- a/include/configs/ti814x_evm.h
+++ b/include/configs/ti814x_evm.h
@@ -149,7 +149,6 @@
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
-#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
/*
* 1MB into the SDRAM to allow for SPL's bss@the beginning of SDRAM
diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h
index bba10ec..3da774f 100644
--- a/include/configs/ti816x_evm.h
+++ b/include/configs/ti816x_evm.h
@@ -118,8 +118,6 @@
#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
CONFIG_SPL_TEXT_BASE)
-#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
-
#define CONFIG_SYS_TEXT_BASE 0x80800000
#define CONFIG_DRIVER_TI_EMAC
diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h
index 393d867..938136c 100644
--- a/include/configs/ti_omap3_common.h
+++ b/include/configs/ti_omap3_common.h
@@ -60,7 +60,6 @@
/* SPL */
#define CONFIG_SPL_TEXT_BASE 0x40200800
-#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
(64 << 20))
diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h
index 1a6551e..1d9e59d 100644
--- a/include/configs/ti_omap4_common.h
+++ b/include/configs/ti_omap4_common.h
@@ -139,7 +139,6 @@
* So moving TEXT_BASE down to non-HS limit.
*/
#define CONFIG_SPL_TEXT_BASE 0x40300000
-#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
(128 << 20))
diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h
index 4c3a276..73c1d8f 100644
--- a/include/configs/ti_omap5_common.h
+++ b/include/configs/ti_omap5_common.h
@@ -100,7 +100,6 @@
#define CONFIG_SPL_TEXT_BASE 0x40300000
#endif
-#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
(128 << 20))
diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h
index a0fd583..09a2634 100644
--- a/include/configs/tricorder.h
+++ b/include/configs/tricorder.h
@@ -264,7 +264,6 @@
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
-#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
diff --git a/include/configs/woodburn_sd.h b/include/configs/woodburn_sd.h
index bab7fdf..fb73856 100644
--- a/include/configs/woodburn_sd.h
+++ b/include/configs/woodburn_sd.h
@@ -21,7 +21,6 @@
* SPL
*/
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm1136/u-boot-spl.lds"
#define CONFIG_SPL_TEXT_BASE 0x10002300
#define CONFIG_SPL_MAX_SIZE (64 * 1024) /* 8 KB for stack */
diff --git a/include/configs/x600.h b/include/configs/x600.h
index 0076707..e838456 100644
--- a/include/configs/x600.h
+++ b/include/configs/x600.h
@@ -246,7 +246,6 @@
#define CONFIG_SPL_TEXT_BASE 0xd2800b00
#define CONFIG_SPL_MAX_SIZE (CONFIG_SRAM_SIZE - 0xb00)
#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear"
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds"
#define CONFIG_SPL_FRAMEWORK
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 83a2a02..0c233a9 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -275,8 +275,6 @@
#define CONFIG_CMD_SPL
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-zynq/u-boot-spl.lds"
-
/* MMC support */
#ifdef CONFIG_MMC_SDHCI_ZYNQ
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 60/66] spl: moveconfig: migrate CONFIG_SPL_LDSCRIPT
2017-07-28 19:22 ` [U-Boot] [PATCH v3 60/66] spl: moveconfig: migrate CONFIG_SPL_LDSCRIPT Philipp Tomsich
@ 2017-07-28 19:52 ` Siarhei Siamashka
2017-07-28 20:05 ` Dr. Philipp Tomsich
0 siblings, 1 reply; 95+ messages in thread
From: Siarhei Siamashka @ 2017-07-28 19:52 UTC (permalink / raw)
To: u-boot
On Fri, 28 Jul 2017 21:22:32 +0200
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> wrote:
> With SPL_LDSCRIPT defined via Kconfig, we can run moveconfig... this
> will touch every configuration that uses SPL, even if there was an
> implicit resolution of the SPL_LDSCRIPT: now everything is explicit.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>
> ---
>
> Changes in v3:
> - moveconfig.py CONFIG_SPL_LDSCRIPT
> (Note: I really don't know whether this is what we want, as it's
> making the SPL_LDSCRIPT resolution explicit for every board...
> then again, I understood Tom's comment that moving things into
> Kconfig should be the priority...)
>
> Changes in v2: None
>
> configs/A10-OLinuXino-Lime_defconfig | 1 +
[...]
> include/configs/zynq-common.h | 2 --
> 369 files changed, 313 insertions(+), 106 deletions(-)
>
> diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig
> index 9143022..7d45c1d 100644
> --- a/configs/A10-OLinuXino-Lime_defconfig
> +++ b/configs/A10-OLinuXino-Lime_defconfig
> @@ -11,6 +11,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-olinuxino-lime"
> CONFIG_AHCI=y
> # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
> CONFIG_SPL=y
> +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
Why do we want to clutter board-specific config files with this
information?
If this is migrated to Kconfig, then we probably want to have
reasonable SoC-specific defaults there and leave defconfigs alone.
> CONFIG_SPL_I2C_SUPPORT=y
> # CONFIG_CMD_IMLS is not set
> # CONFIG_CMD_FLASH is not set
--
Best regards,
Siarhei Siamashka
^ permalink raw reply [flat|nested] 95+ messages in thread
* [U-Boot] [PATCH v3 60/66] spl: moveconfig: migrate CONFIG_SPL_LDSCRIPT
2017-07-28 19:52 ` Siarhei Siamashka
@ 2017-07-28 20:05 ` Dr. Philipp Tomsich
2017-07-28 20:20 ` Adam Ford
0 siblings, 1 reply; 95+ messages in thread
From: Dr. Philipp Tomsich @ 2017-07-28 20:05 UTC (permalink / raw)
To: u-boot
> On 28 Jul 2017, at 21:52, Siarhei Siamashka <siarhei.siamashka@gmail.com> wrote:
>
> On Fri, 28 Jul 2017 21:22:32 +0200
> Philipp Tomsich <philipp.tomsich@theobroma-systems.com> wrote:
>
>> With SPL_LDSCRIPT defined via Kconfig, we can run moveconfig... this
>> will touch every configuration that uses SPL, even if there was an
>> implicit resolution of the SPL_LDSCRIPT: now everything is explicit.
>>
>> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>>
>> ---
>>
>> Changes in v3:
>> - moveconfig.py CONFIG_SPL_LDSCRIPT
>> (Note: I really don't know whether this is what we want, as it's
>> making the SPL_LDSCRIPT resolution explicit for every board...
>> then again, I understood Tom's comment that moving things into
>> Kconfig should be the priority...)
>>
>> Changes in v2: None
>>
>> configs/A10-OLinuXino-Lime_defconfig | 1 +
>
> [...]
>
>> include/configs/zynq-common.h | 2 --
>> 369 files changed, 313 insertions(+), 106 deletions(-)
>>
>> diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig
>> index 9143022..7d45c1d 100644
>> --- a/configs/A10-OLinuXino-Lime_defconfig
>> +++ b/configs/A10-OLinuXino-Lime_defconfig
>> @@ -11,6 +11,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-olinuxino-lime"
>> CONFIG_AHCI=y
>> # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
>> CONFIG_SPL=y
>> +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
>
> Why do we want to clutter board-specific config files with this
> information?
I do agree that this is not the preferable way of doing things and
that this should be propagated back up through Kconfig. One
possibility might be to add ‘default “…” if “…”’ entries either to
the central Kconfig for SPL or to have these in the various
machine-subdirectories.
Let’s see if some consensus emerges from this...
My plan was to skip this specific patch on the merge (which is the
reason I kept the moveconfig-run as a separate commit), but keep
it here as a point-of-reference.
> If this is migrated to Kconfig, then we probably want to have
> reasonable SoC-specific defaults there and leave defconfigs alone.
>
>> CONFIG_SPL_I2C_SUPPORT=y
>> # CONFIG_CMD_IMLS is not set
>> # CONFIG_CMD_FLASH is not set
>
>
> --
> Best regards,
> Siarhei Siamashka
^ permalink raw reply [flat|nested] 95+ messages in thread
* [U-Boot] [PATCH v3 60/66] spl: moveconfig: migrate CONFIG_SPL_LDSCRIPT
2017-07-28 20:05 ` Dr. Philipp Tomsich
@ 2017-07-28 20:20 ` Adam Ford
0 siblings, 0 replies; 95+ messages in thread
From: Adam Ford @ 2017-07-28 20:20 UTC (permalink / raw)
To: u-boot
On Fri, Jul 28, 2017 at 3:05 PM, Dr. Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
>
>> On 28 Jul 2017, at 21:52, Siarhei Siamashka <siarhei.siamashka@gmail.com> wrote:
>>
>> On Fri, 28 Jul 2017 21:22:32 +0200
>> Philipp Tomsich <philipp.tomsich@theobroma-systems.com> wrote:
>>
>>> With SPL_LDSCRIPT defined via Kconfig, we can run moveconfig... this
>>> will touch every configuration that uses SPL, even if there was an
>>> implicit resolution of the SPL_LDSCRIPT: now everything is explicit.
>>>
>>> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>>>
>>> ---
>>>
>>> Changes in v3:
>>> - moveconfig.py CONFIG_SPL_LDSCRIPT
>>> (Note: I really don't know whether this is what we want, as it's
>>> making the SPL_LDSCRIPT resolution explicit for every board...
>>> then again, I understood Tom's comment that moving things into
>>> Kconfig should be the priority...)
>>>
>>> Changes in v2: None
>>>
>>> configs/A10-OLinuXino-Lime_defconfig | 1 +
>>
>> [...]
>>
>>> include/configs/zynq-common.h | 2 --
>>> 369 files changed, 313 insertions(+), 106 deletions(-)
>>>
>>> diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig
>>> index 9143022..7d45c1d 100644
>>> --- a/configs/A10-OLinuXino-Lime_defconfig
>>> +++ b/configs/A10-OLinuXino-Lime_defconfig
>>> @@ -11,6 +11,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-olinuxino-lime"
>>> CONFIG_AHCI=y
>>> # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
>>> CONFIG_SPL=y
>>> +CONFIG_SPL_LDSCRIPT="arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
>>
>> Why do we want to clutter board-specific config files with this
>> information?
>
> I do agree that this is not the preferable way of doing things and
> that this should be propagated back up through Kconfig. One
> possibility might be to add ‘default “…” if “…”’ entries either to
> the central Kconfig for SPL or to have these in the various
> machine-subdirectories.
>
> Let’s see if some consensus emerges from this...
>
My vote would be to have the Target selection or Platform selection
imply the respective linker script, so you can keep any exceptions in
the defconfig files, but the majority of them not get overly
cluttered.
adam
> My plan was to skip this specific patch on the merge (which is the
> reason I kept the moveconfig-run as a separate commit), but keep
> it here as a point-of-reference.
>
>> If this is migrated to Kconfig, then we probably want to have
>> reasonable SoC-specific defaults there and leave defconfigs alone.
>>
>>> CONFIG_SPL_I2C_SUPPORT=y
>>> # CONFIG_CMD_IMLS is not set
>>> # CONFIG_CMD_FLASH is not set
>>
>>
>> --
>> Best regards,
>> Siarhei Siamashka
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot
^ permalink raw reply [flat|nested] 95+ messages in thread
* [U-Boot] [PATCH v3 61/66] spl: support TPL_STACK, TPL_MAX_SIZE and TPL_TEXT_BASE via Kconfig
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (59 preceding siblings ...)
2017-07-28 19:22 ` [U-Boot] [PATCH v3 60/66] spl: moveconfig: migrate CONFIG_SPL_LDSCRIPT Philipp Tomsich
@ 2017-07-28 19:22 ` Philipp Tomsich
2017-08-01 9:49 ` Simon Glass
2017-07-28 19:22 ` [U-Boot] [PATCH v3 62/66] armv8: TPL_STACK will always be defined, so test CONFIG_TPL_NEEDS_SEPARATE_STACK Philipp Tomsich
` (4 subsequent siblings)
65 siblings, 1 reply; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:22 UTC (permalink / raw)
To: u-boot
Let's clean up behind ourselves and move the (newly defined)
TPL_STACK, TPL_MAX_SIZE and TPL_TEXT_BASE into Kconfig. Given that
0x0 might be considered to be valid values for TPL_TEXT_BASE and
TPL_STACK, we need to introduce helper config options
("TPL_NEEDS_SEPARATE_...") to indicate that these symbols are used
(and not inherited from their SPL variants) for any given
target-platform.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---
Changes in v3:
- moves TPL_STACK, TPL_MAX_SIZE and TPL_TEXT_BASE to Kconfig
Changes in v2: None
common/spl/Kconfig | 39 +++++++++++++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index b01d4f1..08013b7 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -725,6 +725,45 @@ config TPL_LDSCRIPT
U-Boot stage. Set this to the path of the linker-script to
be used for TPL.
+ May be left empty to trigger the Makefile infrastructure to
+ fall back to the linker-script used for the SPL stage.
+
+config TPL_NEEDS_SEPARATE_TEXT_BASE
+ bool "TPL needs a separate text-base"
+ default n
+ depends on TPL
+ help
+ Enable, if the TPL stage should not inherit its text-base
+ from the SPL stage. When enabled, a base address for the
+ .text sections of the TPL stage has to be set below.
+
+config TPL_NEEDS_SEPARATE_STACK
+ bool "TPL needs a separate initial stack-pointer"
+ default n
+ depends on TPL
+ help
+ Enable, if the TPL stage should not inherit its initial
+ stack-pointer from the settings for the SPL stage.
+
+config TPL_TEXT_BASE
+ hex "Base address for the .text section of the TPL stage"
+ depends on TPL_NEEDS_SEPARATE_TEXT_BASE
+ help
+ The base address for the .text section of the TPL stage.
+
+config TPL_MAX_SIZE
+ int "Maximum size (in bytes) for the TPL stage"
+ depends on TPL
+ help
+ The maximum size (in bytes) of the TPL stage.
+
+config TPL_STACK
+ hex "Address of the initial stack-pointer for the TPL stage"
+ depends on TPL_NEEDS_SEPARATE_STACK
+ help
+ The address of the initial stack-pointer for the TPL stage.
+ Usually this will be the (aligned) top-of-stack.
+
config TPL_BOOTROM_SUPPORT
bool "Support returning to the BOOTROM (from TPL)"
help
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 61/66] spl: support TPL_STACK, TPL_MAX_SIZE and TPL_TEXT_BASE via Kconfig
2017-07-28 19:22 ` [U-Boot] [PATCH v3 61/66] spl: support TPL_STACK, TPL_MAX_SIZE and TPL_TEXT_BASE via Kconfig Philipp Tomsich
@ 2017-08-01 9:49 ` Simon Glass
0 siblings, 0 replies; 95+ messages in thread
From: Simon Glass @ 2017-08-01 9:49 UTC (permalink / raw)
To: u-boot
On 28 July 2017 at 13:22, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> Let's clean up behind ourselves and move the (newly defined)
> TPL_STACK, TPL_MAX_SIZE and TPL_TEXT_BASE into Kconfig. Given that
> 0x0 might be considered to be valid values for TPL_TEXT_BASE and
> TPL_STACK, we need to introduce helper config options
> ("TPL_NEEDS_SEPARATE_...") to indicate that these symbols are used
> (and not inherited from their SPL variants) for any given
> target-platform.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>
> ---
>
> Changes in v3:
> - moves TPL_STACK, TPL_MAX_SIZE and TPL_TEXT_BASE to Kconfig
>
> Changes in v2: None
>
> common/spl/Kconfig | 39 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 39 insertions(+)
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 95+ messages in thread
* [U-Boot] [PATCH v3 62/66] armv8: TPL_STACK will always be defined, so test CONFIG_TPL_NEEDS_SEPARATE_STACK
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (60 preceding siblings ...)
2017-07-28 19:22 ` [U-Boot] [PATCH v3 61/66] spl: support TPL_STACK, TPL_MAX_SIZE and TPL_TEXT_BASE via Kconfig Philipp Tomsich
@ 2017-07-28 19:22 ` Philipp Tomsich
2017-08-01 9:49 ` Simon Glass
2017-07-28 19:22 ` [U-Boot] [PATCH v3 63/66] rockchip: rk3368: mark TPL as not inheriting its stack, text-base and size from SPL Philipp Tomsich
` (3 subsequent siblings)
65 siblings, 1 reply; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:22 UTC (permalink / raw)
To: u-boot
Now that TPL_STACK has been moved off the whitelist (ok, I'm lying:
the 'moving off the whitelist' part comes in once moveconfig
runs... which will be a few commits down the line) and added to
Kconfig, we need to test CONFIG_TPL_NEEDS_SEPARATE_STACK to see
whether the value from TPL_STACK should be used or whether we try to
inherit whatever SPL uses.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---
Changes in v3:
- changes the test to CONFIG_TPL_NEEDS_SEPARATE_STACK, as TPL_STACK
will be a hex-value now (and this always be defined)
Changes in v2: None
arch/arm/lib/crt0_64.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S
index 177b5bf..62fad45 100644
--- a/arch/arm/lib/crt0_64.S
+++ b/arch/arm/lib/crt0_64.S
@@ -69,7 +69,7 @@ ENTRY(_main)
/*
* Set up initial C runtime environment and call board_init_f(0).
*/
-#if defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_STACK)
+#if defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_NEEDS_SEPARATE_STACK)
ldr x0, =(CONFIG_TPL_STACK)
#elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
ldr x0, =(CONFIG_SPL_STACK)
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 62/66] armv8: TPL_STACK will always be defined, so test CONFIG_TPL_NEEDS_SEPARATE_STACK
2017-07-28 19:22 ` [U-Boot] [PATCH v3 62/66] armv8: TPL_STACK will always be defined, so test CONFIG_TPL_NEEDS_SEPARATE_STACK Philipp Tomsich
@ 2017-08-01 9:49 ` Simon Glass
0 siblings, 0 replies; 95+ messages in thread
From: Simon Glass @ 2017-08-01 9:49 UTC (permalink / raw)
To: u-boot
On 28 July 2017 at 13:22, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> Now that TPL_STACK has been moved off the whitelist (ok, I'm lying:
> the 'moving off the whitelist' part comes in once moveconfig
> runs... which will be a few commits down the line) and added to
> Kconfig, we need to test CONFIG_TPL_NEEDS_SEPARATE_STACK to see
> whether the value from TPL_STACK should be used or whether we try to
> inherit whatever SPL uses.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>
> ---
>
> Changes in v3:
> - changes the test to CONFIG_TPL_NEEDS_SEPARATE_STACK, as TPL_STACK
> will be a hex-value now (and this always be defined)
>
> Changes in v2: None
>
> arch/arm/lib/crt0_64.S | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 95+ messages in thread
* [U-Boot] [PATCH v3 63/66] rockchip: rk3368: mark TPL as not inheriting its stack, text-base and size from SPL
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (61 preceding siblings ...)
2017-07-28 19:22 ` [U-Boot] [PATCH v3 62/66] armv8: TPL_STACK will always be defined, so test CONFIG_TPL_NEEDS_SEPARATE_STACK Philipp Tomsich
@ 2017-07-28 19:22 ` Philipp Tomsich
2017-08-01 9:49 ` Simon Glass
2017-07-28 19:22 ` [U-Boot] [PATCH v3 64/66] moveconfig: migrate TPL_STACK, TPL_TEXT_BASE and TPL_MAX_SIZE Philipp Tomsich
` (2 subsequent siblings)
65 siblings, 1 reply; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:22 UTC (permalink / raw)
To: u-boot
The RK3368 needs to have a different base-address and stack-pointer
for its TPL stage. Now that we want to do this via Kconfig, we need
to tick the appropriate 'TPL_NEEDS_...' boxes.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---
Changes in v3:
- changes Kconfig, so RK3368 will notify the SPL configuration of
its need to have the TPL text-base, stack-pointer and max-size
configured
Changes in v2: None
arch/arm/mach-rockchip/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 8406e33..9422cf2 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -69,6 +69,8 @@ config ROCKCHIP_RK3368
select ARM64
select SUPPORT_SPL
select SUPPORT_TPL
+ select TPL_NEEDS_SEPARATE_TEXT_BASE
+ select TPL_NEEDS_SEPARATE_STACK
select SPL_SEPARATE_BSS
select SPL_SERIAL_SUPPORT
select TPL_SERIAL_SUPPORT
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 63/66] rockchip: rk3368: mark TPL as not inheriting its stack, text-base and size from SPL
2017-07-28 19:22 ` [U-Boot] [PATCH v3 63/66] rockchip: rk3368: mark TPL as not inheriting its stack, text-base and size from SPL Philipp Tomsich
@ 2017-08-01 9:49 ` Simon Glass
0 siblings, 0 replies; 95+ messages in thread
From: Simon Glass @ 2017-08-01 9:49 UTC (permalink / raw)
To: u-boot
On 28 July 2017 at 13:22, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> The RK3368 needs to have a different base-address and stack-pointer
> for its TPL stage. Now that we want to do this via Kconfig, we need
> to tick the appropriate 'TPL_NEEDS_...' boxes.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>
> ---
>
> Changes in v3:
> - changes Kconfig, so RK3368 will notify the SPL configuration of
> its need to have the TPL text-base, stack-pointer and max-size
> configured
>
> Changes in v2: None
>
> arch/arm/mach-rockchip/Kconfig | 2 ++
> 1 file changed, 2 insertions(+)
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 95+ messages in thread
* [U-Boot] [PATCH v3 64/66] moveconfig: migrate TPL_STACK, TPL_TEXT_BASE and TPL_MAX_SIZE
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (62 preceding siblings ...)
2017-07-28 19:22 ` [U-Boot] [PATCH v3 63/66] rockchip: rk3368: mark TPL as not inheriting its stack, text-base and size from SPL Philipp Tomsich
@ 2017-07-28 19:22 ` Philipp Tomsich
2017-08-01 9:48 ` Simon Glass
2017-07-28 19:22 ` [U-Boot] [PATCH v3 65/66] rockchip: board: puma-rk3399: fix warnings in puma_rk3399/fit_spl_atf.its Philipp Tomsich
2017-07-28 19:22 ` [U-Boot] [PATCH v3 66/66] rockchip: board: puma_rk3399: rename ATF firmware Philipp Tomsich
65 siblings, 1 reply; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:22 UTC (permalink / raw)
To: u-boot
We can finally drop TPL_STACK, TPL_TEXT_BASE and TPL_MAX_SIZE off the
whitelist (this time it's really happening!) and migrate the setting
(only used on the RK3368-uQ7 so far) into defconfig.
One major caveat: other RK3368 boards that move to use SPL/TPL
will also need to set these values in their defconfig.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---
Changes in v3:
- runs moveconfig.py TPL_STACK TPL_TEXT_BASE TPL_MAX_SIZE
Changes in v2: None
configs/lion-rk3368_defconfig | 3 +++
include/configs/rk3368_common.h | 4 ----
scripts/config_whitelist.txt | 3 ---
3 files changed, 3 insertions(+), 7 deletions(-)
diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig
index 701a78f..cee79c1 100644
--- a/configs/lion-rk3368_defconfig
+++ b/configs/lion-rk3368_defconfig
@@ -33,6 +33,9 @@ CONFIG_SPL_ATF_SUPPORT=y
CONFIG_SPL_ATF_TEXT_BASE=0x10000
CONFIG_TPL=y
CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds"
+CONFIG_TPL_TEXT_BASE=0xff8c1000
+CONFIG_TPL_MAX_SIZE=28672
+CONFIG_TPL_STACK=0xff8cffff
CONFIG_TPL_BOOTROM_SUPPORT=y
CONFIG_TPL_DRIVERS_MISC_SUPPORT=y
CONFIG_FASTBOOT=y
diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h
index 513adab..a89c69a 100644
--- a/include/configs/rk3368_common.h
+++ b/include/configs/rk3368_common.h
@@ -35,10 +35,6 @@
#define CONFIG_SPL_BSS_START_ADDR 0x400000
#define CONFIG_SPL_BSS_MAX_SIZE 0x20000
-#define CONFIG_TPL_TEXT_BASE 0xff8c1000
-#define CONFIG_TPL_MAX_SIZE 0x7000
-#define CONFIG_TPL_STACK 0xff8cffff
-
#define CONFIG_BOUNCE_BUFFER
#ifndef CONFIG_SPL_BUILD
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 0e09a52..167ea55 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -4980,10 +4980,7 @@ CONFIG_TI_KEYSTONE_SERDES
CONFIG_TI_KSNAV
CONFIG_TI_SPI_MMAP
CONFIG_TMU_TIMER
-CONFIG_TPL_MAX_SIZE
CONFIG_TPL_PAD_TO
-CONFIG_TPL_STACK
-CONFIG_TPL_TEXT_BASE
CONFIG_TPM_TIS_BASE_ADDRESS
CONFIG_TPS6586X_POWER
CONFIG_TQM834X
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 64/66] moveconfig: migrate TPL_STACK, TPL_TEXT_BASE and TPL_MAX_SIZE
2017-07-28 19:22 ` [U-Boot] [PATCH v3 64/66] moveconfig: migrate TPL_STACK, TPL_TEXT_BASE and TPL_MAX_SIZE Philipp Tomsich
@ 2017-08-01 9:48 ` Simon Glass
0 siblings, 0 replies; 95+ messages in thread
From: Simon Glass @ 2017-08-01 9:48 UTC (permalink / raw)
To: u-boot
On 28 July 2017 at 13:22, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> We can finally drop TPL_STACK, TPL_TEXT_BASE and TPL_MAX_SIZE off the
> whitelist (this time it's really happening!) and migrate the setting
> (only used on the RK3368-uQ7 so far) into defconfig.
>
> One major caveat: other RK3368 boards that move to use SPL/TPL
> will also need to set these values in their defconfig.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>
> ---
>
> Changes in v3:
> - runs moveconfig.py TPL_STACK TPL_TEXT_BASE TPL_MAX_SIZE
>
> Changes in v2: None
>
> configs/lion-rk3368_defconfig | 3 +++
> include/configs/rk3368_common.h | 4 ----
> scripts/config_whitelist.txt | 3 ---
> 3 files changed, 3 insertions(+), 7 deletions(-)
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 95+ messages in thread
* [U-Boot] [PATCH v3 65/66] rockchip: board: puma-rk3399: fix warnings in puma_rk3399/fit_spl_atf.its
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (63 preceding siblings ...)
2017-07-28 19:22 ` [U-Boot] [PATCH v3 64/66] moveconfig: migrate TPL_STACK, TPL_TEXT_BASE and TPL_MAX_SIZE Philipp Tomsich
@ 2017-07-28 19:22 ` Philipp Tomsich
2017-08-02 3:10 ` Kever Yang
2017-07-28 19:22 ` [U-Boot] [PATCH v3 66/66] rockchip: board: puma_rk3399: rename ATF firmware Philipp Tomsich
65 siblings, 1 reply; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:22 UTC (permalink / raw)
To: u-boot
The ITS file generated warnings due to @<num> designations in the naming
which cause DTC to complain as follows:
Warning (unit_address_vs_reg): Node /images/uboot at 1 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /images/atf at 1 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /images/pmu at 1 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /images/fdt at 1 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /configurations/conf at 1 has a unit name, but no reg property
This removes the @<num> part from the names, as we only have a single
image for each payload aspect (and only a single configuration) anyway.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
Changes in v3: None
Changes in v2: None
board/theobroma-systems/puma_rk3399/fit_spl_atf.its | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/board/theobroma-systems/puma_rk3399/fit_spl_atf.its b/board/theobroma-systems/puma_rk3399/fit_spl_atf.its
index f93c251..0519fad 100644
--- a/board/theobroma-systems/puma_rk3399/fit_spl_atf.its
+++ b/board/theobroma-systems/puma_rk3399/fit_spl_atf.its
@@ -13,7 +13,7 @@
#address-cells = <1>;
images {
- uboot at 1 {
+ uboot {
description = "U-Boot (64-bit)";
data = /incbin/("../../../u-boot-nodtb.bin");
type = "standalone";
@@ -21,7 +21,7 @@
compression = "none";
load = <0x00200000>;
};
- atf at 1 {
+ atf {
description = "ARM Trusted Firmware";
data = /incbin/("../../../bl31.bin");
type = "firmware";
@@ -30,14 +30,14 @@
load = <0x00001000>;
entry = <0x00001000>;
};
- pmu at 1 {
+ pmu {
description = "Cortex-M0 firmware";
data = /incbin/("../../../rk3399m0.bin");
type = "pmu-firmware";
compression = "none";
load = <0xff8c0000>;
};
- fdt at 1 {
+ fdt {
description = "RK3399-Q7 (Puma) flat device-tree";
data = /incbin/("../../../u-boot.dtb");
type = "flat_dt";
@@ -46,12 +46,12 @@
};
configurations {
- default = "conf at 1";
- conf at 1 {
+ default = "conf";
+ conf {
description = "Theobroma Systems RK3399-Q7 (Puma) SoM";
- firmware = "uboot at 1";
- loadables = "atf at 1";
- fdt = "fdt at 1";
+ firmware = "uboot";
+ loadables = "atf";
+ fdt = "fdt";
};
};
};
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 65/66] rockchip: board: puma-rk3399: fix warnings in puma_rk3399/fit_spl_atf.its
2017-07-28 19:22 ` [U-Boot] [PATCH v3 65/66] rockchip: board: puma-rk3399: fix warnings in puma_rk3399/fit_spl_atf.its Philipp Tomsich
@ 2017-08-02 3:10 ` Kever Yang
2017-08-02 9:09 ` Dr. Philipp Tomsich
0 siblings, 1 reply; 95+ messages in thread
From: Kever Yang @ 2017-08-02 3:10 UTC (permalink / raw)
To: u-boot
Hi Philipp,
rk3399 atf has 3 parts, sram.data, sram.text, pmu_fw for m0, and
now the ATF project output
with all 3 section in one bl31.elf, I use to abstract them into 3
separate bin file and package them
with fit.
Could you share some more detail about how you use the ATF in
puma-rk3399? You only have
two section in its description. How many steps do you need for rk3399 to
get uboot, atf and the image
can be flash to eMMC?
Thanks,
- Kever
On 07/29/2017 03:22 AM, Philipp Tomsich wrote:
> The ITS file generated warnings due to @<num> designations in the naming
> which cause DTC to complain as follows:
> Warning (unit_address_vs_reg): Node /images/uboot at 1 has a unit name, but no reg property
> Warning (unit_address_vs_reg): Node /images/atf at 1 has a unit name, but no reg property
> Warning (unit_address_vs_reg): Node /images/pmu at 1 has a unit name, but no reg property
> Warning (unit_address_vs_reg): Node /images/fdt at 1 has a unit name, but no reg property
> Warning (unit_address_vs_reg): Node /configurations/conf at 1 has a unit name, but no reg property
>
> This removes the @<num> part from the names, as we only have a single
> image for each payload aspect (and only a single configuration) anyway.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
> board/theobroma-systems/puma_rk3399/fit_spl_atf.its | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/board/theobroma-systems/puma_rk3399/fit_spl_atf.its b/board/theobroma-systems/puma_rk3399/fit_spl_atf.its
> index f93c251..0519fad 100644
> --- a/board/theobroma-systems/puma_rk3399/fit_spl_atf.its
> +++ b/board/theobroma-systems/puma_rk3399/fit_spl_atf.its
> @@ -13,7 +13,7 @@
> #address-cells = <1>;
>
> images {
> - uboot at 1 {
> + uboot {
> description = "U-Boot (64-bit)";
> data = /incbin/("../../../u-boot-nodtb.bin");
> type = "standalone";
> @@ -21,7 +21,7 @@
> compression = "none";
> load = <0x00200000>;
> };
> - atf at 1 {
> + atf {
> description = "ARM Trusted Firmware";
> data = /incbin/("../../../bl31.bin");
> type = "firmware";
> @@ -30,14 +30,14 @@
> load = <0x00001000>;
> entry = <0x00001000>;
> };
> - pmu at 1 {
> + pmu {
> description = "Cortex-M0 firmware";
> data = /incbin/("../../../rk3399m0.bin");
> type = "pmu-firmware";
> compression = "none";
> load = <0xff8c0000>;
> };
> - fdt at 1 {
> + fdt {
> description = "RK3399-Q7 (Puma) flat device-tree";
> data = /incbin/("../../../u-boot.dtb");
> type = "flat_dt";
> @@ -46,12 +46,12 @@
> };
>
> configurations {
> - default = "conf at 1";
> - conf at 1 {
> + default = "conf";
> + conf {
> description = "Theobroma Systems RK3399-Q7 (Puma) SoM";
> - firmware = "uboot at 1";
> - loadables = "atf at 1";
> - fdt = "fdt at 1";
> + firmware = "uboot";
> + loadables = "atf";
> + fdt = "fdt";
> };
> };
> };
^ permalink raw reply [flat|nested] 95+ messages in thread* [U-Boot] [PATCH v3 65/66] rockchip: board: puma-rk3399: fix warnings in puma_rk3399/fit_spl_atf.its
2017-08-02 3:10 ` Kever Yang
@ 2017-08-02 9:09 ` Dr. Philipp Tomsich
0 siblings, 0 replies; 95+ messages in thread
From: Dr. Philipp Tomsich @ 2017-08-02 9:09 UTC (permalink / raw)
To: u-boot
Kever,
We use a fork of the ATF repository and have the M3 firmware completely factored out and have changed parts of the SRAM setup.
In other words: there will be two separate .bin files created that need to be loaded to two separate locations.
Please refer to our board’s README for the steps to get it set up and booted.
Note that there will be a structural update to our ATF in the next couple of weeks that is expected to change things around quite a bit.
Regards,
Philipp.
> On 02 Aug 2017, at 05:10, Kever Yang <kever.yang@rock-chips.com> wrote:
>
> Hi Philipp,
>
> rk3399 atf has 3 parts, sram.data, sram.text, pmu_fw for m0, and now the ATF project output
>
> with all 3 section in one bl31.elf, I use to abstract them into 3 separate bin file and package them
>
> with fit.
>
> Could you share some more detail about how you use the ATF in puma-rk3399? You only have
>
> two section in its description. How many steps do you need for rk3399 to get uboot, atf and the image
>
> can be flash to eMMC?
>
> Thanks,
> - Kever
> On 07/29/2017 03:22 AM, Philipp Tomsich wrote:
>> The ITS file generated warnings due to @<num> designations in the naming
>> which cause DTC to complain as follows:
>> Warning (unit_address_vs_reg): Node /images/uboot at 1 has a unit name, but no reg property
>> Warning (unit_address_vs_reg): Node /images/atf at 1 has a unit name, but no reg property
>> Warning (unit_address_vs_reg): Node /images/pmu at 1 has a unit name, but no reg property
>> Warning (unit_address_vs_reg): Node /images/fdt at 1 has a unit name, but no reg property
>> Warning (unit_address_vs_reg): Node /configurations/conf at 1 has a unit name, but no reg property
>>
>> This removes the @<num> part from the names, as we only have a single
>> image for each payload aspect (and only a single configuration) anyway.
>>
>> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>>
>> Reviewed-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> Changes in v3: None
>> Changes in v2: None
>>
>> board/theobroma-systems/puma_rk3399/fit_spl_atf.its | 18 +++++++++---------
>> 1 file changed, 9 insertions(+), 9 deletions(-)
>>
>> diff --git a/board/theobroma-systems/puma_rk3399/fit_spl_atf.its b/board/theobroma-systems/puma_rk3399/fit_spl_atf.its
>> index f93c251..0519fad 100644
>> --- a/board/theobroma-systems/puma_rk3399/fit_spl_atf.its
>> +++ b/board/theobroma-systems/puma_rk3399/fit_spl_atf.its
>> @@ -13,7 +13,7 @@
>> #address-cells = <1>;
>> images {
>> - uboot at 1 {
>> + uboot {
>> description = "U-Boot (64-bit)";
>> data = /incbin/("../../../u-boot-nodtb.bin");
>> type = "standalone";
>> @@ -21,7 +21,7 @@
>> compression = "none";
>> load = <0x00200000>;
>> };
>> - atf at 1 {
>> + atf {
>> description = "ARM Trusted Firmware";
>> data = /incbin/("../../../bl31.bin");
>> type = "firmware";
>> @@ -30,14 +30,14 @@
>> load = <0x00001000>;
>> entry = <0x00001000>;
>> };
>> - pmu at 1 {
>> + pmu {
>> description = "Cortex-M0 firmware";
>> data = /incbin/("../../../rk3399m0.bin");
>> type = "pmu-firmware";
>> compression = "none";
>> load = <0xff8c0000>;
>> };
>> - fdt at 1 {
>> + fdt {
>> description = "RK3399-Q7 (Puma) flat device-tree";
>> data = /incbin/("../../../u-boot.dtb");
>> type = "flat_dt";
>> @@ -46,12 +46,12 @@
>> };
>> configurations {
>> - default = "conf at 1";
>> - conf at 1 {
>> + default = "conf";
>> + conf {
>> description = "Theobroma Systems RK3399-Q7 (Puma) SoM";
>> - firmware = "uboot at 1";
>> - loadables = "atf at 1";
>> - fdt = "fdt at 1";
>> + firmware = "uboot";
>> + loadables = "atf";
>> + fdt = "fdt";
>> };
>> };
>> };
>
>
^ permalink raw reply [flat|nested] 95+ messages in thread
* [U-Boot] [PATCH v3 66/66] rockchip: board: puma_rk3399: rename ATF firmware
2017-07-28 19:21 [U-Boot] [PATCH v3 00/66] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7 Philipp Tomsich
` (64 preceding siblings ...)
2017-07-28 19:22 ` [U-Boot] [PATCH v3 65/66] rockchip: board: puma-rk3399: fix warnings in puma_rk3399/fit_spl_atf.its Philipp Tomsich
@ 2017-07-28 19:22 ` Philipp Tomsich
65 siblings, 0 replies; 95+ messages in thread
From: Philipp Tomsich @ 2017-07-28 19:22 UTC (permalink / raw)
To: u-boot
From: Klaus Goger <klaus.goger@theobroma-systems.com>
prefix the bl31 firmware needed to build uboot.itb so it can coexist in
the build area with ATFs from other boards (i.e. lion_rk3368)
Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---
Changes in v3: None
Changes in v2: None
board/theobroma-systems/puma_rk3399/README | 2 +-
board/theobroma-systems/puma_rk3399/fit_spl_atf.its | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/theobroma-systems/puma_rk3399/README b/board/theobroma-systems/puma_rk3399/README
index 250e345..214281a 100644
--- a/board/theobroma-systems/puma_rk3399/README
+++ b/board/theobroma-systems/puma_rk3399/README
@@ -37,7 +37,7 @@ Compile the ATF
> cd arm-trusted-firmware
> make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl31
- > cp build/rk3399/release/bl31.bin ../u-boot
+ > cp build/rk3399/release/bl31.bin ../u-boot/bl31-rk3399.bin
Compile the M0 firmware
=======================
diff --git a/board/theobroma-systems/puma_rk3399/fit_spl_atf.its b/board/theobroma-systems/puma_rk3399/fit_spl_atf.its
index 0519fad..520f846 100644
--- a/board/theobroma-systems/puma_rk3399/fit_spl_atf.its
+++ b/board/theobroma-systems/puma_rk3399/fit_spl_atf.its
@@ -23,7 +23,7 @@
};
atf {
description = "ARM Trusted Firmware";
- data = /incbin/("../../../bl31.bin");
+ data = /incbin/("../../../bl31-rk3399.bin");
type = "firmware";
arch = "arm64";
compression = "none";
--
2.1.4
^ permalink raw reply related [flat|nested] 95+ messages in thread