[U-Boot] [PATCH v3 51/66] rockchip: rk3368: dts: add DMC node in rk3368.dtsi

Philipp Tomsich
2017-07-28T19:22:23Z

For full SPL support, including DRAM initialisation, we need a few
nodes from the DTS: this commit adds the DMC (DRAM controller) node,
the service_msch (memory scheduler) node and marks GRF, PMUGRF and CRU
as 'u-boot,dm-pre-reloc'. In addition to this, we also include the
dt-binding for the DMC to allow DTS files including this DTSI to refer
to the symbolic constants for the DDR3 bin and for the
memory-schedule.

Note that the DMC contains both the memory regions for the
(Designware) protocol controller as well as the DDR PHY.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

---

Changes in v3: None
Changes in v2:
- removes a 'u-boot,dm-pre-reloc' from dmc-node in rk3368.dtsi

arch/arm/dts/rk3368.dtsi | 25 +++++++++++++++++++------
1 file changed, 19 insertions(+), 6 deletions(-)

diff --git a/arch/arm/dts/rk3368.dtsi b/arch/arm/dts/rk3368.dtsi
index 59c20da..0dad34d 100644
--- a/arch/arm/dts/rk3368.dtsi
+++ b/arch/arm/dts/rk3368.dtsi
@@ -46,6 +46,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/memory/rk3368-dmc.h>

/ {
compatible = "rockchip,rk3368";
@@ -227,6 +228,22 @@
#clock-cells = <0>;
};

+ dmc: dmc at ff610000 {
+ compatible = "rockchip,rk3368-dmc", "syscon";
+ rockchip,cru = <&cru>;
+ rockchip,grf = <&grf>;
+ rockchip,msch = <&service_msch>;
+ reg = <0 0xff610000 0 0x400
+ 0 0xff620000 0 0x400>;
+ };
+
+ service_msch: syscon at ffac0000 {
+ u-boot,dm-pre-reloc;
+ compatible = "rockchip,rk3368-msch", "syscon";
+ reg = <0x0 0xffac0000 0x0 0x2000>;
+ status = "okay";
+ };
+
sdmmc: dwmmc at ff0c0000 {
compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff0c0000 0x0 0x4000>;
@@ -546,12 +563,6 @@
status = "disabled";
};

- dmc: dmc at ff610000 {
- u-boot,dm-pre-reloc;
- compatible = "rockchip,rk3368-dmc", "syscon";
- reg = <0x0 0xff610000 0x0 0x1000>;
- };
-
i2c0: i2c at ff650000 {
compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
reg = <0x0 0xff650000 0x0 0x1000>;
@@ -658,6 +669,7 @@
};

cru: clock-controller at ff760000 {
+ u-boot,dm-pre-reloc;
compatible = "rockchip,rk3368-cru";
reg = <0x0 0xff760000 0x0 0x1000>;
rockchip,grf = <&grf>;
@@ -666,6 +678,7 @@
};

grf: syscon at ff770000 {
+ u-boot,dm-pre-reloc;
compatible = "rockchip,rk3368-grf", "syscon";
reg = <0x0 0xff770000 0x0 0x1000>;
};
--
2.1.4