From: Marcel Ziswiler <marcel@ziswiler.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 2/3] apalis_t30: fix pcie port 0 and 1 pin muxing
Date: Tue, 8 Aug 2017 14:43:44 +0200 [thread overview]
Message-ID: <20170808124345.5252-3-marcel@ziswiler.com> (raw)
In-Reply-To: <20170808124345.5252-1-marcel@ziswiler.com>
From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Fix optional Apalis type specific 4 lane PCIe port 0 and Apalis PCIe
port 1 pin muxing.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---
board/toradex/apalis_t30/pinmux-config-apalis_t30.h | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/board/toradex/apalis_t30/pinmux-config-apalis_t30.h b/board/toradex/apalis_t30/pinmux-config-apalis_t30.h
index e0b00ea..6c30631 100644
--- a/board/toradex/apalis_t30/pinmux-config-apalis_t30.h
+++ b/board/toradex/apalis_t30/pinmux-config-apalis_t30.h
@@ -285,14 +285,14 @@ static struct pmux_pingrp_config tegra3_pinmux_common[] = {
DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT),
- DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, RSVD2, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, RSVD2, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, RSVD2, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT),
- DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, DOWN, TRISTATE, OUTPUT), /* NC */
- DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, DOWN, TRISTATE, OUTPUT), /* NC */
- DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, DOWN, TRISTATE, OUTPUT), /* NC */
+ DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, RSVD2, DOWN, TRISTATE, OUTPUT), /* NC */
+ DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, RSVD2, DOWN, TRISTATE, OUTPUT), /* NC */
+ DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, RSVD2, DOWN, TRISTATE, OUTPUT), /* NC */
DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT),
DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT),
--
2.9.4
next prev parent reply other threads:[~2017-08-08 12:43 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-08 12:43 [U-Boot] [PATCH 0/3] fix apalis_t30 optional pcie operation Marcel Ziswiler
2017-08-08 12:43 ` [U-Boot] [PATCH 1/3] apalis_t30: describe pcie ports Marcel Ziswiler
2017-08-13 21:35 ` Simon Glass
2017-08-08 12:43 ` Marcel Ziswiler [this message]
2017-08-08 12:43 ` [U-Boot] [PATCH 3/3] apalis_t30: fix optional pcie port reset for reliable pcie operation Marcel Ziswiler
2017-08-08 16:14 ` Stephen Warren
2017-08-09 14:53 ` Marcel Ziswiler
2017-08-09 15:59 ` Stephen Warren
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