[U-Boot] [PATCH 3/3] apalis_t30: fix optional pcie port reset for reliable pcie operation

[Marcel Ziswiler <marcel@ziswiler.com>]

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Allow optionally bringing up the Apalis type specific 4 lane PCIe port
as well as the PCIe switch as found on the Apalis Evaluation board. In
order to avoid violating the PCIe reset timing do this by overriding the
tegra_pcie_board_port_reset() function. Note however that both the
Apalis type specific 4 lane PCIe port as well as the regular Apalis PCIe
port are also left disabled in the device tree by default.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---

 board/toradex/apalis_t30/apalis_t30.c | 47 +++++++++++++++++++++++++++++++++++
 include/configs/apalis_t30.h          |  1 +
 2 files changed, 48 insertions(+)

diff --git a/board/toradex/apalis_t30/apalis_t30.c b/board/toradex/apalis_t30/apalis_t30.c
index 827eefd..e997429 100644
--- a/board/toradex/apalis_t30/apalis_t30.c
+++ b/board/toradex/apalis_t30/apalis_t30.c
@@ -14,6 +14,7 @@
 #include <asm/io.h>
 #include <dm.h>
 #include <i2c.h>
+#include <pci_tegra.h>
 #include "../common/tdx-common.h"
 
 #include "pinmux-config-apalis_t30.h"
@@ -23,6 +24,11 @@ DECLARE_GLOBAL_DATA_PTR;
 #define PMU_I2C_ADDRESS		0x2D
 #define MAX_I2C_RETRY		3
 
+#ifdef APALIS_T30_PCIE_EVALBOARD_INIT
+#define PEX_PERST_N	TEGRA_GPIO(S, 7) /* Apalis GPIO7 */
+#define RESET_MOCI_CTRL	TEGRA_GPIO(I, 4)
+#endif /* APALIS_T30_PCIE_EVALBOARD_INIT */
+
 int arch_misc_init(void)
 {
 	if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) ==
@@ -107,6 +113,47 @@ int tegra_pcie_board_init(void)
 		return err;
 	}
 
+#ifdef APALIS_T30_PCIE_EVALBOARD_INIT
+	gpio_request(PEX_PERST_N, "PEX_PERST_N");
+	gpio_request(RESET_MOCI_CTRL, "RESET_MOCI_CTRL");
+#endif /* APALIS_T30_PCIE_EVALBOARD_INIT */
+
 	return 0;
 }
+
+void tegra_pcie_board_port_reset(void *port)
+{
+	int index = tegra_pcie_port_index_of_port(port);
+	if (index == 2) { /* I210 Gigabit Ethernet Controller (On-module) */
+		tegra_pcie_port_reset(port);
+#ifdef APALIS_T30_PCIE_EVALBOARD_INIT
+	} else if (index == 1) { /* Apalis PCIe */
+		/*
+		 * As port 0 and 1 share the same RESET_MOCI only assert it once
+		 * for both ports below to avoid loosing the previously brought
+		 * up port again.
+		 */
+	} else if (index == 0) { /* Apalis Type Specific 4 Lane PCIe */
+		/*
+		 * Reset PLX PEX 8605 PCIe Switch plus PCIe devices on Apalis
+		 * Evaluation Board
+		 */
+		gpio_direction_output(PEX_PERST_N, 0);
+		gpio_direction_output(RESET_MOCI_CTRL, 0);
+
+		/*
+		 * Must be asserted for 100 ms after power and clocks are stable
+		 */
+		mdelay(100);
+
+		gpio_set_value(PEX_PERST_N, 1);
+		/*
+		 * Err_5: PEX_REFCLK_OUTpx/nx Clock Outputs is not Guaranteed
+		 * Until 900 us After PEX_PERST# De-assertion
+		 */
+		mdelay(1);
+		gpio_set_value(RESET_MOCI_CTRL, 1);
+#endif /* APALIS_T30_PCIE_EVALBOARD_INIT */
+	}
+}
 #endif /* CONFIG_PCI_TEGRA */
diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h
index daa3be0..f2a8b03 100644
--- a/include/configs/apalis_t30.h
+++ b/include/configs/apalis_t30.h
@@ -36,6 +36,7 @@
 
 /* PCI host support */
 #define CONFIG_CMD_PCI
+#undef APALIS_T30_PCIE_EVALBOARD_INIT
 
 /* PCI networking support */
 #define CONFIG_E1000_NO_NVM
-- 
2.9.4