[U-Boot] [PATCH 1/3] apalis_t30: describe pcie ports

Marcel Ziswiler
2017-08-08T12:43:43Z

From: Marcel Ziswiler <marcel.ziswiler@toradex.com>

Add some more comments describing the various PCIe ports available.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---

arch/arm/dts/tegra30-apalis.dts | 3 +++
1 file changed, 3 insertions(+)

diff --git a/arch/arm/dts/tegra30-apalis.dts b/arch/arm/dts/tegra30-apalis.dts
index 0b84dae..0852d8d 100644
--- a/arch/arm/dts/tegra30-apalis.dts
+++ b/arch/arm/dts/tegra30-apalis.dts
@@ -43,16 +43,19 @@
vddio-pex-ctl-supply = <&sys_3v3_reg>;
hvdd-pex-supply = <&sys_3v3_reg>;

+ /* Apalis Type Specific 4 Lane PCIe */
pci at 1,0 {
/* TS_DIFF1/2/3/4 left disabled */
nvidia,num-lanes = <4>;
};

+ /* Apalis PCIe */
pci at 2,0 {
/* PCIE1_RX/TX left disabled */
nvidia,num-lanes = <1>;
};

+ /* I210 Gigabit Ethernet Controller (On-module) */
pci at 3,0 {
status = "okay";
nvidia,num-lanes = <1>;
--
2.9.4