From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tom Rini Date: Tue, 9 Jan 2018 08:46:43 -0500 Subject: [U-Boot] [PATCH v2 01/12] riscv: cpu: Add nx25 to support RISC-V In-Reply-To: References: <1514267759-3508-1-git-send-email-uboot@andestech.com> <1514267759-3508-2-git-send-email-uboot@andestech.com> Message-ID: <20180109134643.GK2621@bill-the-cat> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit To: u-boot@lists.denx.de On Tue, Jan 09, 2018 at 01:47:23PM +0800, 陳建志 wrote: > Hi Tom > > How about the Andes NX25 cpu for RISC-V arch patchsets [PATCH v2 x/12] > reviewing status ? > Is everything ok ? Yes, I think everything is OK. Can you please also include an update to .travis.yml that gets the architecture to be built during CI? Thanks! -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: not available URL: