From mboxrd@z Thu Jan 1 00:00:00 1970 From: Anatolij Gustschin Date: Wed, 10 Jan 2018 14:07:46 +0100 Subject: [U-Boot] [PATCH v3 4/6] am335x-fb: setup display PLL In-Reply-To: <1515520896-18833-5-git-send-email-oe5hpm@oevsv.at> References: <1515520896-18833-1-git-send-email-oe5hpm@oevsv.at> <1515520896-18833-5-git-send-email-oe5hpm@oevsv.at> Message-ID: <20180110140746.36214744@crub> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Tue, 9 Jan 2018 19:01:34 +0100 Hannes Schmelzer oe5hpm at oevsv.at wrote: > The LCDC IP-core an be feed from several clock sources, one of those is > a dedicated DPLL for generating a dividable base-clock for this IP-core. > > The TRM specifies the maximum input frequency for the LCCD with 200 MHz, > so we must not exceed this value with the PLL frequency (which can lock > much higher). > > This patch tries every combination of multipliers and divisors of the > PLL and the IP-core itself for getting as near as possible the the > requested panel->pxl_clk. > > Signed-off-by: Hannes Schmelzer Reviewed-by: Anatolij Gustschin