[U-Boot] [RESEND PATCH 08/14] board: stm32f429-disco: switch to DM STM32 clock driver

patrice.chotard at st.com
2017-12-12T08:49:39Z

Use available DM clk_stm32f.c driver instead of dedicated
mach-stm32/stm32f4/clock.c.

Migrate periph_clock defines from stm32_periph.h directly in
CLK driver. These periph_clock defines will be removed when STMMAC,
TIMER2 and SYSCFG drivers will support DM CLK.

Enable also CLK flag.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/include/asm/arch-stm32f4/stm32.h | 17 --
arch/arm/mach-stm32/stm32f4/Makefile | 2 +-
arch/arm/mach-stm32/stm32f4/clock.c | 258 ---------------------
board/st/stm32f429-discovery/stm32f429-discovery.c | 24 +-
configs/stm32f429-discovery_defconfig | 1 +
drivers/clk/clk_stm32f.c | 7 +-
6 files changed, 9 insertions(+), 300 deletions(-)
delete mode 100644 arch/arm/mach-stm32/stm32f4/clock.c

diff --git a/arch/arm/include/asm/arch-stm32f4/stm32.h b/arch/arm/include/asm/arch-stm32f4/stm32.h
index bd5c2ec..889778c 100644
--- a/arch/arm/include/asm/arch-stm32f4/stm32.h
+++ b/arch/arm/include/asm/arch-stm32f4/stm32.h
@@ -42,11 +42,6 @@ struct stm32_u_id_regs {
u32 u_id_high;
};

-struct stm32_pwr_regs {
- u32 cr;
- u32 csr;
-};
-
/*
* Registers access macros
*/
@@ -56,9 +51,6 @@ struct stm32_pwr_regs {
#define STM32_RCC_BASE (STM32_AHB1PERIPH_BASE + 0x3800)
#define STM32_RCC ((struct stm32_rcc_regs *)STM32_RCC_BASE)

-#define STM32_PWR_BASE (STM32_APB1PERIPH_BASE + 0x7000)
-#define STM32_PWR ((struct stm32_pwr_regs *)STM32_PWR_BASE)
-
#define FLASH_CNTL_BASE (STM32_AHB1PERIPH_BASE + 0x3C00)

static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
@@ -67,15 +59,6 @@ static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
[5 ... 11] = 128 * 1024
};

-enum clock {
- CLOCK_CORE,
- CLOCK_AHB,
- CLOCK_APB1,
- CLOCK_APB2
-};
-
-int configure_clocks(void);
-unsigned long clock_get(enum clock clck);
void stm32_flash_latency_cfg(int latency);

#endif /* _MACH_STM32_H_ */
diff --git a/arch/arm/mach-stm32/stm32f4/Makefile b/arch/arm/mach-stm32/stm32f4/Makefile
index 63db820..86c81bb 100644
--- a/arch/arm/mach-stm32/stm32f4/Makefile
+++ b/arch/arm/mach-stm32/stm32f4/Makefile
@@ -8,4 +8,4 @@
# SPDX-License-Identifier: GPL-2.0+
#

-obj-y += clock.o timer.o
+obj-y += timer.o
diff --git a/arch/arm/mach-stm32/stm32f4/clock.c b/arch/arm/mach-stm32/stm32f4/clock.c
deleted file mode 100644
index 774591d..0000000
--- a/arch/arm/mach-stm32/stm32f4/clock.c
+++ /dev/null
@@ -1,258 +0,0 @@
-/*
- * (C) Copyright 2015
- * Kamil Lulko, <kamil.lulko@gmail.com>
- *
- * (C) Copyright 2014
- * STMicroelectronics
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <stm32_rcc.h>
-#include <asm/io.h>
-#include <asm/arch/stm32.h>
-#include <asm/arch/stm32_periph.h>
-
-#define RCC_CR_HSION (1 << 0)
-#define RCC_CR_HSEON (1 << 16)
-#define RCC_CR_HSERDY (1 << 17)
-#define RCC_CR_HSEBYP (1 << 18)
-#define RCC_CR_CSSON (1 << 19)
-#define RCC_CR_PLLON (1 << 24)
-#define RCC_CR_PLLRDY (1 << 25)
-
-#define RCC_PLLCFGR_PLLM_MASK 0x3F
-#define RCC_PLLCFGR_PLLN_MASK 0x7FC0
-#define RCC_PLLCFGR_PLLP_MASK 0x30000
-#define RCC_PLLCFGR_PLLQ_MASK 0xF000000
-#define RCC_PLLCFGR_PLLSRC (1 << 22)
-#define RCC_PLLCFGR_PLLN_SHIFT 6
-#define RCC_PLLCFGR_PLLP_SHIFT 16
-#define RCC_PLLCFGR_PLLQ_SHIFT 24
-
-#define RCC_CFGR_AHB_PSC_MASK 0xF0
-#define RCC_CFGR_APB1_PSC_MASK 0x1C00
-#define RCC_CFGR_APB2_PSC_MASK 0xE000
-#define RCC_CFGR_SW0 (1 << 0)
-#define RCC_CFGR_SW1 (1 << 1)
-#define RCC_CFGR_SW_MASK 0x3
-#define RCC_CFGR_SW_HSI 0
-#define RCC_CFGR_SW_HSE RCC_CFGR_SW0
-#define RCC_CFGR_SW_PLL RCC_CFGR_SW1
-#define RCC_CFGR_SWS0 (1 << 2)
-#define RCC_CFGR_SWS1 (1 << 3)
-#define RCC_CFGR_SWS_MASK 0xC
-#define RCC_CFGR_SWS_HSI 0
-#define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0
-#define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1
-#define RCC_CFGR_HPRE_SHIFT 4
-#define RCC_CFGR_PPRE1_SHIFT 10
-#define RCC_CFGR_PPRE2_SHIFT 13
-
-#define RCC_APB1ENR_PWREN (1 << 28)
-
-/*
- * RCC USART specific definitions
- */
-#define RCC_ENR_USART1EN (1 << 4)
-#define RCC_ENR_USART2EN (1 << 17)
-#define RCC_ENR_USART3EN (1 << 18)
-#define RCC_ENR_USART6EN (1 << 5)
-
-#define PWR_CR_VOS0 (1 << 14)
-#define PWR_CR_VOS1 (1 << 15)
-#define PWR_CR_VOS_MASK 0xC000
-#define PWR_CR_VOS_SCALE_MODE_1 (PWR_CR_VOS0 | PWR_CR_VOS1)
-#define PWR_CR_VOS_SCALE_MODE_2 (PWR_CR_VOS1)
-#define PWR_CR_VOS_SCALE_MODE_3 (PWR_CR_VOS0)
-
-/*
- * RCC GPIO specific definitions
- */
-#define RCC_ENR_GPIO_A_EN (1 << 0)
-#define RCC_ENR_GPIO_B_EN (1 << 1)
-#define RCC_ENR_GPIO_C_EN (1 << 2)
-#define RCC_ENR_GPIO_D_EN (1 << 3)
-#define RCC_ENR_GPIO_E_EN (1 << 4)
-#define RCC_ENR_GPIO_F_EN (1 << 5)
-#define RCC_ENR_GPIO_G_EN (1 << 6)
-#define RCC_ENR_GPIO_H_EN (1 << 7)
-#define RCC_ENR_GPIO_I_EN (1 << 8)
-#define RCC_ENR_GPIO_J_EN (1 << 9)
-#define RCC_ENR_GPIO_K_EN (1 << 10)
-
-#if !defined(CONFIG_STM32_HSE_HZ)
-#error "CONFIG_STM32_HSE_HZ not defined!"
-#else
-#if (CONFIG_STM32_HSE_HZ == 8000000)
-#if (CONFIG_SYS_CLK_FREQ == 180000000)
-/* 180 MHz */
-struct pll_psc sys_pll_psc = {
- .pll_m = 8,
- .pll_n = 360,
- .pll_p = 2,
- .pll_q = 8,
- .ahb_psc = AHB_PSC_1,
- .apb1_psc = APB_PSC_4,
- .apb2_psc = APB_PSC_2
-};
-#else
-/* default 168 MHz */
-struct pll_psc sys_pll_psc = {
- .pll_m = 8,
- .pll_n = 336,
- .pll_p = 2,
- .pll_q = 7,
- .ahb_psc = AHB_PSC_1,
- .apb1_psc = APB_PSC_4,
- .apb2_psc = APB_PSC_2
-};
-#endif
-#else
-#error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists"
-#endif
-#endif
-
-int configure_clocks(void)
-{
- /* Reset RCC configuration */
- setbits_le32(&STM32_RCC->cr, RCC_CR_HSION);
- writel(0, &STM32_RCC->cfgr); /* Reset CFGR */
- clrbits_le32(&STM32_RCC->cr, (RCC_CR_HSEON | RCC_CR_CSSON
- | RCC_CR_PLLON));
- writel(0x24003010, &STM32_RCC->pllcfgr); /* Reset value from RM */
- clrbits_le32(&STM32_RCC->cr, RCC_CR_HSEBYP);
- writel(0, &STM32_RCC->cir); /* Disable all interrupts */
-
- /* Configure for HSE+PLL operation */
- setbits_le32(&STM32_RCC->cr, RCC_CR_HSEON);
- while (!(readl(&STM32_RCC->cr) & RCC_CR_HSERDY))
- ;
-
- /* Enable high performance mode, System frequency up to 180 MHz */
- setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_PWREN);
- writel(PWR_CR_VOS_SCALE_MODE_1, &STM32_PWR->cr);
-
- setbits_le32(&STM32_RCC->cfgr, ((
- sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT)
- | (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT)
- | (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
-
- writel(sys_pll_psc.pll_m
- | (sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT)
- | (((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT)
- | (sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT),
- &STM32_RCC->pllcfgr);
- setbits_le32(&STM32_RCC->pllcfgr, RCC_PLLCFGR_PLLSRC);
-
- setbits_le32(&STM32_RCC->cr, RCC_CR_PLLON);
-
- while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY))
- ;
-
- stm32_flash_latency_cfg(5);
- clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
- setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL);
-
- while ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) !=
- RCC_CFGR_SWS_PLL)
- ;
-
- return 0;
-}
-
-unsigned long clock_get(enum clock clck)
-{
- u32 sysclk = 0;
- u32 shift = 0;
- /* Prescaler table lookups for clock computation */
- u8 ahb_psc_table[16] = {
- 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
- };
- u8 apb_psc_table[8] = {
- 0, 0, 0, 0, 1, 2, 3, 4
- };
-
- if ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) ==
- RCC_CFGR_SWS_PLL) {
- u16 pllm, plln, pllp;
- pllm = (readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
- plln = ((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
- >> RCC_PLLCFGR_PLLN_SHIFT);
- pllp = ((((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
- >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
- sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp;
- }
-
- switch (clck) {
- case CLOCK_CORE:
- return sysclk;
- break;
- case CLOCK_AHB:
- shift = ahb_psc_table[(
- (readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK)
- >> RCC_CFGR_HPRE_SHIFT)];
- return sysclk >>= shift;
- break;
- case CLOCK_APB1:
- shift = apb_psc_table[(
- (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB1_PSC_MASK)
- >> RCC_CFGR_PPRE1_SHIFT)];
- return sysclk >>= shift;
- break;
- case CLOCK_APB2:
- shift = apb_psc_table[(
- (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB2_PSC_MASK)
- >> RCC_CFGR_PPRE2_SHIFT)];
- return sysclk >>= shift;
- break;
- default:
- return 0;
- break;
- }
-}
-
-void clock_setup(int peripheral)
-{
- switch (peripheral) {
- case USART1_CLOCK_CFG:
- setbits_le32(&STM32_RCC->apb2enr, RCC_ENR_USART1EN);
- break;
- case GPIO_A_CLOCK_CFG:
- setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_A_EN);
- break;
- case GPIO_B_CLOCK_CFG:
- setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_B_EN);
- break;
- case GPIO_C_CLOCK_CFG:
- setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_C_EN);
- break;
- case GPIO_D_CLOCK_CFG:
- setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_D_EN);
- break;
- case GPIO_E_CLOCK_CFG:
- setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_E_EN);
- break;
- case GPIO_F_CLOCK_CFG:
- setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_F_EN);
- break;
- case GPIO_G_CLOCK_CFG:
- setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_G_EN);
- break;
- case GPIO_H_CLOCK_CFG:
- setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_H_EN);
- break;
- case GPIO_I_CLOCK_CFG:
- setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_I_EN);
- break;
- case GPIO_J_CLOCK_CFG:
- setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_J_EN);
- break;
- case GPIO_K_CLOCK_CFG:
- setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_K_EN);
- break;
- default:
- break;
- }
-}
diff --git a/board/st/stm32f429-discovery/stm32f429-discovery.c b/board/st/stm32f429-discovery/stm32f429-discovery.c
index 7e62bd2..c5f4573 100644
--- a/board/st/stm32f429-discovery/stm32f429-discovery.c
+++ b/board/st/stm32f429-discovery/stm32f429-discovery.c
@@ -13,12 +13,10 @@

#include <common.h>
#include <dm.h>
-#include <stm32_rcc.h>
+
#include <asm/io.h>
#include <asm/arch/stm32.h>
#include <asm/arch/gpio.h>
-#include <asm/arch/stm32_periph.h>
-#include <asm/arch/stm32_defs.h>

DECLARE_GLOBAL_DATA_PTR;

@@ -48,7 +46,6 @@ int uart_setup_gpio(void)
int i;
int rv = 0;

- clock_setup(GPIO_A_CLOCK_CFG);
for (i = 0; i < ARRAY_SIZE(usart_gpio); i++) {
rv = stm32_gpio_config(&usart_gpio[i], &gpio_ctl_usart);
if (rv)
@@ -114,13 +111,6 @@ static int fmc_setup_gpio(void)
int rv = 0;
int i;

- clock_setup(GPIO_B_CLOCK_CFG);
- clock_setup(GPIO_C_CLOCK_CFG);
- clock_setup(GPIO_D_CLOCK_CFG);
- clock_setup(GPIO_E_CLOCK_CFG);
- clock_setup(GPIO_F_CLOCK_CFG);
- clock_setup(GPIO_G_CLOCK_CFG);
-
for (i = 0; i < ARRAY_SIZE(ext_ram_fmc_gpio); i++) {
rv = stm32_gpio_config(&ext_ram_fmc_gpio[i],
&gpio_ctl_fmc);
@@ -132,11 +122,6 @@ out:
return rv;
}

-/*
- * STM32 RCC FMC specific definitions
- */
-#define STM32_RCC_ENR_FMC (1 << 0) /* FMC module clock */
-
int dram_init(void)
{
int rv;
@@ -145,9 +130,6 @@ int dram_init(void)
rv = fmc_setup_gpio();
if (rv)
return rv;
-
- setbits_le32(&STM32_RCC->ahb3enr, STM32_RCC_ENR_FMC);
-
rv = uclass_get_device(UCLASS_RAM, 0, &dev);
if (rv) {
debug("DRAM init failed: %d\n", rv);
@@ -176,13 +158,9 @@ int board_early_init_f(void)
{
int res;

- configure_clocks();
-
res = uart_setup_gpio();
if (res)
return res;
- clock_setup(USART1_CLOCK_CFG);
-
return 0;
}

diff --git a/configs/stm32f429-discovery_defconfig b/configs/stm32f429-discovery_defconfig
index ae106ff..ee50b35 100644
--- a/configs/stm32f429-discovery_defconfig
+++ b/configs/stm32f429-discovery_defconfig
@@ -19,6 +19,7 @@ CONFIG_CMD_TIMER=y
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_CLK=y
CONFIG_MISC=y
CONFIG_STM32_RCC=y
# CONFIG_MMC is not set
diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/clk_stm32f.c
index 634f071..63116e0 100644
--- a/drivers/clk/clk_stm32f.c
+++ b/drivers/clk/clk_stm32f.c
@@ -12,7 +12,6 @@

#include <asm/io.h>
#include <asm/arch/stm32.h>
-#include <asm/arch/stm32_periph.h>
#include <asm/arch/stm32_pwr.h>

#include <dt-bindings/mfd/stm32f7-rcc.h>
@@ -88,6 +87,12 @@
*/
#define RCC_APB2ENR_SYSCFGEN BIT(14)

+enum periph_clock {
+ SYSCFG_CLOCK_CFG,
+ TIMER2_CLOCK_CFG,
+ STMMAC_CLOCK_CFG,
+};
+
struct stm32_clk_info stm32f4_clk_info = {
/* 180 MHz */
.sys_pll_psc = {
--
1.9.1