From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tom Rini Date: Mon, 15 Jan 2018 08:52:28 -0500 Subject: [U-Boot] [U-Boot, v2, 01/12] riscv: cpu: Add nx25 to support RISC-V In-Reply-To: <1514267759-3508-2-git-send-email-uboot@andestech.com> References: <1514267759-3508-2-git-send-email-uboot@andestech.com> Message-ID: <20180115135228.GW4660@bill-the-cat> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Tue, Dec 26, 2017 at 01:55:48PM +0800, Andes wrote: > From: Rick Chen > > Add Andes nx25 cpu core (called AndesStar V5) to support RISC-V arch > > Verifications: > 1. startup and relocation ok. > 2. boot from rom or ram both ok. > 2. timer driver ok. > 3. uart driver ok > 4. mmc driver ok > 5. spi driver ok. > 6. 32/64 bit both ok. > > Detail verification message please see doc/README.ae250. > > Signed-off-by: Rick Chen > Signed-off-by: Rick Chen > Signed-off-by: Greentime Hu > Cc: Padmarao Begari Applied to u-boot/master. But that said, the whole of arch/riscv/ and board/AndesTech/nx25-ae250/ introduces some checkpatch.pl issues, please investigate and fix appropriate ones, thanks! -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: not available URL: