From mboxrd@z Thu Jan 1 00:00:00 1970 From: Peng Fan Date: Fri, 19 Jan 2018 17:09:18 +0800 Subject: [U-Boot] [PATCH 1/5] imx: mx7: change sdhc clk to 392M Message-ID: <20180119090922.32320-1-peng.fan@nxp.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Change sdhc clk to 392M. Prepare support for SDR104 and HS200. Signed-off-by: Peng Fan Cc: Stefano Babic Cc: Fabio Estevam Cc: Jaehoon Chung --- arch/arm/mach-imx/mx7/clock.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-imx/mx7/clock.c b/arch/arm/mach-imx/mx7/clock.c index c11042d6f5..227037c53d 100644 --- a/arch/arm/mach-imx/mx7/clock.c +++ b/arch/arm/mach-imx/mx7/clock.c @@ -561,17 +561,17 @@ static void init_clk_esdhc(void) /* 196: 392/2 */ target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK | CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | - CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2); + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); clock_set_target_val(USDHC1_CLK_ROOT, target); target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK | CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | - CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2); + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); clock_set_target_val(USDHC2_CLK_ROOT, target); target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK | CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | - CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2); + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); clock_set_target_val(USDHC3_CLK_ROOT, target); /* enable the clock gate */ -- 2.14.1