[U-Boot] [PATCH v10 07/12] mips: bmips: add bcm63xx-spi driver support for BCM6348

Álvaro Fernández Rojas
2018-01-23T16:15:00Z

This driver manages the SPI controller present on this SoC.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
v10: no changes
v9: no changes
v8: no changes
v7: no changes
v6: no changes
v5: no changes
v4: no changes
v3: rename BCM6338 SPI driver to BCM6348
v2: add spi alias

arch/mips/dts/brcm,bcm6348.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)

diff --git a/arch/mips/dts/brcm,bcm6348.dtsi b/arch/mips/dts/brcm,bcm6348.dtsi
index 711b643b5a..540b9fea5b 100644
--- a/arch/mips/dts/brcm,bcm6348.dtsi
+++ b/arch/mips/dts/brcm,bcm6348.dtsi
@@ -12,6 +12,10 @@
/ {
compatible = "brcm,bcm6348";

+ aliases {
+ spi0 = &spi;
+ };
+
cpus {
reg = <0xfffe0000 0x4>;
#address-cells = <1>;
@@ -118,6 +122,19 @@
status = "disabled";
};

+ spi: spi at fffe0c00 {
+ compatible = "brcm,bcm6348-spi";
+ reg = <0xfffe0c00 0xc0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&periph_clk BCM6348_CLK_SPI>;
+ resets = <&periph_rst BCM6348_RST_SPI>;
+ spi-max-frequency = <20000000>;
+ num-cs = <4>;
+
+ status = "disabled";
+ };
+
memory-controller at fffe2300 {
compatible = "brcm,bcm6338-mc";
reg = <0xfffe2300 0x38>;
--
2.11.0