From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Sun, 4 Feb 2018 21:10:18 +0100 Subject: [U-Boot] [PATCH v2 6/9] mips: bmips: add support for bcm6362 usb In-Reply-To: <20180204201021.1635-1-noltari@gmail.com> References: <20180204101934.27842-1-noltari@gmail.com> <20180204201021.1635-1-noltari@gmail.com> Message-ID: <20180204201021.1635-7-noltari@gmail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit To: u-boot@lists.denx.de Signed-off-by: Álvaro Fernández Rojas --- v2: no changes arch/mips/dts/brcm,bcm6362.dtsi | 30 ++++++++++++++++++++++++++++++ include/configs/bmips_bcm6362.h | 7 +++++++ 2 files changed, 37 insertions(+) diff --git a/arch/mips/dts/brcm,bcm6362.dtsi b/arch/mips/dts/brcm,bcm6362.dtsi index 921fcd52c3..20a589b007 100644 --- a/arch/mips/dts/brcm,bcm6362.dtsi +++ b/arch/mips/dts/brcm,bcm6362.dtsi @@ -177,6 +177,36 @@ #power-domain-cells = <1>; }; + ehci: usb-controller at 10002500 { + compatible = "brcm,bcm6362-ehci", "generic-ehci"; + reg = <0x10002500 0x100>; + phys = <&usbh>; + big-endian; + + status = "disabled"; + }; + + ohci: usb-controller at 10002600 { + compatible = "brcm,bcm6362-ohci", "generic-ohci"; + reg = <0x10002600 0x100>; + phys = <&usbh>; + big-endian; + + status = "disabled"; + }; + + usbh: usb-phy at 10002700 { + compatible = "brcm,bcm6368-usbh"; + reg = <0x10002700 0x38>; + #phy-cells = <0>; + clocks = <&periph_clk BCM6362_CLK_USBH>; + clock-names = "usbh"; + power-domains = <&periph_pwr BCM6362_PWR_USBH>; + resets = <&periph_rst BCM6362_RST_USBH>; + + status = "disabled"; + }; + memory-controller at 10003000 { compatible = "brcm,bcm6328-mc"; reg = <0x10003000 0x864>; diff --git a/include/configs/bmips_bcm6362.h b/include/configs/bmips_bcm6362.h index 6ff0a33d49..79eeb17feb 100644 --- a/include/configs/bmips_bcm6362.h +++ b/include/configs/bmips_bcm6362.h @@ -14,6 +14,13 @@ #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_SDRAM_BASE 0x80000000 +/* USB */ +#define CONFIG_EHCI_DESC_BIG_ENDIAN +#define CONFIG_EHCI_MMIO_BIG_ENDIAN +#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_OHCI_NEW + /* U-Boot */ #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 -- 2.11.0