From mboxrd@z Thu Jan 1 00:00:00 1970 From: Miquel Raynal Date: Sat, 24 Feb 2018 17:35:06 +0100 Subject: [U-Boot] [PATCH v2 11/20] sunxi: spl: deassert the NAND controller reset line In-Reply-To: <20180222135335.q4kzk2gmodtuxvuj@flea.lan> References: <20180222133350.8033-1-miquel.raynal@bootlin.com> <20180222133350.8033-12-miquel.raynal@bootlin.com> <20180222135335.q4kzk2gmodtuxvuj@flea.lan> Message-ID: <20180224173506.653f9635@xps13> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable To: u-boot@lists.denx.de Hi Maxime, On Thu, 22 Feb 2018 14:53:35 +0100, Maxime Ripard wrote: > On Thu, Feb 22, 2018 at 02:33:41PM +0100, Miquel Raynal wrote: > > Ensure the NAND controller reset line is deasserted before use. > >=20 > > Signed-off-by: Miquel Raynal > > --- > > board/sunxi/board.c | 1 + > > 1 file changed, 1 insertion(+) > >=20 > > diff --git a/board/sunxi/board.c b/board/sunxi/board.c > > index 8891961dcc..54ac018b80 100644 > > --- a/board/sunxi/board.c > > +++ b/board/sunxi/board.c > > @@ -286,6 +286,7 @@ static void nand_clock_setup(void) > > (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; > > =20 > > setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0= )); > > + setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0)); =20 >=20 > This is only relevant for the SoCs after the A31 (sun6i, sun8i, and > probably the A80 (sun9i) and the armv8 (sun50i) families), so you > should put an ifdef there. Can you tell me if something like this would fit? =20 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NA= ND0)); +#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \ + defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0)); +#endif setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1= ); Thanks, Miqu=C3=A8l --=20 Miquel Raynal, Bootlin (formerly Free Electrons) Embedded Linux and Kernel engineering https://bootlin.com