[U-Boot] [PATCH] watchdog: omap_wdt: improve watchdog reset path

Lokesh Vutla
2018-03-02T09:13:24Z

On Thursday 01 March 2018 06:45 AM, Ruslan Bilovol wrote:
> Remove busy looping during watchdog reset.
> Each polling of W_PEND_WTGR bit ("finish posted
> write") after watchdog reset takes 120-140us
> on BeagleBone Black board. Current U-Boot code
> has watchdog resets in random places and often
> there is situation when watchdog is reset
> few times in a row in nested functions.
> This adds extra delays and slows the whole system.
>
> Instead of polling W_PEND_WTGR bit, we skip
> watchdog reset if the bit is set. Anyway, watchdog
> is in the middle of reset *right now*, so we can
> just return.
>
> This noticeably increases performance of the
> system. Below are some measurements on BBB:
> - DFU upload over USB 15% faster
> - fastboot image upload 3x times faster
> - USB ep0 transfers with 4k packets 20% faster
>
> Signed-off-by: Ruslan Bilovol <ruslan.bilovol at gmail.com

Given the limited usage of trigger register in this driver, I do not see
any issue with this patch.

Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>

Thanks and regards,
Lokesh

> ---
> drivers/watchdog/omap_wdt.c | 21 +++++++++++++++------
> 1 file changed, 15 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/watchdog/omap_wdt.c b/drivers/watchdog/omap_wdt.c
> index 7b1f429..d724c96 100644
> --- a/drivers/watchdog/omap_wdt.c
> +++ b/drivers/watchdog/omap_wdt.c
> @@ -53,16 +53,25 @@ void hw_watchdog_reset(void)
> {
> struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
>
> - /* wait for posted write to complete */
> - while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WTGR)
> - ;
> + /*
> + * Somebody just triggered watchdog reset and write to WTGR register
> + * is in progress. It is resetting right now, no need to trigger it
> + * again
> + */
> + if ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WTGR)
> + return;
>
> wdt_trgr_pattern = ~wdt_trgr_pattern;
> writel(wdt_trgr_pattern, &wdt->wdtwtgr);
>
> - /* wait for posted write to complete */
> - while ((readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WTGR))
> - ;
> + /*
> + * Don't wait for posted write to complete, i.e. don't check
> + * WDT_WWPS_PEND_WTGR bit in WWPS register. There is no writes to
> + * WTGR register outside of this func, and if entering it
> + * we see WDT_WWPS_PEND_WTGR bit set, it means watchdog reset
> + * was just triggered. This prevents us from wasting time in busy
> + * polling of WDT_WWPS_PEND_WTGR bit.
> + */
> }
>
> static int omap_wdt_set_timeout(unsigned int timeout)
>