From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andre Przywara Date: Fri, 2 Mar 2018 00:56:45 +0000 Subject: [U-Boot] [PATCH v3 06/20] arm: dts: sunxi: update H3 to new EMAC binding In-Reply-To: <20180302005659.28728-1-andre.przywara@arm.com> References: <20180302005659.28728-1-andre.przywara@arm.com> Message-ID: <20180302005659.28728-7-andre.przywara@arm.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de The U-Boot driver for the sun8i-emac was using some preliminary DT binding. Now since Linux got its own driver in v4.15 and our driver can now cope with both bindings, let's convert the DT nodes used by the various H3 boards over to the new bindings used by the kernel. Signed-off-by: Andre Przywara --- arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts | 6 +-- arch/arm/dts/sun8i-h3-libretech-all-h3-cc.dts | 7 +-- arch/arm/dts/sun8i-h3-nanopi-neo.dts | 6 +-- arch/arm/dts/sun8i-h3-orangepi-2.dts | 7 +-- arch/arm/dts/sun8i-h3-orangepi-one.dts | 7 +-- arch/arm/dts/sun8i-h3-orangepi-pc.dts | 7 +-- arch/arm/dts/sun8i-h3-orangepi-plus.dts | 8 +++- arch/arm/dts/sun8i-h3-orangepi-plus2e.dts | 9 +++- arch/arm/dts/sun8i-h3.dtsi | 69 ++++++++++++++++++++------- 9 files changed, 75 insertions(+), 51 deletions(-) diff --git a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts index 20d489cb2a..e0efcb3ba3 100644 --- a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts +++ b/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts @@ -100,14 +100,10 @@ }; &emac { - phy = <&phy1>; + phy-handle = <&int_mii_phy>; phy-mode = "mii"; - allwinner,use-internal-phy; allwinner,leds-active-low; status = "okay"; - phy1: ethernet-phy at 1 { - reg = <1>; - }; }; &mmc0 { diff --git a/arch/arm/dts/sun8i-h3-libretech-all-h3-cc.dts b/arch/arm/dts/sun8i-h3-libretech-all-h3-cc.dts index 97b993f636..c8fd69f0a4 100644 --- a/arch/arm/dts/sun8i-h3-libretech-all-h3-cc.dts +++ b/arch/arm/dts/sun8i-h3-libretech-all-h3-cc.dts @@ -125,15 +125,10 @@ }; &emac { - phy = <&phy1>; + phy-handle = <&int_mii_phy>; phy-mode = "mii"; - allwinner,use-internal-phy; allwinner,leds-active-low; status = "okay"; - - phy1: ethernet-phy at 1 { - reg = <1>; - }; }; &ir { diff --git a/arch/arm/dts/sun8i-h3-nanopi-neo.dts b/arch/arm/dts/sun8i-h3-nanopi-neo.dts index 5113059098..78f6c24952 100644 --- a/arch/arm/dts/sun8i-h3-nanopi-neo.dts +++ b/arch/arm/dts/sun8i-h3-nanopi-neo.dts @@ -48,12 +48,8 @@ }; &emac { - phy = <&phy1>; + phy-handle = <&int_mii_phy>; phy-mode = "mii"; - allwinner,use-internal-phy; allwinner,leds-active-low; status = "okay"; - phy1: ethernet-phy at 1 { - reg = <1>; - }; }; diff --git a/arch/arm/dts/sun8i-h3-orangepi-2.dts b/arch/arm/dts/sun8i-h3-orangepi-2.dts index caa1a6959c..d97fdacb35 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-2.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-2.dts @@ -55,6 +55,7 @@ aliases { serial0 = &uart0; /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ + ethernet0 = &emac; ethernet1 = &rtl8189; }; @@ -110,14 +111,10 @@ }; &emac { - phy = <&phy1>; + phy-handle = <&int_mii_phy>; phy-mode = "mii"; - allwinner,use-internal-phy; allwinner,leds-active-low; status = "okay"; - phy1: ethernet-phy at 1 { - reg = <1>; - }; }; &ir { diff --git a/arch/arm/dts/sun8i-h3-orangepi-one.dts b/arch/arm/dts/sun8i-h3-orangepi-one.dts index 8df5c74f04..adab1cbfc9 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-one.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-one.dts @@ -53,6 +53,7 @@ compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -95,14 +96,10 @@ }; &emac { - phy = <&phy1>; + phy-handle = <&int_mii_phy>; phy-mode = "mii"; - allwinner,use-internal-phy; allwinner,leds-active-low; status = "okay"; - phy1: ethernet-phy at 1 { - reg = <1>; - }; }; &mmc0 { diff --git a/arch/arm/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/dts/sun8i-h3-orangepi-pc.dts index b8340f74e7..afba264ea5 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-pc.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-pc.dts @@ -53,6 +53,7 @@ compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3"; aliases { + ethernet0 = &emac; serial0 = &uart0; }; @@ -167,12 +168,8 @@ }; &emac { - phy = <&phy1>; + phy-handle = <&int_mii_phy>; phy-mode = "mii"; - allwinner,use-internal-phy; allwinner,leds-active-low; status = "okay"; - phy1: ethernet-phy at 1 { - reg = <1>; - }; }; diff --git a/arch/arm/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/dts/sun8i-h3-orangepi-plus.dts index e7079b26bc..136e4414a4 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-plus.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-plus.dts @@ -82,7 +82,13 @@ pinctrl-0 = <&emac_rgmii_pins>; phy-supply = <®_gmac_3v3>; phy-mode = "rgmii"; - /delete-property/allwinner,use-internal-phy; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy at 1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; }; &mmc2 { diff --git a/arch/arm/dts/sun8i-h3-orangepi-plus2e.dts b/arch/arm/dts/sun8i-h3-orangepi-plus2e.dts index f97b040b35..51aaf49b6d 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-plus2e.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-plus2e.dts @@ -69,8 +69,15 @@ pinctrl-names = "default"; pinctrl-0 = <&emac_rgmii_pins>; phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; phy-mode = "rgmii"; - /delete-property/allwinner,use-internal-phy; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy at 1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; }; &pio { diff --git a/arch/arm/dts/sun8i-h3.dtsi b/arch/arm/dts/sun8i-h3.dtsi index afa60793a2..39a6438ec4 100644 --- a/arch/arm/dts/sun8i-h3.dtsi +++ b/arch/arm/dts/sun8i-h3.dtsi @@ -144,9 +144,10 @@ #size-cells = <1>; ranges; - syscon: syscon at 01c00000 { - compatible = "allwinner,sun8i-h3-syscon","syscon"; - reg = <0x01c00000 0x34>; + syscon: syscon at 1c00000 { + compatible = "allwinner,sun8i-h3-system-controller", + "syscon"; + reg = <0x01c00000 0x1000>; }; dma: dma-controller at 01c02000 { @@ -339,15 +340,12 @@ interrupt-controller; #interrupt-cells = <3>; - emac_rgmii_pins: emac0 at 0 { - allwinner,pins = "PD0", "PD1", "PD2", "PD3", - "PD4", "PD5", "PD7", - "PD8", "PD9", "PD10", - "PD12", "PD13", "PD15", - "PD16", "PD17"; - allwinner,function = "emac"; - allwinner,drive = ; - allwinner,pull = ; + emac_rgmii_pins: emac0 { + pins = "PD0", "PD1", "PD2", "PD3", "PD4", + "PD5", "PD7", "PD8", "PD9", "PD10", + "PD12", "PD13", "PD15", "PD16", "PD17"; + function = "emac"; + drive-strength = <40>; }; mmc0_pins_a: mmc0 at 0 { @@ -466,16 +464,51 @@ emac: ethernet at 1c30000 { compatible = "allwinner,sun8i-h3-emac"; - reg = <0x01c30000 0x104>, <0x01c00030 0x4>; - reg-names = "emac", "syscon"; + syscon = <&syscon>; + reg = <0x01c30000 0x10000>; interrupts = ; - resets = <&ccu RST_BUS_EMAC>, <&ccu RST_BUS_EPHY>; - reset-names = "ahb", "ephy"; - clocks = <&ccu CLK_BUS_EMAC>, <&ccu CLK_BUS_EPHY>; - clock-names = "ahb", "ephy"; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + }; + + mdio-mux { + compatible = "allwinner,sun8i-h3-mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + + mdio-parent-bus = <&mdio>; + /* Only one MDIO is usable at the time */ + internal_mdio: mdio at 1 { + compatible = "allwinner,sun8i-h3-mdio-internal"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + int_mii_phy: ethernet-phy at 1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + }; + }; + + external_mdio: mdio at 2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; }; gic: interrupt-controller at 01c81000 { -- 2.14.1