[U-Boot] [PATCH v2 0/9] splash screen on the stm32f746 disco board

[U-Boot] [PATCH v2 0/9] splash screen on the stm32f746 disco board

[yannick fertre]

Version 2:
- Add patch to display bitmap stmicroelectronics_uboot_logo_8bit_rle
- Add patch to defconfig to add splash screen
- Rename panel in dts.

Version 1:
- Initial commit

This serie contains all patchsets needed for displaying a splash screen 
on the stm32f746 disco board & some display features (reset, blending & line
interrupt position).

Philippe CORNU (1):
  arm: dts: stm32: add ltdc for STM32F746

yannick fertre (8):
  video: stm32: stm32_ltdc: add reset
  video: stm32: stm32_ltdc: update file header & footer
  video: stm32: stm32_ltdc: set rate of the pixel clock
  video: stm32: stm32_ltdc: missing set of line interrupt position
  video: stm32: stm32_ltdc: set the blending factor
  arm: dts: stm32: add display for STM32F746 disco board
  stm32f7: board: add splash screen
  board: Add display to STM32F746 SoC discovery board

 arch/arm/dts/stm32f746-disco.dts           |   70 +
 arch/arm/dts/stm32f746.dtsi                |    9 +
 board/st/stm32f746-disco/stm32f746-disco.c |    9 +
 configs/stm32f746-disco_defconfig          |    6 +
 drivers/video/stm32/stm32_ltdc.c           |  117 +-
 include/configs/stm32f746-disco.h          |   10 +
 include/st_logo_data.h                     | 3267 ++++++++++++++++++++++++++++
 7 files changed, 3453 insertions(+), 35 deletions(-)
 create mode 100644 include/st_logo_data.h

-- 
1.9.1

[U-Boot] [PATCH v2 1/9] video: stm32: stm32_ltdc: add reset

[yannick fertre]

Add reset of LTDC display controller.

Signed-off-by: yannick fertre <yannick.fertre@st.com>
---
 drivers/video/stm32/stm32_ltdc.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c
index b417ac2..d8784f1 100644
--- a/drivers/video/stm32/stm32_ltdc.c
+++ b/drivers/video/stm32/stm32_ltdc.c
@@ -11,6 +11,7 @@
 #include <clk.h>
 #include <dm.h>
 #include <panel.h>
+#include <reset.h>
 #include <video.h>
 #include <asm/io.h>
 #include <asm/arch/gpio.h>
@@ -302,6 +303,7 @@ static int stm32_ltdc_probe(struct udevice *dev)
 	struct stm32_ltdc_priv *priv = dev_get_priv(dev);
 	struct udevice *panel;
 	struct clk pclk, pxclk;
+	struct reset_ctl rst;
 	int ret;
 
 	priv->regs = (void *)dev_read_addr(dev);
@@ -316,6 +318,15 @@ static int stm32_ltdc_probe(struct udevice *dev)
 		return ret;
 	}
 
+	ret = reset_get_by_index(dev, 0, &rst);
+	if (ret) {
+		debug("%s: missing ltdc hardware reset\n", __func__);
+		return -ENODEV;
+	}
+
+	/* Reset */
+	reset_deassert(&rst);
+
 	ret = panel_enable_backlight(panel);
 	if (ret) {
 		debug("%s: panel %s enable backlight error %d\n",
-- 
1.9.1

[U-Boot] [PATCH v2 2/9] video: stm32: stm32_ltdc: update file header & footer

[yannick fertre]

Modified copyright & driver name.

Signed-off-by: yannick fertre <yannick.fertre@st.com>
---
 drivers/video/stm32/stm32_ltdc.c | 17 ++++++++---------
 1 file changed, 8 insertions(+), 9 deletions(-)

diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c
index d8784f1..8d89b58 100644
--- a/drivers/video/stm32/stm32_ltdc.c
+++ b/drivers/video/stm32/stm32_ltdc.c
@@ -1,8 +1,7 @@
 /*
- * Copyright (C) STMicroelectronics SA 2017
- *
- * Authors: Philippe Cornu <philippe.cornu@st.com>
- *          Yannick Fertre <yannick.fertre@st.com>
+ * Copyright (C) 2017-2018 STMicroelectronics - All Rights Reserved
+ * Author(s): Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
+ *	      Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
  *
  * SPDX-License-Identifier: GPL-2.0+
  */
@@ -408,10 +407,10 @@ static const struct udevice_id stm32_ltdc_ids[] = {
 };
 
 U_BOOT_DRIVER(stm32_ltdc) = {
-	.name	= "stm32_ltdc",
-	.id	= UCLASS_VIDEO,
-	.of_match = stm32_ltdc_ids,
-	.probe	= stm32_ltdc_probe,
-	.bind	= stm32_ltdc_bind,
+	.name			= "stm32_display",
+	.id			= UCLASS_VIDEO,
+	.of_match		= stm32_ltdc_ids,
+	.probe			= stm32_ltdc_probe,
+	.bind			= stm32_ltdc_bind,
 	.priv_auto_alloc_size	= sizeof(struct stm32_ltdc_priv),
 };
-- 
1.9.1

[U-Boot] [PATCH v2 3/9] video: stm32: stm32_ltdc: set rate of the pixel clock

[yannick fertre]

pxclk is useless to set pixel clock.

Signed-off-by: yannick fertre <yannick.fertre@st.com>
---
 drivers/video/stm32/stm32_ltdc.c | 52 ++++++++++++++++++++++------------------
 1 file changed, 29 insertions(+), 23 deletions(-)

diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c
index 8d89b58..08e0afc 100644
--- a/drivers/video/stm32/stm32_ltdc.c
+++ b/drivers/video/stm32/stm32_ltdc.c
@@ -301,9 +301,9 @@ static int stm32_ltdc_probe(struct udevice *dev)
 	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
 	struct stm32_ltdc_priv *priv = dev_get_priv(dev);
 	struct udevice *panel;
-	struct clk pclk, pxclk;
+	struct clk pclk;
 	struct reset_ctl rst;
-	int ret;
+	int rate, ret;
 
 	priv->regs = (void *)dev_read_addr(dev);
 	if ((fdt_addr_t)priv->regs == FDT_ADDR_T_NONE) {
@@ -311,9 +311,16 @@ static int stm32_ltdc_probe(struct udevice *dev)
 		return -EINVAL;
 	}
 
-	ret = uclass_first_device(UCLASS_PANEL, &panel);
+	ret = clk_get_by_index(dev, 0, &pclk);
 	if (ret) {
-		debug("%s: panel device error %d\n", __func__, ret);
+		debug("%s: peripheral clock get error %d\n", __func__, ret);
+		return ret;
+	}
+
+	ret = clk_enable(&pclk);
+	if (ret) {
+		debug("%s: peripheral clock enable error %d\n",
+		      __func__, ret);
 		return ret;
 	}
 
@@ -326,6 +333,12 @@ static int stm32_ltdc_probe(struct udevice *dev)
 	/* Reset */
 	reset_deassert(&rst);
 
+	ret = uclass_first_device(UCLASS_PANEL, &panel);
+	if (ret) {
+		debug("%s: panel device error %d\n", __func__, ret);
+		return ret;
+	}
+
 	ret = panel_enable_backlight(panel);
 	if (ret) {
 		debug("%s: panel %s enable backlight error %d\n",
@@ -333,31 +346,24 @@ static int stm32_ltdc_probe(struct udevice *dev)
 		return ret;
 	}
 
-	ret = fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(dev),
-					   0, &priv->timing);
+	ret = fdtdec_decode_display_timing(gd->fdt_blob,
+					   dev_of_offset(dev), 0,
+					   &priv->timing);
 	if (ret) {
-		debug("%s: decode display timing error %d\n", __func__, ret);
+		debug("%s: decode display timing error %d\n",
+		      __func__, ret);
 		return -EINVAL;
 	}
 
-	ret = clk_get_by_name(dev, "pclk", &pclk);
-	if (ret) {
-		debug("%s: peripheral clock get error %d\n", __func__, ret);
-		return ret;
+	rate = clk_set_rate(&pclk, priv->timing.pixelclock.typ);
+	if (rate < 0) {
+		debug("%s: fail to set pixel clock %d hz %d hz\n",
+		      __func__, priv->timing.pixelclock.typ, rate);
+		return rate;
 	}
 
-	ret = clk_enable(&pclk);
-	if (ret) {
-		debug("%s: peripheral clock enable error %d\n", __func__, ret);
-		return ret;
-	}
-
-	/* Verify pixel clock value if any & inform user accordingly */
-	ret = clk_get_by_name(dev, "pxclk", &pxclk);
-	if (!ret) {
-		if (clk_get_rate(&pxclk) != priv->timing.pixelclock.typ)
-			printf("Warning: please adjust ltdc pixel clock\n");
-	}
+	debug("%s: Set pixel clock req %d hz get %d hz\n", __func__,
+	      priv->timing.pixelclock.typ, rate);
 
 	/* TODO Below parameters are hard-coded for the moment... */
 	priv->l2bpp = VIDEO_BPP16;
-- 
1.9.1

[U-Boot] [PATCH v2 4/9] video: stm32: stm32_ltdc: missing set of line interrupt position

[yannick fertre]

Set LIPCR (line interrupt position conf) register with line length.

Signed-off-by: yannick fertre <yannick.fertre@st.com>
---
 drivers/video/stm32/stm32_ltdc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c
index 08e0afc..6c3557b 100644
--- a/drivers/video/stm32/stm32_ltdc.c
+++ b/drivers/video/stm32/stm32_ltdc.c
@@ -219,6 +219,8 @@ static void stm32_ltdc_set_mode(struct stm32_ltdc_priv *priv)
 	val = (total_w << 16) | total_h;
 	clrsetbits_le32(regs + LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val);
 
+	setbits_le32(regs + LTDC_LIPCR, acc_act_h + 1);
+
 	/* Signal polarities */
 	val = 0;
 	debug("%s: timing->flags 0x%08x\n", __func__, timing->flags);
-- 
1.9.1

[U-Boot] [PATCH v2 5/9] video: stm32: stm32_ltdc: set the blending factor

[yannick fertre]

Set the blending factor regarding the pixel format

Signed-off-by: yannick fertre <yannick.fertre@st.com>
---
 drivers/video/stm32/stm32_ltdc.c | 41 ++++++++++++++++++++++++++++++++++------
 1 file changed, 35 insertions(+), 6 deletions(-)

diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c
index 6c3557b..e160c77 100644
--- a/drivers/video/stm32/stm32_ltdc.c
+++ b/drivers/video/stm32/stm32_ltdc.c
@@ -138,7 +138,9 @@ struct stm32_ltdc_priv {
 #define LXCFBLNR_CFBLN	GENMASK(10, 0)	/* Color Frame Buffer Line Number */
 
 #define BF1_PAXCA	0x600		/* Pixel Alpha x Constant Alpha */
+#define BF1_CA		0x400		/* Constant Alpha */
 #define BF2_1PAXCA	0x007		/* 1 - (Pixel Alpha x Constant Alpha) */
+#define BF2_1CA		0x005		/* 1 - Constant Alpha */
 
 enum stm32_ltdc_pix_fmt {
 	PF_ARGB8888 = 0,
@@ -161,11 +163,17 @@ static u32 stm32_ltdc_get_pixel_format(enum video_log2_bpp l2bpp)
 		pf = PF_RGB565;
 		break;
 
+	case VIDEO_BPP32:
+		pf = PF_ARGB8888;
+		break;
+
+	case VIDEO_BPP8:
+		pf = PF_L8;
+		break;
+
 	case VIDEO_BPP1:
 	case VIDEO_BPP2:
 	case VIDEO_BPP4:
-	case VIDEO_BPP8:
-	case VIDEO_BPP32:
 	default:
 		debug("%s: warning %dbpp not supported yet, %dbpp instead\n",
 		      __func__, VNBITS(l2bpp), VNBITS(VIDEO_BPP16));
@@ -178,6 +186,23 @@ static u32 stm32_ltdc_get_pixel_format(enum video_log2_bpp l2bpp)
 	return (u32)pf;
 }
 
+static bool has_alpha(u32 fmt)
+{
+	switch (fmt) {
+	case PF_ARGB8888:
+	case PF_ARGB1555:
+	case PF_ARGB4444:
+	case PF_AL44:
+	case PF_AL88:
+		return true;
+	case PF_RGB888:
+	case PF_RGB565:
+	case PF_L8:
+	default:
+		return false;
+	}
+}
+
 static void stm32_ltdc_enable(struct stm32_ltdc_priv *priv)
 {
 	/* Reload configuration immediately & enable LTDC */
@@ -247,6 +272,7 @@ static void stm32_ltdc_set_layer1(struct stm32_ltdc_priv *priv, ulong fb_addr)
 	u32 line_length;
 	u32 bus_width;
 	u32 val, tmp, bpp;
+	u32 format;
 
 	x0 = priv->crop_x;
 	x1 = priv->crop_x + priv->crop_w - 1;
@@ -277,15 +303,18 @@ static void stm32_ltdc_set_layer1(struct stm32_ltdc_priv *priv, ulong fb_addr)
 	clrsetbits_le32(regs + LTDC_L1CFBLR, LXCFBLR_CFBLL | LXCFBLR_CFBP, val);
 
 	/* Pixel format */
-	val = stm32_ltdc_get_pixel_format(priv->l2bpp);
-	clrsetbits_le32(regs + LTDC_L1PFCR, LXPFCR_PF, val);
+	format = stm32_ltdc_get_pixel_format(priv->l2bpp);
+	clrsetbits_le32(regs + LTDC_L1PFCR, LXPFCR_PF, format);
 
 	/* Constant alpha value */
 	clrsetbits_le32(regs + LTDC_L1CACR, LXCACR_CONSTA, priv->alpha);
 
+	/* Specifies the blending factors : with or without pixel alpha */
+	/* Manage hw-specific capabilities */
+	val = has_alpha(format) ? BF1_PAXCA | BF2_1PAXCA : BF1_CA | BF2_1CA;
+
 	/* Blending factors */
-	clrsetbits_le32(regs + LTDC_L1BFCR, LXBFCR_BF2 | LXBFCR_BF1,
-			BF1_PAXCA | BF2_1PAXCA);
+	clrsetbits_le32(regs + LTDC_L1BFCR, LXBFCR_BF2 | LXBFCR_BF1, val);
 
 	/* Frame buffer line number */
 	clrsetbits_le32(regs + LTDC_L1CFBLNR, LXCFBLNR_CFBLN, priv->crop_h);
-- 
1.9.1

[U-Boot] [PATCH v2 6/9] arm: dts: stm32: add ltdc for STM32F746

[yannick fertre]

From: Philippe CORNU <philippe.cornu@st.com>

Add display controller node in device-tree.

Signed-off-by: yannick fertre <yannick.fertre@st.com>
---
 arch/arm/dts/stm32f746.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
index 46d148e..e4d32bf 100644
--- a/arch/arm/dts/stm32f746.dtsi
+++ b/arch/arm/dts/stm32f746.dtsi
@@ -323,6 +323,15 @@
 			pinctrl-names = "default", "opendrain";
 			max-frequency = <48000000>;
 		};
+
+		ltdc: display-controller at 40016800 {
+			compatible = "st,stm32-ltdc";
+			reg = <0x40016800 0x200>;
+			resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
+			clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
+			u-boot,dm-pre-reloc;
+			status = "disabled";
+		};
 	};
 };
 
-- 
1.9.1

[U-Boot] [PATCH v2 7/9] arm: dts: stm32: add display for STM32F746 disco board

[yannick fertre]

Enable the display controller , panel & backlight.
Set panel display timings & set the RGB data bus.

Signed-off-by: yannick fertre <yannick.fertre@st.com>
---
 arch/arm/dts/stm32f746-disco.dts | 70 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 70 insertions(+)

diff --git a/arch/arm/dts/stm32f746-disco.dts b/arch/arm/dts/stm32f746-disco.dts
index 9e8d2a0..e47f762 100644
--- a/arch/arm/dts/stm32f746-disco.dts
+++ b/arch/arm/dts/stm32f746-disco.dts
@@ -89,6 +89,37 @@
 		compatible = "st,button1";
 		button-gpio = <&gpioi 11 0>;
 	};
+
+	backlight: backlight {
+		compatible = "gpio-backlight";
+		gpios = <&gpiok 3 0>;
+		status = "okay";
+	};
+
+	panel-rgb at 0 {
+		compatible = "simple-panel";
+		backlight = <&backlight>;
+		enable-gpios = <&gpioi 12 0>;
+		status = "okay";
+
+		display-timings {
+			timing at 0 {
+				clock-frequency = <9000000>;
+				hactive = <480>;
+				vactive = <272>;
+				hfront-porch = <2>;
+				hback-porch = <2>;
+				hsync-len = <41>;
+				vfront-porch = <2>;
+				vback-porch = <2>;
+				vsync-len = <10>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <0>;
+				pixelclk-active = <1>;
+			};
+		};
+	};
 };
 
 &clk_hse {
@@ -183,6 +214,40 @@
 			  slew-rate = <2>;
 		};
 	};
+
+	ltdc_pins: ltdc at 0 {
+		pins {
+			pinmux = <STM32F746_PE4_FUNC_LCD_B0>,
+			       <STM32F746_PG12_FUNC_LCD_B4>,
+			       <STM32F746_PI9_FUNC_LCD_VSYNC>,
+			       <STM32F746_PI10_FUNC_LCD_HSYNC>,
+			       <STM32F746_PI14_FUNC_LCD_CLK>,
+			       <STM32F746_PI15_FUNC_LCD_R0>,
+			       <STM32F746_PJ0_FUNC_LCD_R1>,
+			       <STM32F746_PJ1_FUNC_LCD_R2>,
+			       <STM32F746_PJ2_FUNC_LCD_R3>,
+			       <STM32F746_PJ3_FUNC_LCD_R4>,
+			       <STM32F746_PJ4_FUNC_LCD_R5>,
+			       <STM32F746_PJ5_FUNC_LCD_R6>,
+			       <STM32F746_PJ6_FUNC_LCD_R7>,
+			       <STM32F746_PJ7_FUNC_LCD_G0>,
+			       <STM32F746_PJ8_FUNC_LCD_G1>,
+			       <STM32F746_PJ9_FUNC_LCD_G2>,
+			       <STM32F746_PJ10_FUNC_LCD_G3>,
+			       <STM32F746_PJ11_FUNC_LCD_G4>,
+			       <STM32F746_PJ13_FUNC_LCD_B1>,
+			       <STM32F746_PJ14_FUNC_LCD_B2>,
+			       <STM32F746_PJ15_FUNC_LCD_B3>,
+			       <STM32F746_PK0_FUNC_LCD_G5>,
+			       <STM32F746_PK1_FUNC_LCD_G6>,
+			       <STM32F746_PK2_FUNC_LCD_G7>,
+			       <STM32F746_PK4_FUNC_LCD_B5>,
+			       <STM32F746_PK5_FUNC_LCD_B6>,
+			       <STM32F746_PK6_FUNC_LCD_B7>,
+			       <STM32F746_PK7_FUNC_LCD_DE>;
+			slew-rate = <2>;
+		};
+	};
 };
 
 &usart1 {
@@ -250,3 +315,8 @@
 	bus-width = <4>;
 	max-frequency = <25000000>;
 };
+
+&ltdc {
+	status = "okay";
+	pinctrl-0 = <&ltdc_pins>;
+};
-- 
1.9.1

[U-Boot] [PATCH v2 8/9] stm32f7: board: add splash screen

[yannick fertre]

Support several pixel format (8bits, 16bits, 24bits & 32bits).
Add new file st_logo_data.h which contains logo
stmicroelectronics_uboot_logo_8bit_rle.bmp.

Signed-off-by: yannick fertre <yannick.fertre@st.com>
---
 board/st/stm32f746-disco/stm32f746-disco.c |    9 +
 include/configs/stm32f746-disco.h          |   10 +
 include/st_logo_data.h                     | 3267 ++++++++++++++++++++++++++++
 3 files changed, 3286 insertions(+)
 create mode 100644 include/st_logo_data.h

diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c
index 8da7028..ae4539f 100644
--- a/board/st/stm32f746-disco/stm32f746-disco.c
+++ b/board/st/stm32f746-disco/stm32f746-disco.c
@@ -7,8 +7,12 @@
 
 #include <common.h>
 #include <dm.h>
+#include <lcd.h>
 #include <ram.h>
 #include <spl.h>
+#include <splash.h>
+#include <st_logo_data.h>
+#include <video.h>
 #include <asm/io.h>
 #include <asm/armv7m.h>
 #include <asm/arch/stm32.h>
@@ -155,5 +159,10 @@ int board_init(void)
 	STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL;
 #endif
 
+#if defined(CONFIG_CMD_BMP)
+	bmp_display((ulong)stmicroelectronics_uboot_logo_8bit_rle,
+		    BMP_ALIGN_CENTER, BMP_ALIGN_CENTER);
+#endif /* CONFIG_CMD_BMP */
+
 	return 0;
 }
diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h
index 3e952c2..6f0b722 100644
--- a/include/configs/stm32f746-disco.h
+++ b/include/configs/stm32f746-disco.h
@@ -85,4 +85,14 @@
 #endif
 /* For SPL ends */
 
+/* For splashcreen */
+#ifdef CONFIG_DM_VIDEO
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_BMP_16BPP
+#define CONFIG_BMP_24BPP
+#define CONFIG_BMP_32BPP
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#endif
+
 #endif /* __CONFIG_H */
diff --git a/include/st_logo_data.h b/include/st_logo_data.h
new file mode 100644
index 0000000..4d3a26e
--- /dev/null
+++ b/include/st_logo_data.h
@@ -0,0 +1,3267 @@
+/*
+ * Copyright (C) 2018 STMicroelectronics - All Rights Reserved
+ * Author(s): Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
+ *	      Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+/*
+ * file generated from picture
+ * tools/logos/stmicroelectronics_uboot_logo_8bit_rle.bmp
+ */
+
+unsigned char stmicroelectronics_uboot_logo_8bit_rle[] = {
+0x42, 0x4d, 0x5c, 0x98, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7a, 0x04,
+0x00, 0x00, 0x6c, 0x00, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0x60, 0x01,
+0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x01, 0x00, 0x00, 0x00, 0xe2, 0x93,
+0x00, 0x00, 0x13, 0x0b, 0x00, 0x00, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x01,
+0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x42, 0x47, 0x52, 0x73, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0xff, 0xff, 0xff, 0x00, 0xae, 0x82, 0x3a, 0x00, 0xa5, 0x7b,
+0x37, 0x00, 0xfe, 0xfe, 0xfe, 0x00, 0xac, 0x80, 0x39, 0x00, 0x4e, 0x1b,
+0x02, 0x00, 0xb7, 0x88, 0x3b, 0x00, 0x4f, 0x1c, 0x02, 0x00, 0xb3, 0x85,
+0x3a, 0x00, 0xe1, 0xaa, 0x35, 0x00, 0x86, 0x62, 0x1f, 0x00, 0x65, 0x4a,
+0x13, 0x00, 0xa9, 0x7e, 0x38, 0x00, 0xff, 0xfe, 0xff, 0x00, 0x77, 0x55,
+0x13, 0x00, 0xbe, 0x91, 0x47, 0x00, 0xbc, 0x8d, 0x3d, 0x00, 0xfe, 0xfd,
+0xfd, 0x00, 0xa3, 0x7a, 0x38, 0x00, 0xbd, 0x8e, 0x42, 0x00, 0xa7, 0x7d,
+0x39, 0x00, 0x72, 0x52, 0x14, 0x00, 0xbc, 0x8d, 0x40, 0x00, 0x84, 0x60,
+0x1e, 0x00, 0xba, 0x8a, 0x3c, 0x00, 0x75, 0x53, 0x13, 0x00, 0x87, 0x62,
+0x11, 0x00, 0x85, 0x60, 0x10, 0x00, 0x7e, 0x5b, 0x12, 0x00, 0xb4, 0x86,
+0x3a, 0x00, 0x8c, 0x6a, 0x35, 0x00, 0xb1, 0x84, 0x3b, 0x00, 0xaa, 0x7f,
+0x3a, 0x00, 0xbc, 0x8c, 0x3c, 0x00, 0x85, 0x64, 0x34, 0x00, 0xb9, 0x89,
+0x3b, 0x00, 0x93, 0x69, 0x0e, 0x00, 0x8d, 0x65, 0x0e, 0x00, 0xfd, 0xfd,
+0xfc, 0x00, 0xa0, 0x78, 0x37, 0x00, 0x81, 0x5d, 0x12, 0x00, 0x9e, 0x76,
+0x36, 0x00, 0xbe, 0x90, 0x45, 0x00, 0x94, 0x6a, 0x0b, 0x00, 0x8b, 0x64,
+0x10, 0x00, 0x68, 0x4c, 0x14, 0x00, 0x8b, 0x69, 0x35, 0x00, 0x82, 0x5e,
+0x11, 0x00, 0x90, 0x6c, 0x35, 0x00, 0x89, 0x63, 0x0f, 0x00, 0xaf, 0x83,
+0x39, 0x00, 0xa2, 0x75, 0x06, 0x00, 0x96, 0x6b, 0x0d, 0x00, 0x7b, 0x59,
+0x12, 0x00, 0x9c, 0x70, 0x08, 0x00, 0x99, 0x73, 0x37, 0x00, 0xb0, 0x83,
+0x39, 0x00, 0x84, 0x60, 0x11, 0x00, 0x80, 0x5c, 0x14, 0x00, 0x91, 0x68,
+0x0c, 0x00, 0x6a, 0x4d, 0x14, 0x00, 0xc3, 0x99, 0x54, 0x00, 0x92, 0x6e,
+0x36, 0x00, 0x9a, 0x6e, 0x0b, 0x00, 0x8a, 0x68, 0x34, 0x00, 0xc0, 0x94,
+0x4b, 0x00, 0x98, 0x6c, 0x09, 0x00, 0x8f, 0x67, 0x0f, 0x00, 0x82, 0x62,
+0x34, 0x00, 0x7d, 0x5a, 0x15, 0x00, 0xc5, 0x9f, 0x5f, 0x00, 0xbb, 0x8b,
+0x3b, 0x00, 0xc8, 0xa7, 0x6a, 0x00, 0xc0, 0x95, 0x4e, 0x00, 0x87, 0x66,
+0x34, 0x00, 0x9f, 0x72, 0x06, 0x00, 0xbf, 0x93, 0x49, 0x00, 0xfd, 0xfb,
+0xfc, 0x00, 0xc7, 0xa4, 0x66, 0x00, 0x7a, 0x57, 0x13, 0x00, 0xc4, 0x9d,
+0x5a, 0x00, 0x83, 0x5f, 0x13, 0x00, 0x9c, 0x75, 0x36, 0x00, 0x7f, 0x60,
+0x32, 0x00, 0xb5, 0x87, 0x3c, 0x00, 0xc3, 0x9b, 0x57, 0x00, 0xc8, 0xa5,
+0x69, 0x00, 0x72, 0x55, 0x25, 0x00, 0xb9, 0x8a, 0x3a, 0x00, 0x94, 0x70,
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+0x37, 0x00, 0x6c, 0x4e, 0x14, 0x00, 0xc5, 0x9e, 0x5d, 0x00, 0xca, 0xa9,
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+0x58, 0x00, 0xb5, 0x97, 0x60, 0x00, 0x92, 0x75, 0x41, 0x00, 0x6f, 0x51,
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+0x00, 0x00, 0xad, 0x9c, 0x81, 0x00, 0xd1, 0xbc, 0x9a, 0x00, 0x84, 0x64,
+0x2c, 0x00, 0x6e, 0x53, 0x25, 0x00, 0xf2, 0xee, 0xeb, 0x00, 0xbe, 0xa0,
+0x69, 0x00, 0xd5, 0xbf, 0x9b, 0x00, 0xba, 0x99, 0x5c, 0x00, 0x5a, 0x2a,
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+0x29, 0x00, 0xd6, 0xcb, 0xc4, 0x00, 0xe4, 0xdc, 0xd7, 0x00, 0x6f, 0x45,
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+0xbf, 0x00, 0xdc, 0xd2, 0xc8, 0x00, 0xe0, 0xd7, 0xd0, 0x00, 0xe9, 0xbf,
+0x68, 0x00, 0x9d, 0x7d, 0x43, 0x00, 0x5f, 0x31, 0x19, 0x00, 0xb3, 0x9d,
+0x92, 0x00, 0xb8, 0x8a, 0x40, 0x00, 0x9e, 0x82, 0x4f, 0x00, 0x92, 0x6d,
+0x2e, 0x00, 0x65, 0x4a, 0x11, 0x00, 0x97, 0x7b, 0x48, 0x00, 0xbf, 0x93,
+0x41, 0x00, 0x7d, 0x57, 0x44, 0x00, 0x80, 0x5c, 0x02, 0x00, 0x83, 0x5f,
+0x4e, 0x00, 0x97, 0x71, 0x30, 0x00, 0xab, 0x89, 0x4d, 0x00, 0x9d, 0x81,
+0x73, 0x00, 0x87, 0x64, 0x24, 0x00, 0x90, 0x70, 0x61, 0x00, 0xc6, 0xb5,
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+0x26, 0x00, 0xe3, 0xb1, 0x45, 0x00, 0x9c, 0x74, 0x2e, 0x00, 0x7a, 0x57,
+0x01, 0x00, 0xc2, 0xa4, 0x6e, 0x00, 0x86, 0x60, 0x01, 0x00, 0x60, 0x41,
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+0x17, 0x00, 0xf8, 0xf1, 0xe4, 0x00, 0x73, 0x53, 0x0c, 0x00, 0xa7, 0x91,
+0x6b, 0x00, 0xa9, 0x78, 0x04, 0x00, 0xc1, 0xaf, 0xa6, 0x00, 0xac, 0x93,
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+0x75, 0x00, 0xb8, 0xa5, 0x96, 0x00, 0x93, 0x68, 0x01, 0x00, 0xbb, 0x8d,
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+0xd8, 0x00, 0xeb, 0xe0, 0xd1, 0x00, 0xf4, 0xdf, 0xb3, 0x00, 0xe2, 0xad,
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+0x06, 0x00, 0x01, 0x03, 0x4e, 0x00, 0x00, 0x09, 0x26, 0x9b, 0x05, 0x07,
+0x05, 0x98, 0x7c, 0x00, 0x03, 0x00, 0x0e, 0x00, 0x00, 0x06, 0x6b, 0xa4,
+0x07, 0x07, 0x05, 0x87, 0x93, 0x00, 0x01, 0x03, 0x5c, 0x00, 0x00, 0x00,
+0x1f, 0x00, 0x01, 0x03, 0x0f, 0x00, 0x00, 0x03, 0x03, 0x00, 0x03, 0x00,
+0x0f, 0x00, 0x01, 0x03, 0x01, 0x03, 0x0f, 0x00, 0x01, 0x03, 0x0a, 0x00,
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+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
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+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x01
+};
+
-- 
1.9.1

[U-Boot] [PATCH v2 9/9] board: Add display to STM32F746 SoC discovery board

[yannick fertre]

Signed-off-by: yannick fertre <yannick.fertre@st.com>
---
 configs/stm32f746-disco_defconfig | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig
index f8fa198..0bc9c01 100644
--- a/configs/stm32f746-disco_defconfig
+++ b/configs/stm32f746-disco_defconfig
@@ -28,6 +28,7 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_CMD_DNS=y
 CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_BMP=y
 CONFIG_CMD_TIMER=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
@@ -52,5 +53,10 @@ CONFIG_ETH_DESIGNWARE=y
 # CONFIG_PINCTRL_FULL is not set
 CONFIG_DM_SPI=y
 CONFIG_STM32_QSPI=y
+CONFIG_DM_VIDEO=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_VIDEO_STM32=y
+CONFIG_VIDEO_STM32_MAX_XRES=480
+CONFIG_VIDEO_STM32_MAX_YRES=640
 CONFIG_OF_LIBFDT_OVERLAY=y
 # CONFIG_EFI_LOADER is not set
-- 
1.9.1

[U-Boot] [PATCH v2 0/9] splash screen on the stm32f746 disco board

[Anatolij Gustschin]

On Fri, 2 Mar 2018 15:59:20 +0100
yannick fertre yannick.fertre at st.com wrote:

> Version 2:
> - Add patch to display bitmap stmicroelectronics_uboot_logo_8bit_rle
> - Add patch to defconfig to add splash screen
> - Rename panel in dts.
> 
> Version 1:
> - Initial commit
> 
> This serie contains all patchsets needed for displaying a splash screen 
> on the stm32f746 disco board & some display features (reset, blending & line
> interrupt position).
> 
> Philippe CORNU (1):
>   arm: dts: stm32: add ltdc for STM32F746
> 
> yannick fertre (8):
>   video: stm32: stm32_ltdc: add reset
>   video: stm32: stm32_ltdc: update file header & footer
>   video: stm32: stm32_ltdc: set rate of the pixel clock
>   video: stm32: stm32_ltdc: missing set of line interrupt position
>   video: stm32: stm32_ltdc: set the blending factor
>   arm: dts: stm32: add display for STM32F746 disco board
>   stm32f7: board: add splash screen
>   board: Add display to STM32F746 SoC discovery board

Series applied to u-boot-video/next, thanks!

--
Anatolij