From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tom Rini Date: Thu, 22 Mar 2018 16:35:02 -0400 Subject: [U-Boot] davinci: omapl138_lcdk: fix PLL0 frequency In-Reply-To: <1521077790-17411-1-git-send-email-david@lechnology.com> References: <1521077790-17411-1-git-send-email-david@lechnology.com> Message-ID: <20180322203502.GK4759@bill-the-cat.ec.rr.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Wed, Mar 14, 2018 at 08:36:30PM -0500, David Lechner wrote: > commit 1601dd97edc6 ("davinci: omapl138_lcdk: increase PLL0 frequency") > changed the PLL0 frequency to 456MHz, which is needed for the LCDC IP > block. However, in doing so, it caused the PLLOUT clock to be outside > of the allowable specifications given in the OMAP-L138 data sheet. (It > says PLLOUT must be 600MHz max). It also uses a PLLM value outside of > the range given in the TRM (it says PLLM must in the range 0 to 0x1f). > > So here is what we have currently: > > PLLOUT = 24 / (0 + 1) * (37 + 1) = 912MHz (out of spec) > ^ ^ ^ > CLKIN PREDIV PLLM (out of spec) > > input to PLLDIVn = 912 / (1 + 1) = 456MHz (desired result) > ^ ^ > PLLOUT POSTDIV > > This changes the PLLM value to 18 and the POSTDIV value to 0 so that > PLLOUT is now within specification but we still get the desired > result. > > PLLOUT = 24 / (0 + 1) * (18 + 1) = 456MHz (within spec) > ^ ^ ^ > CLKIN PREDIV PLLM > > input to PLLDIVn = 456 / (0 + 1) = 456MHz (desired result) > ^ ^ > PLLOUT POSTDIV > > Fixes: 1601dd97edc6 ("davinci: omapl138_lcdk: increase PLL0 frequency") > Signed-off-by: David Lechner > Reported-by: Sekhar Nori > Tested-by: Sekhar Nori Applied to u-boot/master, thanks! -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: not available URL: