From: Ivan Gorinov <ivan.gorinov@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2] timer: add High Precision Event Timers (HPET) support
Date: Mon, 2 Apr 2018 16:00:47 -0700 [thread overview]
Message-ID: <20180402230047.GA60614@intel.com> (raw)
In-Reply-To: <CAHp75Ve-209jvrjVC5_u3AkX+4uBD2Xwg2SLthJ1SMWWNBotSg@mail.gmail.com>
On Sat, Mar 31, 2018 at 06:31:03AM -0600, Andy Shevchenko wrote:
> >> > + tl = readl(regs + HPET_MAIN_COUNT_L);
> >> > + th = readl(regs + HPET_MAIN_COUNT_H);
> >>
> >> Ditto.
> >
> > If readq() is defined as two read operations in 32-bit code, main counter
> > rollover (low part overflow, high part increment) can happen between them.
>
> And how this contradicts ther current code?
It just does not make the code simpler, rollover check is
still required if U-Boot is compiled as 32-bit code.
Can we do something like the following?
#ifdef CONFIG_X86_64
static u64 read_main_counter(void *regs)
{
return readq(regs + HPET_MAIN_COUNT);
}
#else
/*
* Read the main counter as two 32-bit registers,
* repeat if rollover happens.
*/
static u64 read_main_counter(void *regs)
{
u64 now_tick;
u32 tl, th, th0;
th = readl(regs + HPET_MAIN_COUNT_H);
do {
th0 = th;
tl = readl(regs + HPET_MAIN_COUNT_L);
th = readl(regs + HPET_MAIN_COUNT_H);
now_tick = th;
now_tick <<= 32;
now_tick |= tl;
} while (th != th0);
return now_tick;
}
#endif
next prev parent reply other threads:[~2018-04-02 23:00 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-29 22:29 [U-Boot] [PATCH v2] timer: add High Precision Event Timers (HPET) support Ivan Gorinov
2018-03-30 9:52 ` Bin Meng
2018-03-30 19:46 ` Andy Shevchenko
2018-03-31 1:03 ` Ivan Gorinov
2018-03-31 12:31 ` Andy Shevchenko
2018-04-02 23:00 ` Ivan Gorinov [this message]
2018-04-03 12:17 ` Andy Shevchenko
2018-04-03 23:26 ` Ivan Gorinov
2018-04-04 4:15 ` Bin Meng
2018-04-04 4:40 ` Ivan Gorinov
2018-04-06 13:56 ` Andy Shevchenko
2018-04-06 13:55 ` Andy Shevchenko
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