From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ivan Gorinov <ivan.gorinov@intel.com>
Date: Mon, 2 Apr 2018 16:00:47 -0700
Subject: [U-Boot] [PATCH v2] timer: add High Precision Event Timers
 (HPET) support
In-Reply-To: <CAHp75Ve-209jvrjVC5_u3AkX+4uBD2Xwg2SLthJ1SMWWNBotSg@mail.gmail.com>
References: <20180329222959.GA7323@intel.com>
 <CAHp75Vf9A7kMWDr_ndkCU1zyOqHPG6mgNqyV1CU71j0T0HDL=g@mail.gmail.com>
 <20180331010301.GB45891@intel.com>
 <CAHp75Ve-209jvrjVC5_u3AkX+4uBD2Xwg2SLthJ1SMWWNBotSg@mail.gmail.com>
Message-ID: <20180402230047.GA60614@intel.com>
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On Sat, Mar 31, 2018 at 06:31:03AM -0600, Andy Shevchenko wrote:
> >> > +               tl = readl(regs + HPET_MAIN_COUNT_L);
> >> > +               th = readl(regs + HPET_MAIN_COUNT_H);
> >>
> >> Ditto.
> >
> > If readq() is defined as two read operations in 32-bit code, main counter
> > rollover (low part overflow, high part increment) can happen between them.
> 
> And how this contradicts ther current code?

It just does not make the code simpler, rollover check is
still required if U-Boot is compiled as 32-bit code.

Can we do something like the following?


#ifdef CONFIG_X86_64

static u64 read_main_counter(void *regs)
{
	return readq(regs + HPET_MAIN_COUNT);
}

#else

/*
 * Read the main counter as two 32-bit registers,
 * repeat if rollover happens.
 */
static u64 read_main_counter(void *regs)
{
	u64 now_tick;
	u32 tl, th, th0;

	th = readl(regs + HPET_MAIN_COUNT_H);
	do {
		th0 = th;
		tl = readl(regs + HPET_MAIN_COUNT_L);
		th = readl(regs + HPET_MAIN_COUNT_H);
		now_tick = th;
		now_tick <<= 32;
		now_tick |= tl;
	} while (th != th0);

	return now_tick;
}

#endif