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From: Ivan Gorinov <ivan.gorinov@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2] timer: add High Precision Event Timers (HPET) support
Date: Tue, 3 Apr 2018 21:40:16 -0700	[thread overview]
Message-ID: <20180404044016.GA19408@intel.com> (raw)
In-Reply-To: <CAEUhbmU5_jdeACfh1WdwBWueZ95EVUt=eOGwkH2Z=-Uzi8xUxw@mail.gmail.com>

On Wed, Apr 04, 2018 at 12:15:24PM +0800, Bin Meng wrote:
> > Doesn't readX/writeX imply a single I/O operation?
> > It may be misleading to define it as two.
> >
> > Assuming MMX or SSE2 to be supported by all x86 processors, 64-bit I/O
> > registers can be accessed as a single operation even in 32-bit code:
> >
> 
> Adding such requirement (MMX or SSE2) to U-Boot is not good. Why do we
> require MMX or SSE2 for readq? Can we use general purpose registers?

In 32-bit code, we can't make a 64-bit memory read operation using only
general purpose registers.

> 
> > static inline u64 readq(void *addr)
> > {
> >         u64 value;
> >
> >         asm volatile ("movq (%0), %%xmm0" : : "r" (addr));
> >         asm volatile ("movq %%xmm0, %0" : "=m" (value));
> >
> >         return value;
> > }
> >
> > I can add these definitions to "asm/io.h".

  reply	other threads:[~2018-04-04  4:40 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-29 22:29 [U-Boot] [PATCH v2] timer: add High Precision Event Timers (HPET) support Ivan Gorinov
2018-03-30  9:52 ` Bin Meng
2018-03-30 19:46 ` Andy Shevchenko
2018-03-31  1:03   ` Ivan Gorinov
2018-03-31 12:31     ` Andy Shevchenko
2018-04-02 23:00       ` Ivan Gorinov
2018-04-03 12:17         ` Andy Shevchenko
2018-04-03 23:26           ` Ivan Gorinov
2018-04-04  4:15             ` Bin Meng
2018-04-04  4:40               ` Ivan Gorinov [this message]
2018-04-06 13:56                 ` Andy Shevchenko
2018-04-06 13:55             ` Andy Shevchenko

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