From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ivan Gorinov <ivan.gorinov@intel.com>
Date: Tue, 3 Apr 2018 21:40:16 -0700
Subject: [U-Boot] [PATCH v2] timer: add High Precision Event Timers
 (HPET) support
In-Reply-To: <CAEUhbmU5_jdeACfh1WdwBWueZ95EVUt=eOGwkH2Z=-Uzi8xUxw@mail.gmail.com>
References: <20180329222959.GA7323@intel.com>
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 <20180331010301.GB45891@intel.com>
 <CAHp75Ve-209jvrjVC5_u3AkX+4uBD2Xwg2SLthJ1SMWWNBotSg@mail.gmail.com>
 <20180402230047.GA60614@intel.com>
 <CAHp75Ve-o0snErfyRt=Z2-GSY8e-zAoPWe3S+D=+y0rmM0b5Lw@mail.gmail.com>
 <20180403232647.GA64065@intel.com>
 <CAEUhbmU5_jdeACfh1WdwBWueZ95EVUt=eOGwkH2Z=-Uzi8xUxw@mail.gmail.com>
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On Wed, Apr 04, 2018 at 12:15:24PM +0800, Bin Meng wrote:
> > Doesn't readX/writeX imply a single I/O operation?
> > It may be misleading to define it as two.
> >
> > Assuming MMX or SSE2 to be supported by all x86 processors, 64-bit I/O
> > registers can be accessed as a single operation even in 32-bit code:
> >
> 
> Adding such requirement (MMX or SSE2) to U-Boot is not good. Why do we
> require MMX or SSE2 for readq? Can we use general purpose registers?

In 32-bit code, we can't make a 64-bit memory read operation using only
general purpose registers.

> 
> > static inline u64 readq(void *addr)
> > {
> >         u64 value;
> >
> >         asm volatile ("movq (%0), %%xmm0" : : "r" (addr));
> >         asm volatile ("movq %%xmm0, %0" : "=m" (value));
> >
> >         return value;
> > }
> >
> > I can add these definitions to "asm/io.h".