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From: Chris Packham <judge.packham@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2 6/6] ARM: mvebu: a38x: use non-zero size for ddr scrubbing
Date: Mon,  9 Apr 2018 22:12:57 +1200	[thread overview]
Message-ID: <20180409101257.3899-7-judge.packham@gmail.com> (raw)
In-Reply-To: <20180409101257.3899-1-judge.packham@gmail.com>

From: Chris Packham <chris.packham@alliedtelesis.co.nz>

Make ddr3_calc_mem_cs_size() global scope and use it in
ddr3_new_tip_ecc_scrub to correctly initialize all of DDR memory.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
---
This has been reported upstream at
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/6 

Changes in v2: New

 drivers/ddr/marvell/a38x/mv_ddr_plat.c | 2 +-
 drivers/ddr/marvell/a38x/mv_ddr_plat.h | 1 +
 drivers/ddr/marvell/a38x/xor.c         | 3 +++
 3 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/ddr/marvell/a38x/mv_ddr_plat.c b/drivers/ddr/marvell/a38x/mv_ddr_plat.c
index 1ab72e36189e..5a527b67a84d 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_plat.c
+++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.c
@@ -996,7 +996,7 @@ static u32 ddr3_get_device_size(u32 cs)
 	}
 }
 
-static int ddr3_calc_mem_cs_size(u32 cs, uint64_t *cs_size)
+int ddr3_calc_mem_cs_size(u32 cs, uint64_t *cs_size)
 {
 	u32 cs_mem_size;
 
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_plat.h b/drivers/ddr/marvell/a38x/mv_ddr_plat.h
index 73e54c4b735c..8ea3c8b5c48d 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_plat.h
+++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.h
@@ -233,4 +233,5 @@ u32 mv_ddr_dm_pad_get(void);
 int mv_ddr_pre_training_fixup(void);
 int mv_ddr_post_training_fixup(void);
 int mv_ddr_manual_cal_do(void);
+int ddr3_calc_mem_cs_size(u32 cs, uint64_t *cs_size);
 #endif /* _MV_DDR_PLAT_H */
diff --git a/drivers/ddr/marvell/a38x/xor.c b/drivers/ddr/marvell/a38x/xor.c
index 368432165fa3..d2f90449d5ed 100644
--- a/drivers/ddr/marvell/a38x/xor.c
+++ b/drivers/ddr/marvell/a38x/xor.c
@@ -348,6 +348,9 @@ void ddr3_new_tip_ecc_scrub(void)
 	for (cs_c = 0; cs_c < max_cs; cs_c++)
 		cs_ena |= 1 << cs_c;
 
+	/* assume that all CS have same size */
+	ddr3_calc_mem_cs_size(0, &cs_mem_size);
+
 	mv_sys_xor_init(max_cs, cs_ena, cs_mem_size, 0);
 	total_mem_size = max_cs * cs_mem_size;
 	mv_xor_mem_init(0, 0, total_mem_size, 0xdeadbeef, 0xdeadbeef);
-- 
2.16.2

  parent reply	other threads:[~2018-04-09 10:12 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-04-09 10:12 [U-Boot] [PATCH v2 0/6] ARM: mvebu: a38x: updates to ddr training code Chris Packham
2018-04-09 10:12 ` [U-Boot] [PATCH v2 1/6] ARM: mvebu: a38x: move definition of PEX_CFG_DIRECT_ACCESS Chris Packham
2018-04-09 10:12 ` [U-Boot] [PATCH v2 2/6] ARM: mvebu: a38x: move sys_env_device_rev_get Chris Packham
2018-04-09 10:12 ` [U-Boot] [PATCH v2 3/6] ARM: mvebu: a38x: remove some unused code Chris Packham
2018-04-09 10:12 ` [U-Boot] [PATCH v2 4/6] ARM: mvebu: a38x: sync ddr training code with upstream Chris Packham
2018-04-09 10:12 ` [U-Boot] [PATCH v2 5/6] ARM: mvebu: a38x: restore support for setting timing Chris Packham
2018-04-09 10:12 ` Chris Packham [this message]
2018-05-09 10:23 ` [U-Boot] [PATCH v2 0/6] ARM: mvebu: a38x: updates to ddr training code Stefan Roese

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