[U-Boot] [PATCH v2 4/5] sunxi: R40: add gigabit ethernet devicetree node

[Maxime Ripard <maxime.ripard@bootlin.com>]

On Tue, Apr 17, 2018 at 03:42:34PM +0200, Lothar Felten wrote:
> Add a device tree node for the Allwinner R40/V40 CPU.
> The syscon node is required by the gmac driver.
> 
> Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
> ---
>  arch/arm/dts/sun8i-r40.dtsi | 28 ++++++++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
> 
> diff --git a/arch/arm/dts/sun8i-r40.dtsi b/arch/arm/dts/sun8i-r40.dtsi
> index ee22f6eb3a..93bf811014 100644
> --- a/arch/arm/dts/sun8i-r40.dtsi
> +++ b/arch/arm/dts/sun8i-r40.dtsi
> @@ -114,6 +114,12 @@
>  		#size-cells = <1>;
>  		ranges;
>  
> +		syscon: syscon at 1c00000 {
> +			compatible = "allwinner,sun8i-r40-system-controller",
> +				"syscon";
> +			reg = <0x01c00000 0x1000>;
> +		};

As far as I understood it, the GMAC configuration register is not in
the system controller on the R40, but in the clock controller.

> +
>  		pio: pinctrl at 1c20800 {
>  			compatible = "allwinner,sun8i-r40-pinctrl";
>  			reg = <0x01c20800 0x400>;
> @@ -168,6 +174,28 @@
>  			#size-cells = <0>;
>  		};
>  
> +		gmac: ethernet at 01c50000 {
> +			compatible = "allwinner,sun8i-h3-emac";
> +			syscon = <&syscon>;
> +			reg = <0x01c50000 0x2000>;
> +			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "macirq";
> +			clocks = <&osc24M>, <&osc24M>;
> +			clock-names = "stmmaceth", "allwinner_gmac_tx";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&gmac_pins_rgmii>;
> +			phy-mode = "rgmii";
> +			status = "disabled";
> +
> +			mdio: mdio {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				compatible = "snps,dwmac-mdio";
> +			};
> +		};
> +

And I guess this is just some temporary binding while waiting for
"real" ones to land in Linux?

Maxime

-- 
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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